Chip testing system

Abstract

The utility model provides a chip testing system, and belongs to the technical field of chip testing. The chip testing system comprises a sorting temperature testing device and a chip parameter testing device. And the sorting temperature testing device is used for positioning the tested chip and adjusting a plurality of working environment temperatures of the tested chip. The chip parameter testing device is used for being connected with a tested chip, and the chip parameter testing device is used for carrying out direct current parameter testing, time parameter testing and radio frequency parameter testing on the tested chip at each working environment temperature. And the sorting temperature testing device is connected with the chip parameter testing device and is used for sorting the tested chips according to the direct current parameter testing result, the time parameter testing result and the radio frequency parameter testing result. The chip test system provided by the utility model does not need to depend on different temperature test platforms to carry out temperature switching test, and does not need to carry out step-by-step function test among a plurality of function test platforms, so that the test efficiency of the chip is improved.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of chip testing, and particularly relates to a chip testing system. BACKGROUND

[0002] With the success of global networking, the international application space of the Beidou satellite navigation system in the future will continue to expand. The Beidou navigation satellite chip is a hardware device specially designed to receive and process Beidou satellite signals. These chips contain precise receivers, processors and algorithms inside, which can calculate the precise position, speed and time information of the device from the signals sent by the Beidou satellite system. Beidou navigation satellite chips are widely used in logistics, transportation, intelligent transportation, power and other fields.

[0003] The testing of the Beidou navigation satellite chip is an important link to ensure the quality of the chip in the chip manufacturing process, and is of great significance to the quality and reliability of the product. By testing the chip, it can be verified whether the produced chip meets the requirements. However, at present, when testing the Beidou navigation satellite chip, multiple test platforms are needed to test step by step, the testing process is complex, and thus the testing efficiency is low. CONTENT OF THE INVENTION

[0004] The purpose of the present application is to provide a chip testing system, which aims to solve the problem of low testing efficiency caused by using multiple test platforms to test step by step in the traditional testing of the Beidou navigation satellite chip.

[0005] The present application provides a chip testing system, comprising:

[0006] A sorting temperature testing device is used for positioning the tested chip and adjusting the working environment temperature of the tested chip.

[0007] A chip parameter testing device is used for connecting with the tested chip, and the chip parameter testing device is used for testing the direct current parameter, the time parameter and the radio frequency parameter of the tested chip under each working environment temperature.

[0008] The sorting temperature testing device is connected with the chip parameter testing device, and is used for sorting the tested chip according to the results of the direct current parameter test, the time parameter test and the radio frequency parameter test.

[0009] In one embodiment, the chip parameter testing device comprises:

[0010] A parameter testing module is connected with the multiple pins of the tested chip, and is used for testing the current and voltage of the multiple pins of the tested chip.

[0011] The parameter test module is connected with the power pin of the chip under test, and is used for pressurizing and measuring the current of the power pin of the chip under test.

[0012] In one embodiment, the chip parameter test device further comprises:

[0013] A voltage stabilizer is connected with the parameter test hardware module of the parameter test module, and is used for stabilizing the voltage provided by the parameter test module and outputting a supply voltage.

[0014] An active crystal oscillator is connected with the voltage stabilizer, and an output end of the active crystal oscillator is connected with the external crystal input pin of the chip under test, and is used for providing the input frequency signal required by the frequency stability test in the time parameter test.

[0015] In one embodiment, the chip parameter test device further comprises:

[0016] A first frequency generation module is connected with the external crystal input pin of the chip under test, and is used for providing the input frequency signal required by the frequency stability test in the time parameter test.

[0017] In one embodiment, the chip parameter test device further comprises:

[0018] A frequency transceiver module is connected with the frequency output pin of the chip under test, and is used for measuring the output frequency of the chip under test.

[0019] In one embodiment, the frequency transceiver module is connected with the parameter test control module of the parameter test module, and is used for measuring the output frequency of the chip under test according to the frequency test instruction sent by the parameter test control module, and sending the output frequency to the parameter test control module.

[0020] In one embodiment, the frequency transceiver module is further used for outputting a radio frequency signal to the radio frequency input pin of the chip under test according to the radio frequency parameter test instruction sent by the parameter test control module.

[0021] In one embodiment, the chip parameter test device further comprises:

[0022] An impedance matching circuit is connected with the frequency transceiver module and the radio frequency input pin of the chip under test respectively, and is used for impedance matching of the circuit of the radio frequency parameter test.

[0023] In one embodiment, the impedance matching circuit comprises:

[0024] A connector is connected with the frequency transceiver module, and is used for leading the radio frequency signal transmitted by the frequency transceiver module into the impedance matching circuit.

[0025] An operational amplifier is connected with the connector, and an output end of the operational amplifier is connected with the radio frequency input pin of the measured chip.

[0026] In one embodiment, the chip parameter testing device further comprises:

[0027] A passive crystal oscillator is connected with the clock signal output end of the measured chip, and an output end of the passive crystal oscillator is connected with the clock signal input end of the measured chip.

[0028] Compared with the prior art, the embodiment of the utility model has the beneficial effects that:

[0029] The sorting temperature testing device of the chip testing system provided by the application can adjust multiple test temperature environments of the measured chip, simulate different working environment temperatures of the measured chip, does not need to rely on switching between different temperature testing platforms, can meet the functions of multiple different temperature testing platforms, reduces the environmental influence caused by using multiple sorting machines to test different processes. Furthermore, under the different working environment temperatures provided by the sorting temperature testing device, the chip parameter testing device performs direct current parameter testing, time parameter testing and radio frequency parameter testing on the measured chip, can realize multiple different function tests, and does not need to perform step-by-step switching between multiple different testing platforms. After the chip parameter testing device performs direct current parameter testing, time parameter testing and radio frequency parameter testing on the measured chip, the testing result is sent to the sorting temperature testing device. The sorting temperature testing device sorts the measured chip according to the testing result, and thus realizes the testing of the measured chip. The connection relationship between the sorting temperature testing device and the chip parameter testing device in the chip testing system provided by the application is simple, and the testing process is simple, can realize multiple different function tests of the measured chip under different working environment temperatures, does not need to rely on temperature switching testing between different temperature testing platforms, and does not need to perform step-by-step function testing between multiple function testing platforms, the testing process is simple and easy to operate, and thus the testing efficiency of the chip is improved. BRIEF DESCRIPTION OF DRAWINGS

[0030] Figure 1 The principle structure schematic diagram of the chip testing system provided by the application is shown in the figure;

[0031] Figure 2 The testing principle structure schematic diagram of the parameter testing module provided by the application is shown in the figure;

[0032] Figure 3A schematic diagram of a circuit connection structure of a voltage stabilizer and an active crystal oscillator provided in the present application is shown in FIG. 1.

[0033] Figure 4 A schematic diagram of a connection structure of a frequency transceiver module for measuring the output frequency of a measured chip provided in the present application is shown in FIG. 2.

[0034] Figure 5 A schematic diagram of a connection structure of a frequency transceiver module for measuring the output frequency of a measured chip provided in the present application is shown in FIG. 2.

[0035] Figure 6 A schematic diagram of a circuit connection structure of an impedance matching circuit provided in the present application is shown in FIG. 4.

[0036] Figure 7 A schematic diagram of a circuit connection structure of an impedance matching circuit provided in the present application is shown in FIG. 4. DETAILED DESCRIPTION

[0037] In order to make the technical problems, technical solutions and beneficial effects of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and not intended to limit the present application.

[0038] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0039] It should be understood that the terms "length", "width", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only used to facilitate the description of the present application and simplify the description, and therefore cannot be understood as indicating or implying that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application.

[0040] In addition, the terms "first", "second", "third", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined with "first", "second", etc. can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise specifically limited.

[0041] Please refer to Figure 1The application provides a chip testing system. The chip testing system comprises a handler 10 and a chip parameter testing device 30. The handler 10 is used for positioning a chip under test 20 and adjusting multiple working environment temperatures of the chip under test 20. The chip parameter testing device 30 is used for connecting with the chip under test 20, and the chip parameter testing device 30 is used for performing direct current parameter testing, time parameter testing and radio frequency parameter testing on the chip under test 20 at each working environment temperature. The handler 10 is connected with the chip parameter testing device 30, and the chip under test 20 is sorted according to results of the direct current parameter testing, the time parameter testing and the radio frequency parameter testing.

[0042] In the embodiment, the handler 10 can be used for mass production. The handler 10 can adjust a testing temperature environment of the chip under test 20. The multiple working environment temperatures adjusted by the handler 10 can be adjusted in a temperature range of-45℃ to 125℃, so that different working environment temperatures of the chip under test 20 can be simulated. The multiple working environment temperatures can be-45℃ low temperature, 25℃ normal temperature and 125℃ high temperature, so that three-temperature testing can be realized to test the performance and reliability of the chip under different temperature environments. The handler 10 is Hongji HT1024C. The handler 10 can provide multiple different working environment temperatures, and does not need to be switched between different temperature testing platforms, so that the functions of multiple different temperature testing platforms can be met, and the environmental influence caused by using multiple handlers for testing different processes can be reduced.

[0043] At each working environment temperature provided by the handler 10, the chip parameter testing device 30 can perform direct current parameter testing, time parameter testing and radio frequency parameter testing on the chip under test 20. The direct current parameter testing includes testing of direct current and direct voltage, and can be understood as some electrical parameters used for describing the performance and characteristics of the chip under test 20 under direct current (constant current and voltage) conditions. The time parameter testing can be understood as testing of the performance and characteristics of the chip under test 20 related to time in a working process. The radio frequency parameter testing can be understood as testing of the performance and characteristics of the chip under test 20 in radio frequency applications. The chip parameter testing device 30 mainly comprises a digital-analog tester, and is combined with simple electronic components. The connection relationship is simple, the testing process is simple, multiple different function tests can be realized, and step-by-step switching between multiple testing platforms is not needed, so that the chip testing efficiency is improved.

[0044] By means of the sorting temperature test device 10 of the chip test system provided by the present application, multiple test temperature environments of the chip under test 20 can be adjusted to simulate different working environment temperatures of the chip under test 20. It is not necessary to switch between different temperature test platforms, and it can meet the functions of multiple different temperature test platforms, thereby reducing the environmental impact caused by using multiple sorting machines (handlers) to test different processes. Furthermore, under the different working environment temperatures provided by the sorting temperature test device 10, the chip under test 20 is subjected to DC parameter testing, time parameter testing, and RF parameter testing by the chip parameter testing device 30, so as to realize the testing of multiple different functions without the need for step-by-step switching between multiple different test platforms. After the chip parameter testing device 30 performs DC parameter testing, time parameter testing, and RF parameter testing on the chip under test 20, the test results are sent to the sorting temperature test device 10. The sorting temperature test device 10 sorts the chip under test 20 according to the test results, thereby realizing the testing of the chip under test 20. In the chip testing system provided by the present application, the connection relationship between the sorting temperature testing device 10 and the chip parameter testing device 30 is simple and the testing process is simple. It can realize the testing of multiple different functions of the chip under test 20 at different working environment temperatures. There is no need to rely on temperature switching tests between different temperature testing platforms, nor is there a need to perform step-by-step functional tests between multiple functional testing platforms. The testing process is simple and easy to operate, thereby improving the testing efficiency of the chip.

[0045] See Figure 2 In one embodiment, the chip parameter testing apparatus 30 includes a parameter testing module 310. The parameter testing module 310 is connected to multiple pins of the chip under test 20 and is configured to apply current and perform voltage measurement on the multiple pins of the chip under test 20. The parameter testing module 310 is connected to the power pins of the chip under test 20 and is configured to apply pressure and perform current measurement on the power pins of the chip under test 20.

[0046] In this embodiment, the parameter test module 310 can be a digital-analog hybrid test machine, for example, a Diamond 10 test machine. The parameter test module 310 includes a parameter test hardware module 311 and a parameter test control module 312. The parameter test hardware module 311 includes a direct current module (which can also be understood as a DC module). The direct current module includes a high-density voltage / current instrument (HDVI), 96 digital channel board cards (DPIN), 16-channel digital power supply channel board cards (DPS16), and a relay board card (DIBU), and the like hardware systems. The relay board card (DIBU) is used to provide control relay signals. The parameter test control module 312 includes a test software system. The parameter test hardware module 311 and the parameter test control module 312 transmit instructions through a network cable.

[0047] The 96 digital channel board cards and the 16-channel digital power supply channel board cards in the parameter test module 310 are used to perform current injection pressure measurement and pressure injection current measurement. The 96 digital channel board cards and the 16-channel digital power supply channel board cards differ in test accuracy and range. The current injection pressure measurement on the multiple pins of the chip under test 20 can achieve open short test (which can also be understood as OS test). In an embodiment, each of the multiple pins of the chip under test 20 is connected with a diode. A voltage drop measurement is performed on the multiple pins of the chip under test 20, for example, a pin pair, a VDD pin, an IO PIN, and the like, by applying -200uA. If the voltage drop is within the range of 590mV to 610mV, the open short test of the multiple pins of the chip under test 20 is qualified.

[0048] The current injection pressure measurement on the multiple pins of the chip under test 20 can achieve static current test. In an embodiment, a voltage is applied to the VDD power supply of the chip under test 20, and a current test is performed on the VDD PIN. Both the 96 digital channel board cards and the 16-channel digital power supply channel board cards in the parameter test module 310 can achieve power supply measurement, and the difference lies in the test accuracy and range, which can be selected according to actual scene requirements. Therefore, by performing current injection pressure measurement on the multiple pins of the chip under test 20 and pressure injection current measurement on the power supply pins of the chip under test 20, open short test and static current test can be achieved, and thus direct current parameter test on the chip under test 20 is realized.

[0049] In one embodiment, the chip parameter testing device 30 is configured to sequentially perform the DC parameter test, the time parameter test and the RF parameter test on the chip under test 20 at each operating environment temperature. When the DC parameter test is passed, the time parameter test is performed. When the time parameter test is passed, the RF parameter test is performed. If the DC parameter test is failed, the chip under test 20 is discarded. If the DC parameter test is passed and the time parameter test is failed, the chip under test 20 is discarded. If the DC parameter test is passed, the time parameter test is passed and the RF parameter test is failed, the chip under test 20 is discarded. If the DC parameter test is passed, the time parameter test is passed and the RF parameter test is passed, the chip under test 20 is reserved.

[0050] Referring to Figure 3 In one embodiment, the chip parameter testing device 30 further comprises a voltage stabilizer 320 and an active crystal oscillator 330. The voltage stabilizer 320 is connected with the parameter testing hardware module 311 of the parameter testing module 310. The voltage stabilizer 320 is configured to stabilize the voltage provided by the parameter testing module 310 and output a supply voltage. The power supply end of the active crystal oscillator 330 is connected with the voltage stabilizer 320, and the output end of the active crystal oscillator 330 is connected with the external crystal input pin of the chip under test 20, for providing the input frequency signal required by the frequency stability test in the time parameter test.

[0051] In this embodiment, the time-related parameters include the frequency stability test and the real-time clock test. The parameter testing hardware module 311 comprises 96 digital pin configurations (DPIN) and 16 channels of digital power supply channel cards (DPS16) which can supply power for the voltage stabilizer 320. The VIN end and the CE end of the voltage stabilizer 320 are connected with the 16 channels of digital power supply channel cards through the DPS_LDO_TCXO end. The voltage stabilizer 320 stabilizes the voltage provided by the parameter testing module 310 and provides a stable voltage for the active crystal oscillator 330. The Vcc end of the active crystal oscillator 330 is connected with the OUT end of the voltage stabilizer 320. The VSS end of the voltage stabilizer 320 is grounded. The NC end of the voltage stabilizer 320 is suspended.

[0052] The OUT end of the active crystal oscillator 330 is connected with the external crystal input pin of the chip under test 20, and is used to provide an input frequency signal for the chip under test 20. The active crystal oscillator 330 is used to provide an input frequency signal for the chip under test 20, so as to test the frequency stability. In an embodiment, the active crystal oscillator 330 provides a 26MHz frequency to the input end of the chip under test 20. Through the parameter test hardware module 311, the voltage stabilizer 320 and the active crystal oscillator 330, a stable input frequency signal can be provided for the chip under test 20, so as to test the frequency stability. The connection structure between the voltage stabilizer 320 and the active crystal oscillator 330 and the parameter test hardware module 311 is simple and easy to operate, and has low cost, so that the input frequency signal can be quickly provided for the chip under test 20, thereby improving the chip test efficiency. Moreover, when the connection structure between the voltage stabilizer 320, the active crystal oscillator 330 and the parameter test hardware module 311 is fixed, the chip test needs to be repeated again, and the chip can be fixedly used, so that only the connection between the test chip needs to be operated, and the step-by-step switching between multiple functional test platforms is not needed, thereby improving the chip test efficiency.

[0053] In an embodiment, the chip parameter test device 30 further comprises a first frequency generating module 331. The first frequency generating module 331 is connected with the external crystal input pin of the chip under test 20, and is used to provide an input frequency signal for the chip under test 20 required in the frequency stability test in the time parameter test.

[0054] In the embodiment, the first frequency generating module 331 is a backup input frequency signal providing circuit, which is used when the circuit in which the voltage stabilizer 320 and the active crystal oscillator 330 are located fails, so as to improve the reliability of the entire chip test system, and avoid the failure of providing the input frequency signal in the chip test process.

[0055] In an embodiment, the first frequency generating module 331 comprises a first inductor L1, a first capacitor C1 and an oscillation frequency generator. The oscillation frequency generator is other components capable of generating a 26MHz frequency, such as a TZ0495C crystal oscillator, an osc3225-26Mhz active patch crystal oscillator, a frequency meter and the like. One end of the first inductor L1 is connected with the oscillation frequency generator. The other end of the first inductor L1 is connected with one end of the first capacitor C1. The other end of the first capacitor C1 is connected with the external crystal input pin of the chip under test 20, and is used to provide an input frequency signal for the chip under test 20.

[0056] In one embodiment, a matching circuit is arranged between the voltage stabilizer 320 and the active crystal oscillator 330, including a second capacitor C2, a first resistor R1, a second resistor R2, a third resistor R3, a third capacitor C3, a second inductor L2, a fourth capacitor C4, a fourth resistor R4, and a fifth capacitor C5. One end of the second capacitor C2 is connected to the OUT end of the active crystal oscillator 330, and the other end of the second capacitor C2 is connected to the external crystal input pin of the chip under test 20, for providing an input frequency signal to the chip under test 20. One end of the first resistor R1 is connected to the NC1 end of the active crystal oscillator 330, and the other end of the first resistor R1 is grounded. One end of the second resistor R2 is connected to the NC1 end of the active crystal oscillator 330, and the other end of the second resistor R2 is connected to one end of the third resistor R3, and the other end of the third resistor R3 is connected to the OUT end of the voltage stabilizer 320. One end of the third capacitor C3 is grounded, and the other end of the third capacitor C3 is connected to the Vcc end of the active crystal oscillator 330.

[0057] One end of the second inductor L2 is connected to the Vcc end of the active crystal oscillator 330, and the other end of the second inductor L2 is connected to the OUT end of the voltage stabilizer 320. One end of the fourth capacitor C4 is grounded, and the other end of the fourth capacitor C4 is connected to the OUT end of the voltage stabilizer 320. One end of the fourth resistor R4 is connected to the OUT end of the voltage stabilizer 320, and the other end of the fourth resistor R4 is connected to the VIN end of the voltage stabilizer 320. One end of the fifth capacitor C5 is connected to the VIN end of the voltage stabilizer 320, and the other end of the fifth capacitor C5 is grounded. The capacitors, resistors, and inductors in the matching circuit perform impedance matching on the circuit, making the chip test system more stable. The second capacitor C2 filters the frequency signal output by the active crystal oscillator 330. The filtered frequency signal is input into the chip under test 20.

[0058] See Figure 4 In one embodiment, the chip parameter test device 30 further includes a frequency transceiver module 340. The frequency transceiver module 340 is connected to the frequency output pin of the chip under test 20, for measuring the output frequency of the chip under test 20.

[0059] In this embodiment, the frequency transceiver module 340 can be an element capable of measuring the frequency. In one embodiment, the frequency transceiver module 340 can be a Nighthawk instrument. The frequency transceiver module 340 is connected to the frequency output pin LDO_RF_OUT of the chip under test 20, and can test the output frequency of the chip under test 20. If the output frequency of the chip under test 20 is within the range of 25.9995MHz to 26.0005MHz, it indicates that the frequency of the chip under test 20 is stable, and further indicates that the distortion of the chip under test 20 is small and the stability is good.

[0060] The parameter test hardware module 311, the voltage stabilizer 320 and the active crystal oscillator 330 provide an input frequency signal for the chip under test 20. The frequency transceiver module 340 measures the output frequency signal of the chip under test 20. The parameter test hardware module 311, the voltage stabilizer 320, the active crystal oscillator 330 and the frequency transceiver module 340 form a frequency test loop. The connection structure between the components is simple and easy to operate, and the test process is simple. The test of the chip under test 20 can be realized through simple connection, thereby improving the chip test efficiency.

[0061] In an embodiment, the frequency transceiver module 340 is connected with the parameter test control module 312 of the parameter test module 310. The frequency transceiver module 340 is used to measure the output frequency of the chip under test 20 according to the frequency test instruction sent by the parameter test control module 312, and send the output frequency to the parameter test control module 312.

[0062] In the embodiment, the parameter test control module 312 is a PC test software system. The frequency transceiver module 340 is communicatively connected with the parameter test control module 312 to ensure that they work at the same frequency and can realize the transmission of control instructions and data between them. In an embodiment, the frequency transceiver module 340 transmits through the PCI Express (pcie) transmission. The parameter test control module 312 sends a frequency test instruction to the frequency transceiver module 340. The frequency transceiver module 340 measures the output frequency of the chip under test 20 according to the frequency test instruction, and sends the measured output frequency to the parameter test control module 312. The parameter test control module 312 judges whether the output frequency is within the range of 25.9995MHz to 26.0005MHz. If it is within the range of 25.9995MHz to 26.0005MHz, it indicates that the frequency of the chip under test 20 is stable, and thus the distortion of the chip under test 20 is small and the stability is good. Therefore, the parameter test control module 312 sends the test result to the sorting temperature test device 10 for sorting.

[0063] Please refer to Figure 5 and Figure 6 In an embodiment, the chip parameter test device 30 further comprises an impedance matching circuit 350. The impedance matching circuit 350 is connected with the frequency transceiver module 340 and the radio frequency input pin of the chip under test 20 respectively, and is used for impedance matching of the radio frequency parameter test circuit. The frequency transceiver module 340 is further used to output a radio frequency signal to the radio frequency input pin of the chip under test 20 according to the radio frequency parameter test instruction sent by the parameter test control module 312.

[0064] In this embodiment, the RF parameter test includes automatic gain parameter test and noise ratio parameter test. In the noise ratio parameter test, the power supply VDD of the DUT 20 is supplied by the 16-channel digital power supply channel board card DPS16 in the parameter test hardware module 311, and the other pins of the DUT 20 are reset. At the RF input pin LNA_IN (32 pins shown in FIG. 32) of the DUT 20, the 1561.098MHz and 1575.42MHz mixed -65dbm RF sine wave transmitted by the frequency transceiver module 340 of the peripheral device is transmitted to the DUT 20 through the impedance matching circuit 350. The impedance matching circuit 350 is used to match the impedance of the transmission line formed between the frequency transceiver module 340 and the RF input pin of the DUT 20. By impedance matching, signal reflection can be reduced, power transmission efficiency can be improved, and signal quality can be improved, thereby enhancing the stability and reliability of the test system. In one embodiment, the degree of matching of the impedance between the frequency transceiver module 340 and the RF input pin of the DUT 20 is evaluated by using a vector network analyzer. Figure 2

[0065] When the RF parameters of the DUT 20 are tested, the parameter test control module 312 sends an RF parameter test instruction to the frequency transceiver module 340. The frequency transceiver module 340 outputs an RF signal according to the RF parameter test instruction. The parameter test control module 312 sends a chip power supply instruction to the parameter test hardware module 311. The parameter test hardware module 311 supplies power to the DUT 20 according to the chip power supply instruction.

[0066] The frequency transceiver module 340 can measure frequency and also serve as an RF source. The frequency transceiver module 340 outputs an RF signal to the RF input pin of the DUT 20. The frequency transceiver module 340 serves as an RF signal source and introduces the RF signal into the DUT 20. Through the program compiled by the parameter test control module 312, the corresponding chip test timing pattern is input to the general input / output pin (GPI018) of the DUT 20. The parameter test control module 312 compares the timing pattern of the chip test with the waveform generated by the DUT 20 and the waveform generated by the DUT 20. The signal-to-noise ratio is calculated to realize the noise ratio parameter test.

[0067] In one embodiment, the impedance matching circuit 350 includes a connector 351 and an operational amplifier 352. The connector 351 is connected to the frequency transceiver module 340 and is used to introduce the RF signal transmitted by the frequency transceiver module 340 into the impedance matching circuit 350. The input end of the operational amplifier 352 is connected to the connector 351, and the output end of the operational amplifier 352 is connected to the RF input pin of the DUT 20.

[0068] ​In the embodiment, the operational amplifier 352 is a low-noise operational amplifier. The first end of the connector 351 is connected with the frequency transceiver module 340. The radio frequency signal output by the frequency transceiver module 340 is input into the impedance matching circuit 350 through the connector 351. The second end, the third end, the fourth end and the fifth end of the connector 351 are grounded. The first end of the connector 351 is connected with the AI end of the operational amplifier 352. The AO end of the operational amplifier 352 is connected with the radio frequency input pin of the chip under test 20. The radio frequency signal output by the frequency transceiver module 340 is input into the chip under test 20 through the connector 351 and the operational amplifier 352. The VCC end of the operational amplifier 352 is connected with the digital power supply channel board card DPS16 of the 16 channels in the parameter test hardware module 311, for obtaining the supply voltage. The GND1 end and the GND2 end of the operational amplifier 352 are grounded. The PON end of the operational amplifier 352 is connected with the digital power supply channel board card DPS16 of the 16 channels in the parameter test hardware module 311.

[0069] The radio frequency signal is output by the frequency transceiver module 340, and the impedance matching circuit 350 formed by the connector 351, the operational amplifier 352, the capacitor and the inductor and the like is used for impedance matching, so as to reduce the power distribution network amplitude-phase unbalance degree, to obtain the ideal gain, output power, efficiency and dynamic range of the amplifier, and to reduce the power loss in the feeder. The frequency transceiver module 340 and the impedance matching circuit 350 provide the chip under test 20 with stable and accurate radio frequency signals, reduce the external environmental interference, so as to improve the accuracy of the radio frequency parameter test of the chip under test 20. At the same time, the frequency transceiver module 340 has the functions of measuring frequency and transmitting radio frequency signal, so that the devices required by the chip test system are reduced. The connection structure of the frequency transceiver module 340 and the impedance matching circuit 350 is simple and easy to operate, the test process is simple, and the radio frequency parameter test can be realized through simple connection, without step-by-step switching between multiple functional test platforms, so as to improve the chip test efficiency.

[0070] In one embodiment, the impedance matching circuit 350 further comprises a diode D1, a sixth capacitor C6, a seventh capacitor C7, an eighth capacitor C8, a sixth resistor R6, a ninth capacitor C9, a tenth capacitor C10, an eleventh capacitor C11, a twelfth capacitor C12, a thirteenth capacitor C13, and a third inductor L3. The anode of the diode D1 is grounded, and the cathode of the diode D1 is connected to the first end of the connector 351. One end of the sixth capacitor C6 is connected to the first end of the connector 351. The other end of the sixth capacitor C6 is connected to one end of the eighth capacitor C8. The other end of the eighth capacitor C8 is grounded. One end of the sixth resistor R6 is connected to one end of the eighth capacitor C8, and the other end of the sixth resistor R6 is connected to the AI end of the operational amplifier 352. One end of the seventh capacitor C7 is connected to one end of the eighth capacitor C8. The other end of the seventh capacitor C7 is connected to one end of the ninth capacitor C9. The other end of the ninth capacitor C9 is connected to one end of the tenth capacitor C10. The other end of the tenth capacitor C10 is connected to the AO end of the operational amplifier 352. One end of the eleventh capacitor C11 is connected to the VCC end of the operational amplifier 352, and the other end of the eleventh capacitor C11 is grounded. One end of the twelfth capacitor C12 is connected to one end of the tenth capacitor C10, and the other end of the twelfth capacitor C12 is grounded. One end of the thirteenth capacitor C13 is connected to one end of the twelfth capacitor C12, and the other end of the thirteenth capacitor C13 is connected to the radio frequency input pin of the measured chip 20.

[0071] The impedance matching circuit 350 formed by capacitors, resistors, inductors, and the like, matches the impedance of the transmission line formed between the frequency transceiver module 340 and the radio frequency input pin of the measured chip 20. Impedance matching can reduce signal reflection, improve power transmission efficiency, and improve signal quality, thereby enhancing the stability and reliability of the chip testing system.

[0072] Please refer to Figure 7 In one embodiment, the chip parameter testing device 30 further comprises a passive crystal oscillator 360. The input end of the passive crystal oscillator 360 is connected to the clock signal output end of the measured chip 20, and the output end of the passive crystal oscillator 360 is connected to the clock signal input end of the measured chip 20.

[0073] In this embodiment, the real-time clock test is performed by the passive crystal oscillator 360. The passive crystal oscillator 360 can be a quartz crystal resonator that generates a stable signal by relying on the resonant characteristics. The real-time clock test is located in the backup battery power supply area to ensure that the data in the backup RAM is not lost after the main power supply is powered off, and the main power supply can be quickly repositioned after being powered on again. The input end and the output end of the passive crystal oscillator 360 are connected to the RTC_I pin and the RTC_O pin of the chip under test 20, respectively, without the need for an external capacitor and a feedback resistor. The internal oscillation circuit of the chip under test 20 outputs from the RTC_O pin to the passive crystal oscillator 360 to act as a starting circuit, so that the passive crystal oscillator 360 generates a waveform with a frequency of 32.768 KHZ. The waveform is re-entered from the RTC_I pin into the chip under test 20 to provide a signal for the frequency divider of the chip under test 20, so that the chip under test 20 counts and the time is stored in the chip through conversion.

[0074] Further, the passive crystal oscillator 360 accesses the fixed time in the chip under test 20. After the chip under test 20 is powered off, the time saved in the ARM of the chip under test 20 is read by the parameter test control module 312, so that whether the chip timing function and the chip register RAM function of the chip under test 20 are normal can be known. Thus, the clock signal test of the chip under test 20 is realized by using one passive crystal oscillator 360. The RTC_I pin and the RTC_O pin of the chip under test 20 are connected by the passive crystal oscillator 360, so that the real-time clock test can be realized. The connection structure is simple and easy to operate, the test process is simple, and the chip test efficiency is improved because the step-by-step switching between multiple functional test platforms is not needed.

[0075] In one embodiment, the chip parameter test device 30 further includes a second frequency generating module 361. The second frequency generating module 361 is connected to the clock signal input end of the chip under test 20, and is used to perform the real-time clock test on the chip under test 20.

[0076] In this embodiment, the second frequency generating module 361 is a backup input frequency signal providing circuit, which is used in case of failure of the circuit in which the passive crystal oscillator 360 is located, so as to improve the reliability of the entire chip test system and avoid the failure to provide the input frequency signal in the chip test process.

[0077] In one embodiment, the second frequency generating module 361 includes a fifth resistor R5 and an oscillation frequency generator. The oscillation frequency generator is other components that can generate a frequency of 26 MHz, such as a TZ0495C crystal oscillator, an osc3225-26Mhz active patch crystal oscillator, a frequency meter, etc.

[0078] Therefore, the sorting temperature test device 10 provided by the application can adjust multiple test temperature environments of the chip 20 to be tested, simulate different working environment temperatures of the chip 20 to be tested, and does not need to rely on switching between different temperature test platforms, can meet the functions of multiple different temperature test platforms, and reduces the environmental impact caused by using multiple handlers to test different processes. Further, under the different working environment temperatures provided by the sorting temperature test device 10, the parameter test module 310 is taken as a main device, and one or more of the voltage stabilizer 320, the active crystal oscillator 330, the frequency transceiver module 340, and the passive crystal oscillator 360 are combined to realize direct current parameter test, time parameter test, and radio frequency parameter test on the chip 20 to be tested. When the parameter test module 310 is taken as a main device and one or more of the voltage stabilizer 320, the active crystal oscillator 330, the frequency transceiver module 340, and the passive crystal oscillator 360 are combined, the connection relationship is simple and easy to operate. The voltage stabilizer 320, the active crystal oscillator 330, the frequency transceiver module 340, and the passive crystal oscillator 360 are simple electronic components, and the parameter test module 310 is taken as a main device to realize direct current parameter test, time parameter test, and radio frequency parameter test, and does not need to switch between multiple device platforms to realize direct current parameter test, time parameter test, and radio frequency parameter test on the chip 20 to be tested.

[0079] Those skilled in the art can clearly understand that, for the convenience and brevity of description, only the division of the above functional units and modules is exemplified, and in actual application, the above functions can be completed by different functional units and modules according to needs, that is, the internal structure of the device is divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated in one processing unit, or each unit can be physically present separately, or two or more units can be integrated in one unit, and the integrated unit can be realized in the form of hardware or software. In addition, the specific names of each functional unit and module are only for easy distinction, and do not limit the protection scope of the application.

[0080] In the above embodiments, the description of each embodiment has its own emphasis, and the parts not described or recorded in a certain embodiment can be referred to the related description of other embodiments.

[0081] Those skilled in the art can understand that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be realized by electronic hardware or a combination of computer software and electronic hardware. Whether the functions are realized in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0082] In the embodiments provided by the present application, it should be understood that the disclosed apparatuses / devices can be implemented in other ways. For example, the above-described apparatus / device embodiments are merely illustrative. For example, the division of the modules or units is merely a logical function division, and there can be another division manner in actual implementation. For example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed mutual couplings or direct couplings or communication connections between the units can be indirect couplings or communication connections through some interfaces, devices or units, and can be electrical, mechanical or in other forms.

[0083] The units described as separate components can or can not be physically separate, and the components shown as units can or can not be physical units, i.e. can be located in one place, or can be distributed on a plurality of network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the embodiments.

[0084] In addition, each functional unit in each embodiment of the present application can be integrated into a processing unit, or each unit can exist physically independently, or two or more units can be integrated into one unit. The integrated unit can be realized in the form of hardware or in the form of a software functional unit.

[0085] The integrated module / unit, if implemented in the form of a software function unit and sold or used as an independent product, can be stored in a computer-readable storage medium. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or some intermediate forms, etc. The computer-readable medium can include any entity or device capable of carrying the computer program code, recording medium, U disk, mobile hard disk, magnetic disk, optical disk, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signal, telecommunication signal, and software distribution medium, etc. It should be noted that the computer-readable medium contains content that can be appropriately increased or decreased according to the requirements of legislation and patent practice in the jurisdiction, for example, in some jurisdictions, according to legislation and patent practice, the computer-readable medium does not include electrical carrier signals and telecommunication signals.

[0086] The above-described embodiments are only used to illustrate the technical solutions of the present application, rather than limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacements for some technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application.

Claims

1. A chip testing system, characterized by, The application relates to a chip parameter test device. The application relates to a chip parameter test device. The application relates to a chip parameter test device. The application relates to a chip parameter test device.

2. The chip testing system of claim 1, wherein, The application relates to a chip parameter test device. The application relates to a chip parameter test device. The application relates to a chip parameter test device.

3. The chip testing system of claim 2, wherein, The application relates to a chip parameter test device. The application relates to a chip parameter test device. The application relates to a chip parameter test device.

4. The chip testing system of claim 2, wherein, The application relates to a chip parameter test device. The application relates to a chip parameter test device.

5. The chip testing system of claim 3 or claim 4, wherein, The application relates to a chip parameter test device. The application relates to a chip parameter test device.

6. The chip testing system of claim 5, wherein, The application relates to a chip parameter test device.

7. The chip testing system of claim 6, wherein, The application relates to a chip parameter test device.

8. The chip testing system of claim 7, wherein, The application relates to a chip parameter test device. The application relates to a chip parameter test device. The application relates to a chip parameter test device. The application relates to a chip parameter test device. The application relates to a chip parameter test device. The application relates to a chip parameter test device. The application relates to a chip parameter test device. The application relates to a chip parameter test device. The application relates to a chip parameter test device. The application relates to a chip parameter test device. The application relates to a chip parameter test device. The application relates to a chip parameter test device. The application relates to a chip parameter test device. The application relates to a chip parameter test device. The application relates to a chip parameter test device. The application relates to a chip parameter test device. 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The application relates to a chip parameter test device. The application relates to a chip parameter test device. The application relates to a chip parameter test An impedance matching circuit (350) is connected with the output of the frequency transceiver module (340) and the radio frequency input pin of the chip under test (20) respectively, for impedance matching of the circuit for the radio frequency parameter test.

9. The chip testing system of claim 8, wherein, The impedance matching circuit (350) comprises: A connector (351) connected with the frequency transceiver module (340), for introducing the radio frequency signal transmitted by the frequency transceiver module (340) into the impedance matching circuit (350); An operational amplifier (352), the input of the operational amplifier (352) is connected with the connector (351), and the output of the operational amplifier (352) is connected with the radio frequency input pin of the chip under test (20).

10. The system of claim 1, wherein, The chip parameter test device (30) further comprises: A passive crystal oscillator (360), the input of the passive crystal oscillator (360) is connected with the clock signal output of the chip under test (20), and the output of the passive crystal oscillator (360) is connected with the clock signal input of the chip under test (20), for real-time clock test of the chip under test (20).

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