Fin field effect transistor
By designing the polygonal top structure and material selection of the FinFET, the problems of inaccurate current control and leakage are solved, the turn-on and turn-off speeds are improved, and efficient operation is achieved.
Patent Information
- Application Number
- CN202422659049.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-31
- Publication Date
- 2025-10-24
- Estimated Expiration
- 2034-10-31
AI Technical Summary
The current control of existing fin field-effect transistors is not precise enough, leakage occurs, and the turn-on and turn-off speeds are slow, affecting the efficient operation of the equipment.
The top of the fin is designed to be polygonal, with the sum of its sides greater than its height. An octagonal funnel-shaped structure is adopted to optimize the connection between the gate and the fin. Appropriate materials and geometric parameters are selected to increase the conductive area and reduce resistance.
It improves the current control accuracy, reduces leakage current, speeds up turn-on and turn-off, and ensures efficient operation of the device.
Smart Images
Figure CN223472494U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to a semiconductor technical field, concretely relates to a fin field effect transistor. BACKGROUND
[0002] In the metal oxide semiconductor field effect transistor, when the channel length is shortened to approach the distance between the transistor source and drain, threshold voltage reduction, channel length change, hot carrier effect and other adverse conditions will occur, and short channel effect is more serious. Therefore, the traditional metal oxide semiconductor field effect transistor has been unable to meet the demand, and thus the fin field effect transistor is developed.
[0003] In the prior art, the current control of the fin field effect transistor is not accurate enough and there is a leakage situation. In the use process of the fin field effect transistor, the turn-on and turn-off speed is slow, which affects the efficient operation of the equipment.
[0004] Therefore, the prior art has defects and needs to be improved and developed. UTILITY MODEL CONTENT
[0005] The utility model embodiment provides a kind of fin field effect transistor, to solve the problem that the current control of the fin field effect transistor in prior art is not accurate enough and there is a leakage situation. In the use process of the fin field effect transistor, the turn-on and turn-off speed is slow, which affects the efficient operation of the equipment.
[0006] The utility model embodiment provides a kind of fin field effect transistor, including substrate, further including the fin formed on the substrate, the top of fin is the interface in the extension direction perpendicular to fin and is polygon, the sum of the length of any side of the polygon is greater than the height of the polygon;The substrate is covered with an oxide layer;The gate that crosses fin is fixed on the oxide layer, and the gate is used to adapt the outer contour of fin by sticking to the lower surface of fin;When the gate crosses the gate, the gate is divided into source and drain.
[0007] Further, the polygon is octagon and is left-right symmetrical funnel shape, the top of the octagon is defined as first side, the second side of the octagon is perpendicular to the oxide layer according to clockwise direction, the third side of the octagon is acute angle with the oxide layer, the fourth side of the octagon is perpendicular to the substrate and the highest point of the fourth side is flush with the upper surface of the oxide layer, and the fifth side of the octagon is close to the substrate.
[0008] Further, the length of the first side of the octagon is defined as W, the height of the octagon above the oxide layer is H, H:W=A, wherein W, H are positive number, and the value range of A is [1,100].
[0009] Further, an included angle between the second side of the octagon and the third side of the octagon is defined as θ, and θ is in the range of [120, 150].
[0010] Further, an acute angle between the third side of the octagon and the oxide layer is defined as β, and β is in the range of [30, 60].
[0011] Further, the fins are at least one, and when the number of fins is greater than one, adjacent fins are parallel to each other.
[0012] Further, the fin is one of a single-element semiconductor fin, a compound semiconductor fin, and a semiconductor alloy fin; the single-element semiconductor fin includes a germanium fin and a silicon fin; the compound semiconductor fin includes a gallium arsenide fin and an aluminum gallium arsenide fin; and the semiconductor alloy fin includes a silicon germanium fin and a phosphorus gallium arsenide fin.
[0013] Further, the substrate is one of a silicon substrate, a silicon-on-insulator substrate, and a silicon element mixture substrate.
[0014] Further, the gate is one of a polysilicon gate and a metal gate; the polysilicon gate includes a nickel silicide gate and a cobalt silicide gate; and the metal gate includes a molybdenum gate, a copper gate, a tungsten gate, an aluminum gate, a cobalt gate, a zirconium gate, and a platinum gate.
[0015] Further, the bottom of the gate is further covered with a dielectric layer, and the thickness of the dielectric layer is in the range of [10, 100] angstroms.
[0016] Beneficial effects:
[0017] It can be seen from the above technical solution that the fin field effect transistor is provided, the top of the fin is designed as a polygon, and the sum of the side lengths is greater than the height, so that the conductive area can be effectively increased, and the resistance can be reduced. Through the structure optimization, material selection and geometric parameter design of the fin field effect transistor, the current control accuracy of the transistor is effectively improved, the leakage current is reduced, and the turn-on and turn-off speed is accelerated. The various structural designs complement each other to ensure efficient operation of the device, and are suitable for high-performance electronic equipment.
[0018] It should be understood that all combinations of the aforementioned concepts and additional concepts described in greater detail below can be seen as part of the subject matter of the present disclosure, as long as such concepts are not mutually contradictory.
[0019] The aforementioned and other aspects, embodiments, and features of the present teachings can be understood more readily by reference to the following description in conjunction with the accompanying drawings. Other aspects, features, and / or advantages of the present teachings will become apparent from the description that follows, and from the claims. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] The accompanying drawings are not drawn to scale. In the accompanying drawings, each identical or nearly identical component shown in various figures may be represented by the same reference numeral. For clarity, not every component is labeled in every figure. Embodiments of various aspects of the present invention will now be described by way of example with reference to the accompanying drawings, in which:
[0021] Figure 1 Schematic diagram of the structure of a fin field effect transistor in an embodiment of the present application.
[0022] Figure 2 This is a cross-sectional view of the structure of a fin field effect transistor in an embodiment of the present application.
[0023] Figure 3 It is a structural cross-sectional view of a fin field effect transistor in the prior art.
[0024] Description of Figure Numbers:
[0025] Substrate 1; source 2; drain 3; oxide layer 4; dielectric layer 5; gate 6. DETAILED DESCRIPTION
[0026] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings of the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the described embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention. Unless otherwise defined, the technical terms or scientific terms used herein should be the common meanings understood by people with ordinary skills in the field to which the present invention belongs.
[0027] The terms "first", "second", and similar terms used in the specification and claims of the present patent application do not denote any order, quantity, or importance, but are used to distinguish different components. Similarly, the singular forms "a", "an", and "the" do not denote a quantity limitation, but denote the presence of at least one, unless the context clearly indicates otherwise. The terms "comprise", "comprising", and similar terms mean that the elements or objects preceding the word "comprise" or "comprising" encompass the features, integers, steps, operations, elements, and / or components listed after the word "comprise" or "comprising", and do not exclude one or more other features, integers, steps, operations, elements, components, and / or groups thereof. The terms "upper", "lower", "left", "right", and the like are used only to indicate relative positions, and may change accordingly when the absolute positions of the described objects change.
[0028] In the prior art, the current control of the fin field effect transistor is not accurate enough and there is a leakage, which affects the efficient operation of the device because the turn-on and turn-off speed of the fin field effect transistor is slow.
[0029] In view of this, the embodiments of the present application provide a fin field effect transistor, which refers to Figures 1-2 , comprising a substrate 1, further comprising a fin formed on the substrate 1, the top of the fin is a polygon in the direction perpendicular to the extension direction of the fin, the sum of the lengths of any side of the polygon is greater than the height of the polygon; the substrate 1 is covered with an oxide layer 4; the oxide layer 4 is fixed with a gate 6 crossing the fin, the gate 6 is used to adapt to the outer contour of the fin by fitting the lower surface of the fin; the gate 6 is divided into a source 2 and a drain 3 when the gate 6 crosses the gate 6. By designing the top of the fin as a polygon and the sum of the lengths of the sides being greater than the height, the conductive area can be effectively increased and the resistance can be reduced.
[0030] In some embodiments, the polygon is an octagon and is a left-right symmetrical funnel shape, the top of the octagon is defined as a first side, the second side of the octagon is perpendicular to the oxide layer 4 in a clockwise direction, the third side of the octagon has an acute angle with the oxide layer 4, the fourth side of the octagon is perpendicular to the substrate 1 and the highest point of the fourth side is flush with the upper surface of the oxide layer 4, and the fifth side of the octagon is close to the substrate 1. The funnel structure of the octagon makes the electric field more concentrated at the top of the fin, thereby improving the mobility of the carriers and accelerating the turn-on and turn-off speed. In addition, the left-right symmetrical design helps the overall stability of the device, further improving the reliability of the equipment. In still other embodiments, the oxide layer 4 is a silicon dioxide layer, which can also be a high dielectric constant material, such as titanium oxide, zirconium oxide, etc., to improve the gate 6 capacitance and reduce the gate-drain current at the same time.
[0031] Referring to Figure 2 , the arrows in the figure represent the direction of the electric field, and referring toFigure 3 The arrows in the figure indicate the direction of the electric field. Compared with the fin structure in the prior art, the octagonal structure increases the electric field to which the P-type or N-type minority carriers of the transistor are subjected after the gate 6 voltage is applied, and the speed at which the carriers drift toward the source 2 or drain 3 and the substrate 1 is faster, thereby accelerating the speed at which the transistor is turned on or off.
[0032] In some embodiments, the length of the first side of the octagon is defined as W, and the height of the octagon above the oxide layer 4 is defined as H, where H:W=A, where W and H are positive numbers and the value range of A is [1,100]. A small H value results in high resistance. A large W value can easily merge with adjacent fins and cause a short circuit. A small W value can narrow the contact window between the fin and the gate 6, which can damage the circuit effect. If A is too large, the epitaxial height in the transistor will be shortened, affecting the resistance value. If A is too small, the epitaxial volume in the transistor will be reduced, reducing the tension of the device. Both situations will affect the mobility of the device. Therefore, the value of A is set to [1,100] to balance the resistance value and device tension, thereby improving the quality of the transistor and enhancing the mobility and reliability of the device.
[0033] In some embodiments, the angle between the second side of the octagon and the third side of the octagon is defined as θ, and the value range of θ is [120, 150]. The optimized range of θ can adjust the electric field distribution between the fin and the substrate 1, ensuring electric field concentration, reducing leakage current, and improving switching speed.
[0034] In some embodiments, the acute angle between the third side of the octagon and the oxide layer 4 is defined as β, and the value of β ranges from [30, 60]. The value range of the angle β optimizes the connection between the fin and the oxide layer 4, further concentrates the electric field, improves the carrier migration path, and thus improves switching efficiency.
[0035] In some embodiments, there is at least one fin, and when the number of fins is greater than 1, adjacent fins are parallel to each other. The parallel arrangement of multiple fins improves the parallel conductivity of the transistor, increases the overall current carrying capacity, and further improves the operating efficiency of the device.
[0036] In some embodiments, the fin is one of a single-element semiconductor fin, a compound semiconductor fin, or a semiconductor alloy fin. Single-element semiconductor fins include germanium fins and silicon fins; compound semiconductor fins include gallium arsenide fins and aluminum gallium arsenide fins; and semiconductor alloy fins include silicon germanium fins and gallium arsenide phosphide fins. The choice of single-element semiconductor and compound semiconductor materials provides transistors with diverse material properties, adapting them to different operating environments and performance requirements, such as improving conductivity, corrosion resistance, or reducing leakage.
[0037] In some embodiments, the substrate 1 is one of a silicon substrate 1, a silicon-on-insulator substrate 1, a silicon element mixture substrate 1. The selection of the substrate 1 material enables the device to work stably in harsh environments such as high temperature and high pressure, while optimizing the electric field coupling of the fin and the substrate 1 and improving the overall performance.
[0038] In some embodiments, the gate 6 is one of a polysilicon gate, a metal gate; the polysilicon gate includes a nickel silicide gate, a cobalt silicide gate; the metal gate includes a molybdenum gate, a copper gate, a tungsten gate, an aluminum gate, a cobalt gate, a zirconium gate, a platinum gate. The various materials provide different conductivity and thermal stability options, optimizing the working performance and life of the transistor. For example, the metal gate can withstand higher current, while the polysilicon gate has better thermal stability.
[0039] In some embodiments, the bottom of the gate 6 is also covered with a dielectric layer 5, and the thickness of the dielectric layer 5 is in the range of [10, 100] angstroms. The thickness of the dielectric layer 5 optimizes the protection of the gate 6 while ensuring the concentration of the electric field and improving the response speed of the transistor. The fine control of the thickness of angstroms helps to reduce the leakage phenomenon and improve the switching efficiency of the device. The dielectric layer 5 includes an aluminum oxide dielectric layer, a hafnium oxide dielectric layer, a hafnium silicon oxide dielectric layer, a hafnium silicon nitride oxide dielectric layer, a hafnium titanium oxide dielectric layer, a hafnium zirconium oxide dielectric layer, etc.
[0040] In some embodiments, the source 2 and the drain 3 will have different pentavalent or trivalent ion dopants according to the type of charge carriers, and the concentration of the ion dopants is in the range of 1E19 / cm 3 to 4E21 / cm 3 . The pentavalent ion dopant can be any one of phosphorus, antimony, bismuth or nitrogen. The trivalent ion dopant can be any one of boron, boron fluoride, gallium, indium, thallium or aluminum.
[0041] In summary, the fin field effect transistor provided by the utility model can effectively increase the conductive area and reduce the resistance by designing the top of the fin as a polygon with a side length sum greater than the height. Through the structural optimization, material selection and geometric parameter design of the fin field effect transistor, the current control accuracy of the transistor is effectively improved, the leakage current is reduced, and the turn-on and turn-off speed is accelerated. The various structural designs complement each other to ensure efficient operation of the device, and the device is suitable for high-performance electronic equipment.
[0042] Although the present application has been disclosed with reference to the preferred embodiments thereof, it is not intended to limit the application. Those skilled in the art having ordinary knowledge can make various modifications and improvements without departing from the spirit and scope of the application. Therefore, the scope of protection of the present application shall be subject to the scope defined by the claims.
Claims
1. A fin field effect transistor comprising a substrate, characterized by, Also include the fin formed on the substrate, the top of the fin in the direction perpendicular to the extension of the interface of the fin is a polygon, the polygon is an octagon and is left-right symmetric funnel-shaped, the sum of the length of any side of the polygon is greater than the height of the polygon; The substrate is covered with an oxide layer; define the top of the octagon as the first side, the second side of the octagon in the clockwise direction is perpendicular to the oxide layer, the third side of the octagon forms an acute angle with the oxide layer, the fourth side of the octagon is perpendicular to the substrate and the highest point of the fourth side is flush with the upper surface of the oxide layer, the fifth side of the octagon is close to the substrate; The oxide layer is fixed with a gate across the fin, the gate is used to fit the lower surface of the fin and adapt to the outer contour of the fin; When the gate is across the gate, the gate is divided into source and drain.
2. The fin field effect transistor of claim 1, wherein, Define the length of the first side of the octagon as W, the height of the octagon above the oxide layer as H, H:W=A, where W, H are positive numbers, and the value range of A is [1,100].
3. The fin field effect transistor of claim 2, wherein, Define the angle between the second side of the octagon and the third side of the octagon as θ, the value range of θ is [120,150].
4. The fin field effect transistor of claim 3, wherein, Define the acute angle between the third side of the octagon and the oxide layer as β, the value range of β is [30,60].
5. The fin field effect transistor of claim 4, wherein the gate electrode is formed of a material selected from the group consisting of polysilicon, amorphous silicon, and metal. The fin is at least one, when the number of fins is greater than 1, adjacent fins are parallel to each other.
6. The fin field effect transistor of claim 1, wherein, The fin is one of a single-element semiconductor fin, a compound semiconductor fin, and a semiconductor alloy fin; the single-element semiconductor fin includes a germanium fin and a silicon fin; the compound semiconductor fin includes a gallium arsenide fin and an aluminum gallium arsenide fin; the semiconductor alloy fin includes a silicon germanium fin and a phosphorus gallium arsenide fin.
7. The fin field effect transistor of claim 1, wherein, The substrate is one of a silicon substrate, a silicon-on-insulator substrate, and a silicon element mixture substrate.
8. The fin field effect transistor of claim 1, wherein, The gate is one of a polysilicon gate and a metal gate; the polysilicon gate includes a nickel silicide gate and a cobalt silicide gate; the metal gate includes a molybdenum gate, a copper gate, a tungsten gate, an aluminum gate, a cobalt gate, a zirconium gate, and a platinum gate.
9. The finFET of claim 1, wherein, The bottom of the gate is also covered with a dielectric layer, the thickness of the dielectric layer is in the value range of [10,100], and the unit of the thickness of the dielectric layer is angstrom.