Acquisition device of low-cost light small recorder
By using Microblaze soft cores and FPGA resources to build an acquisition device in the aircraft recorder, the challenges of diverse data acquisition, cost, size, and power consumption are solved, achieving efficient, low-cost, and miniaturized data acquisition and storage, meeting the diverse data type requirements of the aircraft recorder.
Patent Information
- Application Number
- CN202423017475.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-06
- Publication Date
- 2025-10-28
- Estimated Expiration
- 2034-12-06
AI Technical Summary
Existing recorders face challenges in data acquisition due to diverse needs, cost control, power consumption, and size, especially in aircraft recorders where it is difficult to simultaneously meet the requirements of high-performance data acquisition, low cost, small size, and low power consumption.
The Microblaze soft core, based on an FPGA chip, serves as the core CPU processor. Combined with FPGA resources, it builds data acquisition modules and other peripheral modules, including data processing interfaces, AXI bridges, USB modules, and hard disk management modules. This enables the acquisition and storage of various data types, controls and accesses devices through the AXI bridge, and uses DDR and Block RAM modules for data caching. It supports protocols such as LVDS, PCM, 485, 422, and CML.
It achieves efficient acquisition and storage of various data types under the premise of low cost and miniaturization, meeting the data recording needs of aircraft recorders, while reducing power consumption and improving system reliability and integration.
Smart Images
Figure CN223486546U_ABST
Abstract
Description
Technical Field
[0001] This utility model belongs to the field of avionics technology, and in particular relates to a low-cost, lightweight data acquisition device. Background Technology
[0002] As a component of hang-up training, the aircraft's data recorder is mainly used to record the pilot's operations during hang-up training, as well as the working status and parameters of the corresponding vehicle, in order to determine whether the pilot's operations are correct and to provide assistance for the pilot's training.
[0003] As recorders continue to develop, their requirements are also gradually increasing. On the one hand, with the increasing number of recorded data types, recorders need to meet different types of data acquisition needs, and depending on different working scenarios, they need to support data acquisition functions such as LVDS, PCM, 485, 422, and CML. On the other hand, since recorders are usually embedded as an independent module in a carrier, they have very strict requirements in terms of power consumption and size. At the same time, due to the cost increase caused by localization, there are also equally strict requirements in terms of cost control. Utility Model Content
[0004] To address the problems in the background technology, this utility model provides a low-cost, lightweight data acquisition device that can meet different data acquisition needs while ensuring low cost, small size, low power consumption, and high reliability.
[0005] To achieve the above objectives, the present invention adopts the following technical solution.
[0006] A low-cost, lightweight recorder acquisition device, wherein the acquisition device uses the Microblaze soft core of an FPGA chip as the core CPU processor of the acquisition device.
[0007] The following modules are built using FPGA resources: data acquisition module, debug module, local memory, timer module, watchdog module, reset module, USB module, hard disk management module, AXI bridge, register interaction module, Block RAM module 0, UART serial port module, Flash module, XADC module, DDR module, and Block RAM module 1.
[0008] Furthermore, the Microblaze soft core, as the core CPU processor, has the following interfaces: Data Processing Interface (DP), Instruction Processing Interface (IP), Interrupt Interface, Reset Interface, Local Memory Interface, and Debug Interface; and it needs to reserve Cache interfaces, including Cache Data Interface (DC) and Cache Instruction Interface (IC).
[0009] The data processing interface DP, instruction processing interface IP, cache data interface DC, and cache instruction interface IC are respectively connected to the AXI bridge to access other peripherals on the AXI bridge.
[0010] Furthermore, the AXI bridge is used to connect one or more master devices with multiple AXI memory mappings to one or more slave devices with memory mappings. The Microblaze soft core, hard disk management module, and USB module are connected to the AXI bridge as master devices, while the register interaction module, Block RAM module 0, UART serial port module, Flash module, XADC module, DDR module, and Block RAM module 1 are connected to the AXI bridge as slave devices. The master devices control and access the slave devices through the AXI bridge.
[0011] Furthermore, the USB module serves as the channel for USB data upload and download, and includes the USB driver module, Datamover control module, Datamover IP core, and DMA module;
[0012] When uploading data via the USB module, the data upload channel is formed sequentially by the USB driver module, the Datamover control module, the Datamover control module, and the Datamover IP core, and is connected to an external AXI bridge to transmit the data to the designated location.
[0013] When downloading data via USB, the DMA module connects to an external AXI bridge to transmit data to the DMA module. The data is then transmitted to the USB module for download and reception via the DMA module and the USB driver module.
[0014] Furthermore, the hard drive management module includes a SATA IP core, a DMA module, a FIFO IP core 0, and a FIFO IP core 1;
[0015] When performing a hard disk write operation, the DMA module receives control commands from the Microblaze soft core through the AXI bridge and transmits the received write data. The write data is transmitted to the SATA IP core through FIFO IP core 0, and the SATA IP core completes the data writing to the hard disk according to the SATA protocol.
[0016] When performing a hard disk read operation, the DMA module receives control commands from the Microblaze soft core through the AXI bridge, and transfers the data read from the hard disk by the SATAIP core to the designated location through the AXI bridge, thus completing the read of hard disk data.
[0017] Furthermore, the SATA IP core is a management module developed for hard drives that support the SATA protocol. It is configured in SATA1.0, SATA2.0, and SATA3.0 modes. The Microblaze soft core reads and writes register data to the SATA IP core through the AXI bridge.
[0018] FIFO IP core 0 and FIFO IP core 1 are used for data buffering.
[0019] This invention provides a low-cost, lightweight data acquisition device that can meet the requirements of high-performance data acquisition and recording functions, while ensuring low cost, small size, low power consumption, and high reliability. Attached Figure Description
[0020] Figure 1 This is a schematic diagram of the composition of a low-cost, lightweight recorder acquisition device provided by an embodiment of the present invention;
[0021] Figure 2 This is a schematic diagram of the composition of the USB module provided in this embodiment of the present utility model;
[0022] Figure 3 This is a schematic diagram of the composition of the hard disk management module provided in this embodiment of the utility model. Detailed Implementation
[0023] The present invention will now be described in detail with reference to the accompanying drawings.
[0024] This invention provides a low-cost, lightweight data acquisition device. The solution employed is to utilize the Microblaze soft core of an FPGA as the core CPU processor of the acquisition device, while simultaneously using FPGA resources to build the data acquisition interface and other peripheral modules. By using FPGA and Microblaze in the design, the functionality of multiple dedicated chips is realized, significantly reducing the device size and facilitating miniaturization and integration.
[0025] Based on Microblaze, its peripherals include: data acquisition module, debug module, local memory, timer module, watchdog module, reset module, USB module, hard disk management module, AXI (Advanced Dextensible Interface) bridge, register interaction module, Block RAM module 0, UART serial port module, Flash module, XADC module, DDR module, Block RAM module 1, etc.
[0026] After the device is powered on, the reset module starts working and performs reset initialization on each module. After the reset is complete, the application software starts and performs a status self-test. After the application software completes the self-test, it notifies the watchdog module to start working through the register. At this time, all modules have started and entered the state of waiting to collect data. When data is generated at the front end of the acquisition interface, the data acquisition module collects the data signal according to the established protocol. The collected data will be placed in the data buffer area, and the application software will retrieve the data in time and write it to the hard disk.
[0027] In ground mode, the recorder is powered via USB. The ground equipment has dedicated data processing software that can download, view, and analyze the data recorded by the recorder according to its history.
[0028] In this data acquisition device, the core processor chip is an FPGA chip of model JFM-7K325T. The Microblaze soft core is used as the CPU core processor of the acquisition device, while FPGA resources are used to build the data acquisition interface and other peripheral modules. Compared with conventional SoC architecture or microcontroller + FPGA architecture, this solution has advantages such as fast operation speed, low resource consumption, and strong configurability.
[0029] like Figure 1 The diagram shows the overall framework of the acquisition device, with Microblaze as its core. Its peripherals include: data acquisition module, debug module, local memory, timer module, watchdog module, reset module, USB module, hard disk management module, AXI bridge, register interaction module, Block RAM module 0, UART serial port module, Flash module, XADC module, DDR module, and Block RAM module 1.
[0030] The following is a description of the functions of each module.
[0031] As the core of the entire device, the Microblaze interface includes the following main interfaces: Data Processing Interface (DP), Instruction Processing Interface (IP), Interrupt Interface, Reset Interface, Local Memory Interface (DLMB, ILMB), and Debug Interface. Additionally, to improve data processing and computation efficiency, cache interfaces are reserved, including a Cache Data Interface (DC) and a Cache Instruction Interface (IC). DP, IP, DC, and IC connect to the AXI bridge, allowing access to other peripherals on the AXI bridge.
[0032] An AXI bridge is used to connect one or more master devices with multiple AXI memory maps to one or more slave devices with memory maps. In this device, the Microblaze, hard disk management module, and USB module are connected to the AXI bridge as master devices, while the register interaction module, Block RAM module 0, UART serial port module, Flash module, XADC module, DDR module, and Block RAM module 1 are connected to the AXI bridge as slave devices. The master devices can control and access the slave devices through AXI.
[0033] The data acquisition module can acquire front-end signals according to different protocols, such as LVDS, PCM, 485, 422, CML and other data types, and write the acquired data to the specified data buffer.
[0034] The Debug module implements the debug functionality during the debugging phase.
[0035] Local memory is primarily the space where application software runs. Its size is configurable, typically ranging from 32kB to 512kB, and can be flexibly configured according to the actual application scenario and FPGA hardware resources.
[0036] The timer module provides configurable timer interrupts for application software, and the specific implementation and parameter configuration can be flexibly configured by the application software.
[0037] The watchdog module is used to periodically check whether the application software is working properly. Due to the design requirements of low cost and low power consumption, this acquisition device minimizes the use of dedicated chips and does not use a dedicated watchdog chip. Instead, the watchdog function is implemented on the FPGA side. Specifically: The watchdog module does not work before the application software starts. After the application software starts, a notification register is sent to indicate that the application software has started, and the watchdog module begins to work. The application software needs to feed the watchdog module within 1 second (the specific value can be configured via the register); otherwise, the watchdog module will consider the application software to be in an abnormal working state and will perform a global reset.
[0038] The reset module outputs different reset signals as required.
[0039] The USB module is the channel for uploading and downloading data via USB. For example... Figure 2 The diagram shows the components of a USB module, which mainly include a USB driver module, a Datamover control module, a Datamover IP core, and a DMA (Direct Memory Access) module.
[0040] (1) When uploading data via USB, the USB driver module first receives the data transmitted by the USB upload interface and sends the data to the Datamover control module. The Datamover control module schedules the Datamover IP core through control commands, and finally the Datamover IP core transmits the data to the designated location through the AXI bridge to complete the data upload.
[0041] (2) When downloading data via USB, the DMA module receives the control command from Microblaze through the AXI bridge, transfers the data from the specified memory address to the USB driver module, and then the USB driver module transfers the data to the USB download receiver to complete the data download.
[0042] (3) The USB driver module is developed based on the USB chips provided by different hardware manufacturers. The interface remains unchanged, and the module can be flexibly adapted to support USB2.0 and USB3.0.
[0043] The hard drive management module performs functions such as self-testing, reading, writing, and erasing on the hard drive. For example... Figure 3 The diagram shows the components of the hard drive management module, which mainly include a SATA (Serial ATA) IP core, a DMA module, a FIFO (First In First Out) IP core 0, and a FIFO IP core 1.
[0044] (1) When performing a hard disk write operation, the DMA module receives the control command of Microblaze through the AXI bridge and transmits the received write data. The write data is transmitted to the SATA IP core through FIFO IP core 0. The SATA IP core completes the data writing to the hard disk according to the SATA protocol.
[0045] (2) When performing a hard disk read operation, the DMA module receives the control command from Microblaze through the AXI bridge, and transfers the data read from the hard disk by the SATAIP core to the specified location through the AXI bridge to complete the reading of hard disk data.
[0046] (3) Among them, the SATA IP core is a management module developed for hard drives that support the SATA protocol. It can be configured as SATA1.0, SATA2.0 and SATA3.0 modes. Microblaze can read and write register data to the SATA IP core through the AXI bridge to realize control and status reading functions.
[0047] (4) FIFO IP core 0 and FIFO IP core 1 mainly serve as a data buffer.
[0048] The register interaction module mainly uses the APB (Advanced Peripheral Bus) bus for low-speed register data interaction.
[0049] Block RAM module 0 utilizes Block RAM resources for data caching. Data acquired by the data acquisition module can be cached here, and the CPU can be notified to retrieve the data through the register interaction module.
[0050] The UART serial port module enables serial port debugging and printing functions.
[0051] The Flash module, acting as the management module for the Flash chip, enables reading and writing to the external Flash chip. On one hand, the Flash chip is used for program storage, ensuring that the program is not lost after the device is powered off. Simultaneously, when the application software is large, the FPGA's Block RAM resources may not be sufficient for its needs. If the program requires memory space provided by DDR, the bootloader needs to use the Flash management module to move the program to DDR for execution. On the other hand, the Flash chip can also serve as a log storage area.
[0052] The XADC module is mainly used to monitor chip temperature, voltage, etc.
[0053] The DDR module utilizes the MIG IP core to read and write to the DDR chip. Depending on the actual application scenario, the DDR chip can be optionally installed. When the application is small and the amount of data collected is small, the application software can run normally using only the FPGA Block RAM resources without using DDR. Therefore, it can be omitted, saving costs and power consumption.
[0054] Block RAM module 1 utilizes Block RAM resources as a multifunctional data cache area, which can be used flexibly according to actual scenarios, such as a cache area for receiving USB commands, a cache area for data download, and a cache area for data writing to disk.
[0055] The working process of this device is described below based on specific application scenarios.
[0056] The main workflow of the recorder can be divided into: power-on startup → initialization and self-test → data acquisition → data recording → device power-off → data download.
[0057] The specific description is as follows:
[0058] After the recorder is powered on, the program is automatically loaded from the external Flash chip into the FPGA for execution. If the program requires a large amount of storage space, a bootloader program is needed to move the program from the Flash chip to DDR for execution. This can be flexibly configured according to the actual scenario.
[0059] Then the reset module starts working, resetting and initializing each module in the system.
[0060] After the reset is complete, the application software starts and performs a status self-check;
[0061] Once the application software completes its self-test, it notifies the watchdog module to start working via a register. At this point, all modules have started and are waiting to collect data.
[0062] When data is generated at the front end of the acquisition interface, the data acquisition module acquires the data signal according to the established protocol;
[0063] The collected data will be placed in the data cache area, i.e. Figure 1 In Block RAM module 0, the application software retrieves data from Block RAM module 0 and writes it to the hard drive. Specifically, in addition to data interaction through Block RAM module 0, the data acquisition module and the application software also interact via registers using APB (the specific register definition can be defined by the user). The data acquisition module cyclically writes the acquired data into Block RAM module 0. During the data writing process, the data acquisition module updates the address of the data being written to Block RAM module 0 in real time to the register. The application software can obtain the size of the data to be read by reading the register value and write it to the hard drive in a timely manner.
[0064] When acquiring high-bandwidth data, the storage space of Block RAM module 0, which serves as the data buffer, is limited, typically only a few hundred kB, which is insufficient to meet the demands of high-bandwidth data acquisition. In this case, DDR memory can be used to replace Block RAM module 0. DDR memory typically has storage spaces of tens of MB or more, which can meet the high-bandwidth data caching requirements. For the application software, it is only necessary to change the address space for data retrieval from Block RAM module 0 to DDR.
[0065] Once the data acquisition is complete, the device is powered off.
[0066] In ground mode, the ground equipment is connected to the recorder via a USB download cable, which also provides power to the recorder.
[0067] The ground equipment is equipped with dedicated data processing software. The data download software and the recorder communicate via USB for commands and data. When the data processing software downloads data, the recorder receives the download command through the USB module, then reads the data into Block RAM module 1 through the hard disk management module, and finally sends the data to the data processing software via the USB module.
[0068] After the data processing software completes the data download, it can be used to check and analyze the data.
[0069] In other application scenarios, data processing software can also upload data to the recorder via USB cable, such as for online program upgrades, updating software version information, and setting recorder product information.
[0070] This invention provides a low-cost, lightweight recorder acquisition method and device. The device can complete the acquisition and recording of data during flight while meeting the requirements of low cost, lightweight, and integration. It supports the acquisition and encoding of multiple data of different types. Then, all data is stored in a storage chip in a fixed frame format. In the power-off state, the recording component and the data downloader are connected through a download cable. The data download processing software completes the download, processing, analysis, and clearing of the recorded data.
Claims
1. A low-cost, lightweight recorder acquisition device, characterized in that, The acquisition device uses the Microblaze soft core of the FPGA chip as the core CPU processor of the acquisition device. The following modules are built using FPGA resources: data acquisition module, debug module, local memory, timer module, watchdog module, reset module, USB module, hard disk management module, AXI bridge, register interaction module, Block RAM module 0, UART serial port module, Flash module, XADC module, DDR module, and Block RAM module 1.
2. The acquisition device for a low-cost, lightweight recorder according to claim 1, characterized in that, The Microblaze soft core, as the core CPU processor, has the following interfaces: Data Processing Interface (DP), Instruction Processing Interface (IP), Interrupt Interface, Reset Interface, Local Memory Interface, and Debug Interface; and it needs to reserve Cache interfaces, including Cache Data Interface (DC) and Cache Instruction Interface (IC). The data processing interface DP, instruction processing interface IP, cache data interface DC, and cache instruction interface IC are respectively connected to the AXI bridge to access other peripherals on the AXI bridge.
3. The acquisition device for a low-cost, lightweight recorder according to claim 2, characterized in that, The AXI bridge is used to connect one or more master devices with multiple AXI memory mappings to one or more slave devices with memory mappings. The Microblaze soft core, hard disk management module, and USB module are connected to the AXI bridge as master devices, while the register interaction module, Block RAM module 0, UART serial port module, Flash module, XADC module, DDR module, and Block RAM module 1 are connected to the AXI bridge as slave devices. The master device controls and accesses the slave devices through the AXI bridge.
4. The acquisition device for a low-cost, lightweight recorder according to claim 3, characterized in that, The USB module is the channel for USB data upload and download, including the USB driver module, Datamover control module, Datamover IP core, and DMA module; When uploading data via the USB module, the data upload channel is formed sequentially by the USB driver module, the Datamover control module, the Datamover control module, and the Datamover IP core, and is connected to an external AXI bridge to transmit the data to the specified location. When downloading data via USB, the DMA module connects to an external AXI bridge to transmit data to the DMA module. The data is then transmitted to the USB module for download and reception via the DMA module and the USB driver module.
5. The acquisition device for a low-cost, lightweight recorder according to claim 4, characterized in that, The hard drive management module includes a SATA IP core, a DMA module, a FIFO IP core 0, and a FIFO IP core 1; When performing a hard disk write operation, the DMA module receives control commands from the Microblaze soft core through the AXI bridge and transmits the received write data. The write data is transmitted to the SATA IP core through FIFO IP core 0, and the SATA IP core completes the data writing to the hard disk according to the SATA protocol. When performing a hard drive read operation, the DMA module receives control commands from the Microblaze soft core through the AXI bridge, and transfers the data read from the hard drive by the SATA IP core to the designated location through the AXI bridge, thus completing the read of hard drive data.
6. The acquisition device for a low-cost, lightweight recorder according to claim 5, characterized in that, The SATA IP core is a management module developed for hard drives that support the SATA protocol. It can be configured in SATA 1.0, SATA 2.0, and SATA 3.0 modes. The Microblaze soft core reads and writes register data to the SATA IP core through the AXI bridge. FIFO IP core 0 and FIFO IP core 1 are used for data buffering.