Package structure

Abstract

Some embodiments of the present application provide a package structure comprising: a conductive layer; the tube core is arranged on the conductive layer, and the tube core comprises an upper surface far away from the conductive layer; a lead connecting the upper surface and the conductive layer; the lead is connected with the upper surface and the conductive layer, and the width of the lead is different from that of the pin in a cross-sectional view transversely penetrating through the tube core. By using the conductive layer and using the pins as the heat conduction areas, the double-sided heat dissipation structure is provided, the electric path is shortened, and the efficiency is improved.

Description

Technical Field

[0001] This application relates to the field of power device technology, and more specifically, to a packaging structure. Background Technology

[0002] With the increasing demand for high-output power (100kW~10MW) inverters in future vehicles such as high-efficiency electric vehicles, electric buses, and electrified high-speed railways, current electric vehicles typically use one SiC (silicon carbide) inverter for the front wheels and an IGBT (insulated-gate bipolar transistor) inverter for the rear wheels to meet performance and driving range requirements. In this context, future developments are driving the integration of thinner / high-heat-dissipation inverters with each wheel—that is, four or more inverters for all four wheels—to further improve vehicle efficiency. The space saved by thinner inverters can be used to increase battery volume, further enhancing the driving range of future vehicles.

[0003] In addition, such as Figure 1A As shown, in a conventional automotive inverter 10, a die 13 (such as a semiconductor die) is attached to a ceramic substrate 12 via solder 17, wherein copper electrodes 12C are disposed on the upper and lower surfaces of the ceramic substrate 12. Furthermore, the die 13 is further externally connected via wire bonding 19 to a pad 20 above it and is sealed by a molding compound 18. Further, the ceramic substrate 12 is attached to a base plate 15 via solder 16, and the base plate 15 is disposed on a substrate 14, such as a PCB (printed circuit board), and the substrate 14 is disposed on a cold plate 11. It is evident that in existing automotive inverters 10, the power module is thick and bulky; it is mostly connected to the inverter mainboard (e.g., die 13) via external pins (pins or square pins of a lead frame), resulting in relatively poor electrical performance. Heat dissipation is mostly achieved by connecting the heat dissipation structure (such as the cold plate 11 (or heat dissipation fins)) to the substrate 14, rather than by directly contacting the heat source such as the Power IC (power integrated circuit (e.g., die 13)) for heat dissipation.

[0004] As can be seen, the composition of current automotive inverter power modules (from top to bottom) is as follows:

[0005] Case type: PCB (substrate 14) and case housing (outer shell, not shown) + base plate 15 such as DCB (direct copper-clad ceramic) / AMB (active metal brazing) substrate + bottom heat dissipation cold plate 11 (base);

[0006] Mold type: PCB (substrate 14) and Mold (molding compound 18) + base plate 15 such as DCB (direct copper clad ceramic) / AMB (active metal brazing) substrate + bottom heat dissipation cold plate 11 (substrate).

[0007] Both of the above types require a base plate 15 (approximately 1mm thick) such as DCB (Direct Copper Ceramic) / AMB (Active Metal Brazing) substrates, and the electrical conduction path is relatively long (Die 13 in automotive inverters → Cu layer (copper layer, such as copper layer 12C) of SBT (substrate, such as ceramic substrate 12) → Wire bond, Wedge bond, or L / F (different types of frames) → pins to substrate 14 such as PCB, resulting in greater heat loss. In addition, most current automotive inverter power modules of Case type and Mold type are currently single-sided heat dissipation, and it is not easy for the die 13 to be directly dissipated by the product (Case) or molding compound, so it needs to be connected to the cold plate 11 through substrate 14 such as PCB.

[0008] See Figure 1B In the SiP (System-in-Package) structure of the automotive IGBT inverter 10', the upper surface 12s of the ceramic substrate 12 is mainly equipped with a SiC (silicon carbide) MOSFET (metal-oxide-semiconductor field-effect transistor) 13', and a cold plate 11 is provided on the lower surface 12d. The cold plate 11 is connected to the ceramic substrate 12 to facilitate heat dissipation. Since the area of ​​the lower surface 12d is occupied by heat dissipation structures (such as the cold plate 11), the signal line L output can only be transmitted upwards to connect to a substrate 14 such as a PCB, and thus the heat conduction efficiency at the top will be limited.

[0009] Figures 1C to 1K The corresponding process flow for the SiP (System-in-Package) structure of the automotive IGBT inverter 10' is shown. See also... Figure 1C A SiC MOSFET 13' is attached to the surface 12s of the ceramic substrate 12, see [reference]. Figure 1D This forms lead 19'. See afterward. Figure 1E Solder 21 is formed at the joint location. Next, see... Figure 1F The metal connector 22 is formed by reflow soldering, and the metal connector 22 is connected to the ceramic substrate 12 and the SiC MOSFET 13' by solder 21, and then as follows Figure 1G As shown, a SiC MOSFET 13' and corresponding partial metal connectors 22 are molded using molding compound 23. See also Figure 1H This forms pin 24. See also Figure 1IThe cold plate 11 is attached to the ceramic substrate 12 using a thermal interface material (TIM) 25. Finally, see Figure 1J The substrate 14 is attached to the pin 24. Figure 1K It shows the relationship with Figure 1B Similarly, the corresponding automotive IGBT inverter 10' has a SiP (System-in-Package) structure, and the signal line L output can only be transmitted upwards to a substrate 14 such as a PCB, thus limiting the upward heat conduction efficiency. Utility Model Content

[0010] To address the aforementioned issues, this application applies a thin and heat-reducing panel-level fan-out structure to automotive inverters, thereby integrating the circuit path with the ceramic substrate into a single thermally and electrically conductive component (such as a conductive layer) to expose the pins of MOSFET dies as thermally conductive areas.

[0011] Some embodiments of this application provide a packaging structure characterized by comprising: a conductive layer; a die disposed on the conductive layer, wherein the die includes an upper surface remote from the conductive layer; a lead connecting the upper surface to the conductive layer; and a pin connecting the upper surface to the conductive layer, wherein, in a cross-sectional view transversely through the die, the width of the lead is different from the width of the pin.

[0012] In some embodiments, in a cross-sectional view transversely through the die, the width of the lead is smaller than the width of the pin.

[0013] In some embodiments, the packaging structure further includes a molding compound that encapsulates the die and exposes the pins.

[0014] In some embodiments, a gap exists between the molding compound and the pin.

[0015] In some embodiments, the gap gradually increases in the direction away from the die.

[0016] In some embodiments, the pin is thermally connected to the die.

[0017] In some embodiments, the pin is L-shaped.

[0018] In some embodiments, the L-shape has a horizontal portion and a vertical portion extending vertically from the horizontal portion, wherein the horizontal portion is thermally connected to the die.

[0019] In some embodiments, the conductive layer includes a heat dissipation via and a wire connecting the heat dissipation via, and the heat dissipation via and the wire are conductive, wherein the vertical portion is connected to the wire and spaced apart from the die.

[0020] In some embodiments, the die includes a field-effect transistor, the gate of which is electrically connected to the lead, the source of which is electrically connected to the lead, and the drain of which faces the conductive layer.

[0021] In some embodiments, the number of heat dissipation holes is multiple, and the multiple heat dissipation holes are stacked vertically.

[0022] In some embodiments, the packaging structure further includes a substrate located beneath the conductive layer.

[0023] In some embodiments, the conductive layer is connected to the substrate via an external connector.

[0024] In some embodiments, the external connector is a pin insert or a metal pad.

[0025] In some embodiments, the substrate is a printed circuit board.

[0026] In some embodiments, the leads and pins are distributed on different sides of the die.

[0027] In some embodiments, the horizontal portion is connected to the core via a sintered material.

[0028] Other embodiments of this application provide a packaging structure including: a conductive layer; a die disposed on the conductive layer, wherein the die includes an upper surface remote from the conductive layer; a lead connecting the upper surface to the conductive layer; and a pin having a horizontal portion and a vertical portion extending perpendicularly from the horizontal portion, wherein the horizontal portion of the pin is connected to the die, and the vertical portion of the pin is connected to the conductive layer.

[0029] In some embodiments, in a cross-sectional view transversely through the die, the width of the lead is smaller than the width of the pin.

[0030] In some embodiments, the packaging structure further includes a molding compound that encapsulates the die and exposes a horizontal portion of the pin, wherein there is a gap between the molding compound and the horizontal portion of the pin.

[0031] This application provides a double-sided heat dissipation structure by using a conductive layer (one conductive layer) and using pins as heat conduction areas, which shortens the electrical path and improves performance. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figures 1A to 1K The packaging structure in the prior art is shown.

[0034] Figures 2 to 2A as well as Figure 3 The packaging structure according to some embodiments of this application is shown.

[0035] Figures 4 to 18 The process flow for forming a packaging structure according to some embodiments of this application is shown. Detailed Implementation

[0036] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art are within the scope of protection of this application. In addition, when using terms such as "approximately," "about," "substantial," or "basically" to describe numerical values ​​or numerical ranges, unless otherwise stated, the term is intended to cover values ​​within ±10% of the described value. For example, the term "about 5nm" covers a size range from 4.5nm to 5.5nm.

[0037] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of elements and arrangements will be described below to simplify the present invention. These are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of the present invention. Such repetition is merely for brevity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0038] This application includes leads and pins of different sizes on the upper surface of the die, wherein the pins connecting to the source of the die have a larger size, which can be used for electrical connection and signal transmission as well as for heat conduction.

[0039] This application integrates the circuit path and the ceramic substrate into a single conductive layer (conductive and thermally conductive component). Specifically, see [link to relevant documentation]. Figure 2 Some embodiments of this application provide a packaging structure 100, which includes: a conductive layer 101; a die 102 disposed on the conductive layer 101, wherein the die 102 includes an upper surface 102s and a lower surface 102d away from the conductive layer 101; a lead 103 connecting the upper surface 102s of the die 102 to the conductive layer 101; and a pin 104 connecting the upper surface 102s of the die 102 to the conductive layer 101, wherein, in such cases... Figure 2 In the cross-sectional view shown, transversely passing through die 102, the width of lead 103 differs from the width of pin 104. Furthermore, in... Figure 2 In the cross-sectional view shown, transversely passing through die 102, the width of lead 103 is smaller than the width of pin 104. The width of lead 103 is smaller than the width of pin 104 in both the horizontal direction H and the direction E. Figure 2 As shown, the lead 103 and pin 104 are distributed on different sides of the die 103. In a further embodiment, the lead 103 is connected to the heat dissipation via 101V of the conductive layer 101 via solder 110, as shown. Figure 2 As shown, the solder 110 has a circular shape. In some embodiments, the leads 103 and pins 104 may include metals such as copper, gold, silver, etc.

[0040] Furthermore, the package structure 100 also includes a molding compound 105 that encapsulates the die 102 and exposes the leads 104. In some embodiments, the molding compound 105 includes, but is not limited to, molding compounds. Further, from Figure 2 As can be seen, there is a gap V between the molded compound 105 and the lead 104. This gap V gradually increases in the direction E away from the die 102. Specifically, the width of this gap V in the horizontal direction H gradually increases in the direction E away from the die 102. Figure 2 As can be seen, the top surface 104s of the pin 104 is exposed, and the gap V between the pin 104 and the molding compound 105 facilitates heat dissipation. Furthermore, the presence of the gap V prevents bridging of the corresponding thermal interface material (TIM) if a thermal interface material (TIM) is subsequently formed on the corresponding pin 104, and can increase the area of ​​the TIM by approximately 15%-20%. In some embodiments, the pin 104 is thermally connected to the die 102. Further, the pin 104 is L-shaped, and the L-shape has a horizontal portion 104L and a vertical portion 104H extending vertically from the horizontal portion 104L, wherein the horizontal portion 104L is thermally connected to the die 102. In some embodiments, the horizontal portion 104L is connected to the die 102 via a sintered material 108. Figure 2As shown, the vertical portion 104H of the pin 104 can be connected to the conductive layer 101 via solder 111 and pin support 112, specifically, to the heat dissipation via 101V of the conductive layer 101. In some embodiments, the sintering material 108 and the pin support 112 may include metals, such as, but not limited to, copper.

[0041] Continue to refer to Figure 2 ,from Figure 2 As can be seen, the conductive layer 101 includes a heat dissipation via 101V and a wire 101L connecting the heat dissipation via 101V, and the heat dissipation via 101V and the wire 101L are conductive. The vertical portion 104H of the pin 104 is connected to the wire 101L and spaced apart from the die 102. Figure 2 In the illustrated embodiment, the conductive layer 101 has multiple heat dissipation vias 101V, and these vias 101V are vertically stacked. In some other embodiments, the multiple heat dissipation vias 101V are vertically aligned. In still other embodiments, the multiple heat dissipation vias 101V are not aligned with each other. Further as... Figure 2 As shown, the plurality of heat dissipation vias 101V and the corresponding conductive lines 101L are respectively embedded in the corresponding dielectric layers 101P. In some embodiments, the heat dissipation vias 101V and the conductive lines 101L are made of metal, including but not limited to metals such as copper, gold, and silver. In some embodiments, the dielectric layer 101P includes but is not limited to polyimide, polypropylene, etc.

[0042] In a further embodiment, die 102 includes a field-effect transistor, such as a metal-oxide-semiconductor field-effect transistor (MOSFET), and more particularly, such as a silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor. Figure 2 As shown, the gate G of the transistor is electrically connected to lead 103, the source S of the transistor is electrically connected to pin 104, and the drain D of the transistor faces the conductive layer 101. Furthermore, the drain D of the transistor is connected to the conductive layer 101 via solder 113.

[0043] In a further embodiment, the package structure 100 also includes a substrate 106 located beneath the conductive layer 101. In some specific embodiments, the substrate 106 may be a printed circuit board (PCB). In some embodiments, the conductive layer 101 is connected to the substrate 106 via an external connector 107. Figure 2 In the illustrated embodiment, the external connector 107 is a pin insert, i.e., the base 106 is connected by inserting the pin insert into the base 106. In some embodiments, the pin insert is as follows: Figure 2 The locking mechanism is shown and is made of a metal such as copper. In some embodiments, the external connector 107 is connected to the conductive layer 101 via solder 107'. See also Figure 3 , Figure 3 Another packaging structure 100' according to an embodiment of this application is shown, in Figure 3 In the illustrated embodiment, the external connector 107 is a metal pad, such as a copper pad. Figure 3 As shown, the metal pad is connected to the substrate 106 and the conductive layer 101 via solder 107' above and below it, and optionally, a bonding layer 107" exists between the metal pad and the conductive layer 101. The bonding layer 107" can be a cured metal layer, such as a cured copper metal layer.

[0044] This application includes leads 103 and pins 104 of different sizes on the upper surface 102s of the die 102, and the L-shaped pins 104 connected to the source S of the die 102, such as a MOSFET, have a larger size, which can serve as both electrical connection for signal transmission and heat conduction. Furthermore, the package structure 100 provided by this application can dissipate heat on both sides, and its heat dissipation path and electrical conduction paths L1 and L2 are as follows... Figure 2A As shown, this allows for a shorter electrical path while simultaneously dissipating heat.

[0045] Continue to refer to Figure 2 This application provides a packaging structure 100, which includes: a conductive layer 101; a die 102 disposed on the conductive layer 101, wherein the die 102 includes an upper surface 102s away from the conductive layer 101; a lead 103 connecting the upper surface 102s to the conductive layer 101; and a pin 104 having a horizontal portion 104L and a vertical portion 104H extending vertically from the horizontal portion 104L, wherein the horizontal portion 104L of the pin 104 is connected to the die 102, and the vertical portion 104H of the pin 104 is connected to the conductive layer 101. Figure 2 In the cross-sectional view shown laterally through die 102, the width of lead 103 is smaller than the width of pin 104. The package structure 100 also includes a molding compound 105 that encapsulates die 102 and exposes the horizontal portion 104L of pin 104, wherein a gap V exists between the molding compound 105 and the horizontal portion 104L of pin 104.

[0046] In summary, in the packaging structures 100 and 100' provided in this application, the FORDL (fan-out redistribution) technology (i.e., using an integral conductive layer 101) enables the die 102 to conduct electricity directly up and down (i.e., the heat dissipation path and the electrical conduction paths L1 and L2), thereby reducing heat loss and improving module efficiency.

[0047] Furthermore, in this application, a cold plate 114 can be attached below the substrate 106 (such as a PCB) of the package structures 100 and 100' (see...). Figure 14 and Figure 18 Therefore, in addition to being able to conduct heat directly up and down to the lower substrate 106 and cold plate 114 through the FO Panel (fan-out package), the heat dissipation path can also be connected to the metal heat dissipation structure through the thermal interface material (TIM) to dissipate heat to the top surface.

[0048] Furthermore, the power module with the 100 / 100' packaging structure provided in this application has a withstand voltage of over 1200V, achieving a 10% power increase compared to existing technologies at the same voltage; reducing heat loss by 10-15%; and reducing the power module thickness by over 20%. The 100 / 100' packaging structure provided in this application differs from current automotive inverter power modules, possessing the technical capability of Fan-out RDLPanel (fan-out redistribution structure packaging). Therefore, the 100 / 100' packaging structure provided in this application combines improved performance with advanced technology.

[0049] Next, refer to Figures 4 to 14 Let me introduce Figure 2 The process flow for forming the packaging structure 100 shown.

[0050] Reference Figure 4 A conductive layer 101 is provided, which is attached to a carrier 1001 via an adhesive layer 1002. In some embodiments, the carrier 1001 may be a silicon carrier or any other suitable carrier. The adhesive layer 1002 may be an adhesive layer. Further, the conductive layer 101 has a plurality of dielectric layers 101P and a plurality of heat dissipation vias 101V embedded in the dielectric layers, as well as wires 101L connecting the respective heat dissipation vias 101V. The dielectric layers 101P may be formed from polyimide by a deposition process of physical vapor deposition or chemical vapor deposition, and the heat dissipation vias 101V and wires 101L may be formed from a metal such as copper by a plating process or electroless plating process or an inlay process commonly used in the art. In addition, the number of dielectric layers 101P and the corresponding heat dissipation vias 101V and wires 101L formed may be determined according to the actual situation until a conductive layer 101 of the desired thickness is formed. Furthermore, after providing the conductive layer 101, the lower surface 102d of the die 102 is attached to the conductive layer 101 using solder 109, wherein the drain D of the die 102 faces the conductive layer 101. Additionally, as further as... Figure 4 As shown, the pin support 112 is also attached to the conductive layer 101 by solder 111. In some embodiments, the pin support 112 includes a metal, such as copper.

[0051] Next, see Figure 5The L-shaped pin 104 is attached to the die 102 and the conductive layer 101, wherein the horizontal portion 104L of the pin 104 is connected to the die 102 (such as to the source S of a transistor). Specifically, after the horizontal portion 104L of the pin 104 is attached to the die 102 using a sintering material 108 such as metal, sintering is performed to shape the sintering material 108, thereby forming a structure as shown in the image. Figure 5 The shape shown. Further, the vertical portion 104H of the pin 104 is attached to the conductive layer 101 via the pin support 112 and solder 111. Further, a lead 103 is formed by a wire bonding process, thereby connecting the die 102 (such as the gate G of a transistor) to the conductive layer 101; further, the lead 103 is connected to the conductive layer 101 via solder 110. In summary, for a die 102 such as a transistor, the gate G of the transistor is electrically connected to the lead 103, the source S of the transistor is electrically connected to the pin 104, and the drain D of the transistor faces the conductive layer 101. Further, in Figure 5 In the cross-sectional view shown, the width of pin 104 is greater than the width of lead 103.

[0052] See Figure 6 Using molding compound to form molding compound 105, such as Figure 6 As shown, molding compound 105 molds pins 104 and die 102 therein, and the top surface 105t of molding compound 105 is higher than pins 104. Next, see... Figure 7 The molding compound 105 is ground using a grinding process, thereby exposing the pin 104 from the top surface 105t of the molding compound 105. In some embodiments, the top surface of the pin 104 may be flush with or slightly higher than the top surface 105t of the molding compound 105. Subsequently, a gap V is formed between the pin 104 and the molding compound 105 using a laser ablation process. The presence of gap V exposes a portion of the surface of the pin 104, thus facilitating heat dissipation. Furthermore, if a thermal interface material (TIM) is subsequently formed on the corresponding pin 104, the presence of gap V can prevent bridging of the corresponding TIM material and can increase the area of ​​the TIM material by approximately 15%-20%.

[0053] See Figure 8 A carrier 1003 is attached above the pin 104 and the top surface 105t of the molding compound 105, such as via an adhesive layer 1004. This carrier 1003 and adhesive layer 1004 can be similar to or the same as the carrier 1001 and adhesive layer 1002 discussed above, and will not be elaborated further here. See also... Figure 9 ,Will Figure 8 The structure is flipped, and the carrier 1001 is removed by a peeling process.

[0054] See Figure 10 The lead substrate 107A is attached to the surface of the conductive layer 101 opposite to the die 102 by means of solder 107' or a soldering process. In some embodiments, the lead substrate 107A is made of a metal such as copper.

[0055] See afterward. Figure 11 An adhesive tape 1005, such as a tape commonly used in the art, is formed over the lead substrate 107A. After forming the adhesive tape 1005, see [link to documentation]. Figure 12 ,Will Figure 11 The structure shown is flipped over, and the carrier 1003 is removed, for example, through a peeling process. The structure is then cut using a blade S to form... Figure 12 The structure shown.

[0056] Next, see Figure 13 ,Will Figure 12 The structure shown is flipped over and placed on carrier 1006 (any suitable carrier is acceptable, such as a silicon carrier, glass carrier, etc.). Then, the pin insert 107B is inserted and fixed to the pin substrate 107A, thereby forming a pin insert as an external connector 107.

[0057] Finally, see Figure 14 ,Will Figure 13 The structure shown is flipped, and a slightly inserted member, serving as an external connector 107, is connected to the substrate 106, such as a PCB, thereby forming... Figure 2 The packaging structure 100 is shown. Furthermore, as... Figure 14 As shown, a cold plate 114, commonly used in the art, can be attached below the substrate 106 for further heat dissipation.

[0058] Next, see Figures 15 to 18 To describe Figure 3 The process flow for forming the package structure 100' shown.

[0059] The process for forming the package structure 100' is the same as described above. Figures 4 to 9 The process for forming the package structure 100 shown is basically the same, except that, in the above... Figure 10 When forming the pin substrate 107A, see [link / reference]. Figure 15 Metal pads 107 are formed on the surface of the conductive layer 101 opposite to the die 102. The pads 107 are formed on the surface of the conductive layer 101 by processes such as soldering 107', welding, or sintering. Furthermore, an bonding layer 107" may be formed between the pads 107 and the solder 107'. Afterwards... Figure 16 and Figure 17 The steps are the same as those mentioned above. Figures 11 to 12 The steps described are the same and will not be described in detail here.

[0060] Finally, see Figure 18 ,Will Figure 17 The structure shown is flipped and connected to the base 106 via an external connector 107, thereby forming Figure 3 The package structure 100' is shown. Furthermore, as... Figure 18 As shown, a cold plate 114, commonly used in the art, can be attached below the substrate 106 for further heat dissipation.

[0061] In summary, this application applies a thin and heat-reducing panel-level fan-out structure to an automotive inverter, thereby integrating the circuit path with the ceramic substrate into a single thermally and electrically conductive component (conductive layer 101) to expose the pins 104 connected to the die 102 as a thermally conductive area.

[0062] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A packaging structure, characterized in that, include: Conductive layer; A die is disposed on the conductive layer, wherein the die includes an upper surface remote from the conductive layer; Lead wires connect the upper surface to the conductive layer; Pins connect the upper surface to the conductive layer. In a cross-sectional view that passes laterally through the die, the width of the lead wire is different from the width of the pin.

2. The packaging structure according to claim 1, characterized in that, In a cross-sectional view transversely through the die, the width of the lead is smaller than the width of the pin.

3. The packaging structure according to claim 1, characterized in that, Also includes: A molding compound is used to encapsulate the die and expose the pins.

4. The packaging structure according to claim 3, characterized in that, There is a gap between the molding compound and the pin.

5. The packaging structure according to claim 4, characterized in that, The gap gradually increases in the direction away from the core.

6. The packaging structure according to claim 3, characterized in that, The pin is thermally connected to the die.

7. The packaging structure according to claim 3, characterized in that, The pin is L-shaped.

8. The packaging structure according to claim 7, characterized in that, The L-shape has a horizontal portion and a vertical portion extending perpendicularly from the horizontal portion. The horizontal portion is thermally connected to the core.

9. The packaging structure according to claim 8, characterized in that, The conductive layer includes heat dissipation vias and wires connecting the heat dissipation vias, and the heat dissipation vias and the wires are conductive. The vertical portion is connected to the conductor and spaced apart from the tube core.

10. The packaging structure according to claim 1, characterized in that, The die includes a field-effect transistor, the gate of which is electrically connected to the lead, the source of which is electrically connected to the lead, and the drain of which faces the conductive layer.

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