Substrate structure with through silicon vias
By filling the gaps with an insulating polymer layer applied by spin coating and baked at low temperature on a silicon through-hole substrate, the high cost and processing risk of 3D silicon through-hole technology are solved, achieving low-cost and high-efficiency packaging.
Patent Information
- Application Number
- CN202422791893.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-15
- Publication Date
- 2025-10-28
- Estimated Expiration
- 2034-11-15
AI Technical Summary
Existing 3D through-silicon via (TSV) technology suffers from expensive manufacturing processes and high processing risks, making it difficult to achieve low-cost and efficient wafer packaging, especially with poor packaging yield under the requirement of small-pitch packaging.
An insulating polymer layer, applied by spin coating and baked at low temperature, fills the gaps in the silicon through-hole substrate, providing excellent copper migration inhibition and eliminating the cost of expensive chemical vapor deposition. The insulating polymer layer covers the back insulation of the silicon through-hole chip to ensure smooth process and electrical quality.
It reduced packaging costs, improved packaging yield, ensured electrical quality, and enabled low-temperature operation, avoiding copper migration issues.
Smart Images
Figure CN223487052U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to a semiconductor packaging technology, and more particularly to a substrate structure with silicon through-holes and its fabrication method. Background Technology
[0002] The miniaturization of integrated circuits (ICs) has advanced to an extremely small scale of tens of nanometers. Wafer modules must meet the requirements of being thin, light, small, low-cost, low-power, high-efficiency, highly multifunctional heterogeneous integration, and ready to market. Therefore, both wafer-level manufacturing technology and wafer-level packaging technology need to be accelerated. While flip-chip packaging, commonly used in high-end products, can solve the wafer packaging problem for short connections, it can only perform single-layer wafer packaging. Furthermore, with the rapid increase in the number of transistors and I / O pins, flip-chip packaging is gradually becoming unable to meet the packaging requirements of bump gaps less than 150μm.
[0003] Taking system-in-package (SIP) technologies such as multi-chip package (MCP), package on package (POP), and package in package (PIP) as examples, the expansion of packaging layout from two-dimensional to three-dimensional increases the difficulty of packaging technology. However, 3D integrated circuits through silicon via (3D IC TSV) technology enables wafers to evolve from two-dimensional planar layout to three-dimensional vertical stack layout. Its three-dimensional interconnect technology using 3D IC TSV has advantages such as shorter wire interconnect paths, lower resistance and inductance, and more efficient transmission of signals, power and heat.
[0004] The fabrication process for 3D through-silicon vias (TSVs) includes TSV etching, TSV filling, substrate bonding, wafer thinning, and substrate removal. Related technologies include TSV forming, wafer manipulation, wafer thinning, bonding and assembly, and wafer testing. These technologies involve costly process steps, such as dry etching of the photomask, chemical vapor deposition (CVD) using expensive materials or equipment, and chemical-mechanical planarization (CMP). Furthermore, the TSV etching, substrate bonding, and wafer thinning steps are subject to processing risks; insufficient wafer support can lead to wafer breakage and poor yield. Utility Model Content
[0005] To address the aforementioned problems, this invention provides a substrate structure with silicon through-holes and its fabrication method, which can reduce packaging costs. In the step of thinning an insulating polymer recess on the silicon through-hole substrate to form metal pad openings, an insulating polymer layer, spin-coated and baked at low temperature, fills any gaps or gaps that may exist at the interface between different material layers, providing excellent copper migration inhibition. This enables low-temperature operation and ensures smooth subsequent processes and the electrical quality of the product.
[0006] To address the aforementioned problems, this invention provides a substrate structure with silicon through-holes and its fabrication method. By applying a low-temperature baked insulating polymer layer to the back insulation of the silicon through-hole chip, good copper migration suppression can be provided, while saving the cost of expensive chemical vapor deposition.
[0007] According to the above, a substrate structure with through-silicon vias includes: a substrate having a first surface and a second surface opposite to each other; a plurality of through-silicon via structures disposed in the substrate and perpendicularly penetrating between the first surface and the second surface of the substrate, wherein each of the plurality of through-silicon via structures includes a conductive pad, a through electrode, and a liner, wherein the conductive pad is adjacent to the first surface of the substrate; the liner is located between the substrate and the through electrode; and a first surface of the through electrode contacts the conductive pad, a second surface of the through electrode is adjacent to the second surface of the substrate; and an insulating polymer layer covers the second surface of the substrate, wherein at least a portion of the through electrode and the corresponding liner of each of the plurality of through-silicon via structures protrudes from the second surface of the substrate, and the insulating polymer layer conformally covers the protruding through electrode and the liner.
[0008] Preferably, the substrate structure with silicon through-holes further includes a plurality of front bumps disposed on the first surface of the substrate, wherein the plurality of front bumps correspond to and are attached to the conductive pad respectively.
[0009] Preferably, the substrate structure with through-silicon vias further includes a first insulating layer located on the first surface of the substrate and exposing the plurality of front bumps.
[0010] Preferably, the insulating polymer layer is made of polyimide.
[0011] Preferably, the material of the through electrode is copper, silver or tin metal, or a copper, silver or tin metal alloy, or a copper, silver or tin metal compound, and the material of the liner is silicon dioxide.
[0012] According to the above, a substrate structure with through-silicon vias includes: a substrate having a first surface and a second surface opposite to each other; a plurality of through-silicon via structures disposed in the substrate and perpendicularly penetrating between the first surface and the second surface of the substrate, wherein each of the plurality of through-silicon via structures includes a conductive pad, a through electrode, and a liner, wherein the conductive pad is adjacent to the first surface of the substrate, the liner is located between the substrate and the through electrode, and a first surface of the through electrode contacts the conductive pad, a second surface of the through electrode is adjacent to the second surface of the substrate, and at least a portion of the through electrode and the corresponding liner of each of the plurality of through-silicon via structures protrudes from the second surface of the substrate; and an insulating polymer layer covers the second surface of the substrate, and the insulating polymer layer on the second surface of the substrate is flush with each of the plurality of through-silicon via structures and the liner.
[0013] Preferably, the substrate structure with through-silicon vias further includes a plurality of front bumps and a first insulating layer disposed on the first surface of the substrate, wherein the plurality of front bumps correspond to and are attached to the conductive pads respectively, and the first insulating layer exposes the plurality of front bumps.
[0014] Preferably, the substrate structure with through-silicon vias further includes a plurality of bump under-metal layers and corresponding plurality of solder balls disposed on each of the plurality of through-silicon via structures on the second surface of the substrate.
[0015] Preferably, the substrate structure having through-silicon vias further includes a wiring layer disposed on each of the plurality of through-silicon via structures on the second surface of the substrate.
[0016] According to the above, a substrate structure with through-silicon vias includes: a substrate having a first surface and a second surface opposite to each other; a plurality of through-silicon via structures disposed in the substrate and perpendicularly penetrating between the first surface and the second surface of the substrate, wherein each of the plurality of through-silicon via structures includes a conductive pad, a through electrode, and a liner, wherein the conductive pad is adjacent to the first surface of the substrate, the liner is located between the substrate and the through electrode, a first surface of the through electrode contacts the conductive pad, a second surface of the through electrode is adjacent to the second surface of the substrate, at least a portion of the through electrode and the corresponding liner of each of the plurality of through-silicon via structures protrudes from the second surface of the substrate, and an insulating polymer layer covers the second surface of the substrate, exposing at least a portion of each of the plurality of through-silicon via structures and the liner in the insulating polymer layer.
[0017] Preferably, the substrate structure having through-silicon vias further includes a plurality of bump under-metal layers and corresponding plurality of solder balls disposed on each of the plurality of through-silicon via structures exposed by the insulating polymer layer, or further includes a redistribution layer disposed on each of the plurality of through-silicon via structures exposed by the insulating polymer layer. Attached Figure Description
[0018] Figure 1 This is a partial cross-sectional schematic diagram of the substrate structure with silicon through-holes according to the first embodiment of this utility model.
[0019] Figure 2 This is a partial cross-sectional schematic diagram of the fabrication of a substrate structure with silicon through-holes according to the first embodiment of this utility model.
[0020] Figure 3 This is a partial cross-sectional schematic diagram of the fabrication of a substrate structure with silicon through-holes according to the first embodiment of this utility model.
[0021] Figure 4 This is a partial cross-sectional schematic diagram of the fabrication of a substrate structure with silicon through-holes according to the first embodiment of this utility model.
[0022] Figure 5 Then it is Figure 4 Enlarged schematic diagram of the area within the dashed line.
[0023] Figure 6 This is a partial cross-sectional schematic diagram of the fabrication of a substrate structure with silicon through-holes according to the first embodiment of this utility model.
[0024] Figure 7 Then it is Figure 6 Enlarged schematic diagram of the area within the dashed line.
[0025] Figure 8 This is a partial cross-sectional schematic diagram of the fabrication of a substrate structure with silicon through-holes according to the first embodiment of this utility model.
[0026] Figure 9 This is a partial cross-sectional schematic diagram of the fabrication of a substrate structure with silicon through-holes according to the second embodiment of this utility model.
[0027] Figure 10 for Figure 8 A partial cross-sectional view of the substrate structure with silicon through-holes that was subsequently fabricated.
[0028] Figure 11 Then it is Figure 9 A partial cross-sectional view of the substrate structure with silicon through-holes that was subsequently fabricated.
[0029] List of reference numerals
[0030] 10 substrates
[0031] 11 Second page
[0032] 13 First page
[0033] 20 conductive pads
[0034] 23 First page
[0035] 30 through electrode
[0036] 31 Second page
[0037] 32 electrode metal layers
[0038] 33 First page
[0039] 34 solder balls
[0040] 36-layer wiring
[0041] 40 Lining
[0042] 41 Second page
[0043] 50 First Insulation Layer
[0044] 52-bump under-metal layer
[0045] 54 solder balls
[0046] 60 insulating polymer layers
[0047] 65 opening Detailed Implementation
[0048] The preferred embodiments of the present invention will now be described with reference to the accompanying drawings. These specific embodiments are intended to illustrate the present invention in detail and should not be construed as limiting it. Various modifications and variations can be made without departing from the spirit and scope of the present invention, and all such modifications should be included within the protection scope of the present invention. Unless otherwise stated or defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art. In the context of combining the technical solutions of the present invention with real-world scenarios, all technical and scientific terms used herein may also have meanings corresponding to the purpose of achieving the technical solutions of the present invention. The terms "first," "second," etc., used herein are merely for distinguishing names and do not represent a specific number or order. The term "and / or," as used herein, includes any and all combinations of one or more of the associated listed items.
[0049] Figure 1 This is a partial cross-sectional schematic diagram of the substrate structure with through-silicon vias according to the first embodiment of this utility model. Please refer to... Figure 1The substrate structure with through-silicon vias includes a substrate 10, one or more conductive pads 20, through-electrodes 30, and a substrate 40. The substrate 10 has a first side 13 and a second side 11 facing each other; the first side 13 is generally referred to as the front side, and the second side 11 as the back side. Furthermore, the substrate 10 can be a substrate used in the manufacture of semiconductor memory components, semiconductor logic components, optoelectronic components, display units, etc. The front side generally corresponds to the side adjacent to the active region where active components such as field-effect transistors and analog integrated circuits are formed, or passive components such as resistors, capacitors, and connectors are formed. Moreover, in one embodiment, the substrate 10 can be a silicon substrate.
[0050] Continued reference Figure 1 One or more conductive pads 20 are provided on a first surface 13 of a substrate 10. One or more through electrodes 30 are individually disposed vertically in the substrate 10 corresponding to the conductive pads 20. The first surface 33 of the through electrode 30 is closer to and attached to / contacts the conductive pads 20 than the second surface 31 of the through electrode 30, and the first surface 33 and the second surface 31 are opposite to each other. Alternatively, the first surface 33 of the through electrode 30 is adjacent to the first surface 13 of the substrate 10, and the second surface 31 of the through electrode 30 is adjacent to the second surface 11 of the substrate 10. Furthermore, the material of the through electrode 30 may include copper, silver, or tin metal / metal alloy / metal compound, but is not limited thereto. Moreover, a liner 40 is conformally disposed on the sidewall and the second surface 31 of each through electrode 30, so the liner 40 is located between the substrate 10 and the through electrode 30. The material of the liner 40 is an oxide, such as silicon dioxide, which can prevent metal atoms or metal ions of the through electrode 30 from diffusing into the substrate 10. Furthermore, the silicon through-hole structure referred to herein includes the conductive pad 20, the through electrode 30, and the liner 40.
[0051] Figure 2 This is a partial cross-sectional schematic diagram illustrating the fabrication of a substrate structure with through-silicon vias according to the first embodiment of this utility model. Please refer to... Figure 2 A first insulating layer 50 is first applied to the first surface 13 of the substrate 10, and then patterned to expose a portion of the first surface 23 of the conductive pad 20. In the first embodiment, the first insulating layer 50 may be applied to the second surface 13 of the substrate 10 by means of a suitable method, such as coating with a polymer or photocurable resin, and then patterned by a suitable exposure, development, and etching method.
[0052] Figure 3 This is a partial cross-sectional schematic diagram illustrating the fabrication of a substrate structure with through-silicon vias according to the first embodiment of this utility model. Please refer to... Figure 3An under bump metallurgy (UBM) layer 52 is disposed on the first surface 13 of the substrate 10, attaching to / contacting the exposed first surface 23 of the conductive pads 20 and corresponding to each conductive pad 20. Then, one or more solder balls 54 are respectively disposed on the under bump metallurgy layer 52, together forming front bumps of a substrate structure with through-silicon vias. In one embodiment, the under bump metallurgy layer 52 is formed on each conductive pad 20 using, for example, plasma-enhanced chemical vapor deposition (PECVD), and then solder balls 54 are formed on the under bump metallurgy layer 52 using methods such as evaporation, electroplating, printing, solder migration, or ball placement. The under bump metallurgy layer 52 is stacked on the conductive pads 20 and covers a portion of the first insulating layer 50. Furthermore, the under bump metallurgy layer 52 can be cylindrical in shape and can be formed from at least three layers of conductive material, such as a layer of nickel, a layer of tin-silver alloy, and a layer of copper, or alternatively, an alloy layer may be present above the copper layer with a nickel top layer. The solder balls 54 can be formed of one or more conductive materials, such as copper, nickel, tin, silver, titanium, tungsten, chromium, or alloys thereof, or a layer of tin-silver alloy and a layer of copper, or optionally, an alloy layer on top of the copper layer. In one embodiment, if a tin layer has already been formed on the under-bump metal layer 52, a reflow method can be used to form the tin layer into the desired ball shape. Other conductive materials well known in the art are also available, such as titanium / titanium-tungsten / copper arrangements, copper / nickel / gold arrangements, or copper / chromium-copper arrangements, and are therefore not limited thereto. Furthermore, the front bump formed by the under-bump metal layer 52 and the solder balls 54 is electrically connected to the through electrode 30 via the conductive pad 20.
[0053] Figure 4 This is a partial cross-sectional schematic diagram of the fabrication of a substrate structure with through-silicon vias according to the first embodiment of this utility model. Figure 5 Then it is Figure 4 An enlarged diagram of the area within the dashed line. Please refer to it. Figure 4 and Figure 5 The second surface 11 (back side) of the substrate 10 is thinned, for example by mechanical polishing followed by dry etching, until the through electrode 30 and the substrate 40 are exposed on the second surface 11 of the substrate 10. In one embodiment, mechanical polishing makes the exposed second surface 31 of the through electrode 30, the second surface 41 of the substrate 40, and the second surface 11 of the substrate 10 flush. Silicon dry etching then removes a portion of the substrate 10, making the second surface 11 of the substrate 10 lower than the second surface 31 of the through electrode 30 and the second surface 41 of the substrate 40, to prevent copper from migrating onto the silicon surface. Therefore, the actual situation is as follows: Figure 5As shown, the second surface 31 of the through electrode 30, the second surface 41 of the liner 40, and the second surface 11 of the substrate 10 are not on the surface of the alignment height. In this embodiment, the second surface 31 of the through electrode 30 and the second surface 41 of the liner 40 are higher than the second surface 11 of the substrate 10, that is, part of the through electrode 30 and the liner 40 will protrude from the second surface 11 of the substrate 10.
[0054] Figure 6 This is a partial cross-sectional schematic diagram of the fabrication of a substrate structure with through-silicon vias according to the first embodiment of this utility model. Figure 7 Then it is Figure 6 An enlarged diagram of the area within the dashed line. Please refer to it. Figure 6 and Figure 7 An insulating polymer layer 60 covers the second surface 11 of the substrate 10, the exposed through-electrode 30, and the liner 40. In one embodiment, the insulating polymer, such as polyimide, is conformally coated onto the second surface 11 of the substrate 10, the second surface 31 of the exposed through-electrode 30, and the second surface 41 of the liner 40 by spin coating and low-temperature curing. The conformally coated insulating polymer has a structural outline that aligns with the second surface 11 of the substrate 10, the second surface 31 of the exposed through-electrode 30, and the second surface 41 of the liner 40, and the curing temperature, for example but not limited to, 180°C to 200°C. Because the glass bonding adhesive used in silicon through-hole substrates is prone to decomposition and delamination at high temperatures, and some temperature-sensitive chip components / modules, such as memory, are highly sensitive to temperature and may fail due to high temperatures, the structure and manufacturing method provided by this invention, due to the material and application characteristics of the insulating polymer layer 60, allows the insulating polymer layer 60 to adhere tightly and fully fill the adjacent surfaces of any two materials, such as between the substrate 10 and the liner 40 or between the liner 40 and the through electrode 30. This avoids peeling defects on the adjacent surfaces of any two materials, which could lead to subsequent problems.
[0055] Figure 8 From Figure 6 The enlarged cross-sectional view of the first embodiment of this invention, within the area indicated by the dashed line, shows the fabrication of a substrate structure with through-silicon vias. Figure 9 From Figure 6 The enlarged cross-sectional view of the second embodiment of this invention, within the area indicated by the dashed line, shows the fabrication of a substrate structure with silicon through-holes. The formation of the insulating polymer layer 60 ensures material filling between any two interfaces of the substrate 10, the through-electrode 30, and the liner 40. Subsequent processing can then be performed in at least two ways, thinning the insulating polymer layer 60 completely until the through-electrode 30 and the liner 40 are exposed on the surface, such as... Figure 8As shown. Optionally, the insulating polymer layer 60 can be patterned to form a plurality of openings 65 to expose the through electrode 30 or further include exposing the liner 40, as shown. Figure 9 As shown. Therefore, regarding the insulating polymer layer 60 retained on the second surface 11 of the substrate 10, the insulating polymer layer 60 retained by the patterning method is thicker, while the insulating polymer layer 60 retained by the thinning method is thinner.
[0056] Figure 10 for Figure 8 A partial cross-sectional view of the subsequent fabrication of a substrate structure with through-silicon vias. Figure 11 Then it is Figure 9 A partial cross-sectional diagram of the subsequent fabrication of a substrate structure with through-silicon vias. See also the following reference: Figure 10 and Figure 11 An electrode metal layer 32 is formed on the exposed through electrode 30 and substrate 40 in an appropriate manner. Solder balls 34 can be formed directly on the electrode metal layer 32, or a redistribution layer 36 (RDL) can be formed on the insulating polymer layer 60 and connected to the electrode metal layer 32, or the redistribution layer 36 can be formed directly.
[0057] The above description is merely a preferred embodiment of the present utility model and is not intended to limit the scope of the present utility model. At the same time, the above description should be clear to those skilled in the art and can be implemented accordingly. Therefore, other equivalent changes or modifications made without departing from the concept disclosed in the present utility model should be included in the scope of the patent application.
Claims
1. A substrate structure with through-silicon vias, characterized in that, include: A substrate having a first surface and a second surface opposite to each other; A plurality of through-silicon vias are disposed in the substrate and perpendicularly penetrate between the first surface and the second surface of the substrate. Each of the plurality of through-silicon vias includes a conductive pad, a through electrode, and a substrate. The conductive pad is adjacent to the first surface of the substrate; The liner is located between the substrate and the through electrode; and A first surface of the through electrode contacts the conductive pad, and a second surface of the through electrode is adjacent to the second surface of the substrate; and An insulating polymer layer covers the second surface of the substrate, at least a portion of the through electrode and the corresponding liner of each of the plurality of through-silicon via structures protruding from the second surface of the substrate, and the insulating polymer layer conformally covers the protruding through electrode and the liner.
2. The substrate structure with silicon through-holes as described in claim 1 further includes a plurality of front bumps disposed on the first surface of the substrate, wherein the plurality of front bumps respectively correspond to and are attached to the conductive pad.
3. The substrate structure with through-silicon vias as claimed in claim 2, further comprising a first insulating layer located on the first surface of the substrate and exposing the plurality of front bumps.
4. The substrate structure with silicon through-holes as described in claim 1, 2, or 3, characterized in that, The insulating polymer layer is made of polyimide.
5. The substrate structure with silicon through-holes as described in claim 1, 2, or 3, characterized in that, The material of the through electrode is copper, silver or tin metal, or a copper, silver or tin metal alloy, or a copper, silver or tin metal compound, and the material of the liner is silicon dioxide.
6. A substrate structure with through-silicon vias, characterized in that, include: A substrate having a first surface and a second surface opposite to each other; A plurality of through-silicon vias are disposed in the substrate and perpendicularly penetrate between the first surface and the second surface of the substrate. Each of the plurality of through-silicon vias includes a conductive pad, a through electrode, and a substrate. The conductive pad is adjacent to the first surface of the substrate; The liner is located between the substrate and the through electrode; and A first surface of the through electrode contacts the conductive pad, a second surface of the through electrode is adjacent to the second surface of the substrate, and at least a portion of the through electrode and the corresponding liner of each of the plurality of silicon through-hole structures protrude from the second surface of the substrate. as well as An insulating polymer layer covers the second surface of the substrate, and the insulating polymer layer on the second surface of the substrate is flush with each of the plurality of through-silicon via structures and the liner.
7. The substrate structure with through-silicon vias as described in claim 6 further includes a plurality of front bumps and a first insulating layer disposed on the first surface of the substrate, wherein the plurality of front bumps correspond to and are attached to the conductive pads respectively, and the first insulating layer exposes the plurality of front bumps.
8. The substrate structure with through-silicon vias as described in claim 6 or 7, further comprising a plurality of bump under-metal layers and corresponding plurality of solder balls disposed on each of the plurality of through-silicon via structures on the second surface of the substrate, or further comprising a redistribution layer disposed on each of the plurality of through-silicon via structures on the second surface of the substrate.
9. A substrate structure with through-silicon vias, characterized in that, include: A substrate having a first surface and a second surface opposite to each other; A plurality of through-silicon vias are disposed in the substrate and perpendicularly penetrate between the first surface and the second surface of the substrate. Each of the plurality of through-silicon vias includes a conductive pad, a through electrode, and a substrate. The conductive pad is adjacent to the first surface of the substrate; The liner is located between the substrate and the through electrode; and A first surface of the through electrode contacts the conductive pad, a second surface of the through electrode is adjacent to the second surface of the substrate, and at least a portion of the through electrode and the corresponding substrate of each of the plurality of silicon through-hole structures protrude from the second surface of the substrate. as well as An insulating polymer layer covers the second surface of the substrate, and exposes each of the plurality of through-silicon via structures and at least a portion of the liner in the insulating polymer layer.
10. The substrate structure with through-silicon vias as claimed in claim 9, further comprising a plurality of bump under-metal layers and corresponding plurality of solder balls disposed on each of the plurality of through-silicon via structures exposed by the insulating polymer layer, or further comprising a redistribution layer disposed on each of the plurality of through-silicon via structures exposed by the insulating polymer layer.