Power failure protection circuit of programmable controller
By designing a power-down protection circuit in the FPGA programmable controller, and using detection and protection circuits to cut off the power supply loop, the problem of data errors caused by voltage instability or power failure is solved, thereby improving system stability and chip lifespan.
Patent Information
- Application Number
- CN202422954469.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-02
- Publication Date
- 2025-10-28
- Estimated Expiration
- 2034-12-02
AI Technical Summary
Existing FPGA programmable controllers lack power-off protection circuits, which can easily lead to data read and write errors in unstable voltage or power outages, and even cause chip operation to crash.
A power-down protection circuit for a programmable controller was designed. Through the cooperation of a power conversion circuit and a protection circuit, a detection circuit detects abnormal voltage and controls a MOSFET to cut off the power supply circuit, preventing data read/write operations from being performed during periods of voltage instability or power failure.
It effectively prevents data read/write errors, improves system stability and reliability, reduces downtime and maintenance costs, and extends chip lifespan.
Smart Images
Figure CN223487844U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of electronic circuit technology, and more specifically, to a power-down protection circuit for a programmable controller. Background Technology
[0002] FPGA (Field Programmable Gate Array) is a further development based on programmable devices such as PAL (Programmable Array Logic) and GAL (General Purpose Array Logic). It emerged as a semi-custom circuit in the field of Application-Specific Integrated Circuits (ASICs), solving the shortcomings of custom circuits and overcoming the limitation of the limited gate count of the original programmable devices.
[0003] Existing FPGA programmable controllers are generally directly powered without power-down protection circuits. As a result, if the operating voltage is unstable or even power is lost during the reading and writing process of the FPGA chip, data reading and writing errors will occur. In severe cases, it will cause a series of adverse reactions, such as inability to read and write normally, abnormal chip program writing, and even operation crash. Therefore, this utility model proposes a power-down protection circuit for programmable controllers to at least partially solve the problems that may exist in the prior art. Utility Model Content
[0004] To overcome or at least partially solve the above problems, this utility model provides a power-down protection circuit for a programmable controller.
[0005] The embodiments of this utility model are implemented as follows:
[0006] This application provides a power-down protection circuit for a programmable controller, including:
[0007] The power conversion circuit has a protection circuit connected between its input and output terminals;
[0008] The output of the power conversion circuit is electrically connected to the programmable control unit.
[0009] The control terminal of the protection circuit is electrically connected to the detection circuit.
[0010] The input terminal of the power conversion circuit and the input terminal of the protection circuit are electrically connected to the power supply terminal;
[0011] The protection circuit includes a first MOSFET, the source and drain of which are electrically connected between the power supply circuit of the power conversion circuit.
[0012] The gate of the first MOS transistor is electrically connected to the collector of the first transistor, the emitter of the first transistor is grounded, and the base of the first transistor is electrically connected to the detection circuit.
[0013] In some embodiments of this utility model, the detection circuit includes:
[0014] The first voltage divider resistor has one end electrically connected to the power supply terminal and the other end electrically connected to one end of the second voltage divider resistor and the emitter of the second transistor.
[0015] The other end of the second voltage divider resistor is grounded, and the base of the second transistor is electrically connected to the power supply terminal through the first current limiting resistor;
[0016] The collector of the second transistor is electrically connected to the base of the third transistor through a second current-limiting resistor. The collector of the third transistor is electrically connected to the base of the first transistor. The emitter of the third transistor is grounded.
[0017] The emitter of the second transistor is also electrically connected to the positive terminal of the electrolytic capacitor, and the negative terminal of the electrolytic capacitor is grounded.
[0018] In some embodiments of this utility model, the power conversion circuit includes:
[0019] The first power chip has its input terminal electrically connected to the power supply terminal and one end of the first inductor, its output terminal electrically connected to the other end of the first inductor and the anode of the first diode, the cathode of the first diode electrically connected to one end of the third voltage divider resistor, and electrically connected to the input terminal of the second power chip through the first MOSFET; one end of the third voltage divider resistor is electrically connected to one end of the fourth voltage divider resistor and the feedback terminal of the first power chip, and the other end of the fourth voltage divider resistor is grounded.
[0020] The output terminal of the second power chip is electrically connected to the programmable control unit through the second inductor.
[0021] In some embodiments of this utility model, the charging pin of the second power chip is also electrically connected to a secondary battery and a filter capacitor.
[0022] The secondary battery is also electrically connected to the current feedback of the second inductor and the second power chip through a third current-limiting resistor;
[0023] The voltage feedback single terminal of the second power chip is electrically connected to one end of the fifth voltage divider resistor, the sixth voltage divider resistor, and the NTC resistor; the other end of the fifth voltage divider resistor is electrically connected to the second inductor, and the other end of the sixth voltage divider resistor and the other end of the NTC resistor are grounded.
[0024] In some embodiments of this utility model, the programmable control unit includes:
[0025] At least one set of power chips, the input of which is electrically connected to the output of the power conversion circuit, and the output of which is electrically connected to the FPGA unit and the regulation circuit;
[0026] The power supply terminal of the power management core unit is electrically connected to the power conversion circuit through the voltage regulation unit; the control terminal of the power management core unit is electrically connected to the control terminal of the regulation circuit and the enable terminal of the power chip.
[0027] In some embodiments of this utility model, the adjustment circuit includes:
[0028] The gate of the second MOSFET is electrically connected to the enable terminal of the power chip, and the source of the second MOSFET is electrically connected to the voltage regulation unit; the drain of the second MOSFET is electrically connected to the gate of the third MOSFET, and the gate of the third MOSFET is also electrically connected to a pull-down resistor.
[0029] The source of the third MOS transistor is grounded, and the drain of the third MOS transistor is electrically connected to the output terminal of the power chip through a fourth current-limiting resistor.
[0030] Compared with the prior art, the embodiments of this utility model have at least the following advantages or beneficial effects:
[0031] A protection circuit is connected between the input and output terminals of the power conversion circuit. The output terminal of the power conversion circuit is electrically connected to the programmable control unit (FPGA). The control terminal of the protection circuit is electrically connected to the detection circuit. The input terminals of the power conversion circuit and the protection circuit are electrically connected to the power supply terminal. The protection circuit includes a first MOSFET, whose source and drain are electrically connected to the power supply circuit of the power conversion circuit. The gate of the first MOSFET is electrically connected to the collector of a first transistor, the emitter of the first transistor is grounded, and the base of the first transistor is electrically connected to the detection circuit. This power-down protection circuit of the FPGA, through the cooperation of the detection circuit and the protection circuit, cuts off the power supply circuit in case of power failure, preventing data read / write errors in the FPGA chip, improving system stability and reliability, reducing downtime and maintenance costs, and extending chip lifespan. Attached Figure Description
[0032] To more clearly illustrate the technical solutions of the embodiments of this utility model, the drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this utility model and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0033] Figure 1This is a schematic diagram of the module structure of a programmable controller provided in one embodiment of the present invention;
[0034] Figure 2 This is a circuit diagram of the power conversion circuit and protection circuit of a programmable controller power-down protection circuit provided in one embodiment of the present invention.
[0035] Figure 3 This is a circuit diagram of the detection circuit of a power-down protection circuit for a programmable controller provided in one embodiment of the present invention.
[0036] Figure 4 This is a circuit diagram of the detection circuit of a power-down protection circuit for a programmable controller provided in one embodiment of the present invention.
[0037] In the diagram: 100, power conversion circuit; 200, protection circuit; 300, programmable control unit; 400, detection circuit. Detailed Implementation
[0038] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, and not all embodiments. The components of the embodiments of this utility model described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.
[0039] Example 1
[0040] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the various embodiments and features described below can be combined with each other.
[0041] Please refer to Figure 1 and Figure 2 As shown, this utility model embodiment provides a power-down protection circuit for a programmable controller, which includes: a power conversion circuit 100, with a protection circuit 200 connected between its input and output terminals; the output terminal of the power conversion circuit 100 is electrically connected to a programmable control unit 300; the control terminal of the protection circuit 200 is electrically connected to a detection circuit 400; the input terminals of the power conversion circuit 100 and the protection circuit 200 are electrically connected to a power supply terminal VCC; the protection circuit 200 includes a first MOSFET Q2, the source and drain of which are electrically connected between the power supply circuit of the power conversion circuit 100; the gate of the first MOSFET Q2 is electrically connected to the collector of a first transistor Q1, the emitter of the first transistor Q1 is grounded, and the base of the first transistor Q1 is electrically connected to the detection circuit 400.
[0042] In this embodiment, when the power supply terminal VCC experiences voltage instability or power failure, the detection circuit 400 can promptly detect the instability or power failure. The detection circuit 400 transmits a signal to the first transistor Q1 in the protection circuit 200, thereby controlling the switching on and off of the first MOSFET Q2. Upon detecting an abnormal voltage condition, the power supply circuit of the power conversion circuit 100 can be quickly cut off, disconnecting the power supply to the programmable control unit 300 and preventing read / write operations on the FPGA chip during periods of voltage instability or power failure, thus preventing data read / write errors. By promptly cutting off the power supply circuit upon detecting a voltage problem, data errors caused by voltage instability or power failure during FPGA chip read / write operations are effectively avoided. This ensures data integrity and accuracy, guaranteeing the correctness of operations whether reading stored data or writing new programs or configurations, reducing a series of problems caused by data errors, such as abnormal chip program writing or operational crashes; the overall stability of the programmable controller is significantly improved. In complex working environments, even in the event of power outages, this power-down protection circuit ensures the integrity of the system's core—the Programmable Control Unit 300—remains undamaged, reducing the risk of system failure, improving equipment reliability and availability, and minimizing downtime and maintenance costs. By preventing damage to the FPGA chip caused by power outages and voltage instability, the chip's lifespan is extended. Operating under a normal and stable voltage environment reduces the electrical stress caused by abnormal voltages that could damage the chip's internal circuitry, lowering the likelihood of premature aging or failure and thus saving on equipment replacement costs.
[0043] It should be noted that since the power conversion circuit 100 is isolated by the first MOSFET Q2 in the protection circuit 200, by controlling the on and off of the first MOSFET Q2, it can directly control the on and off of the power supply, and can also protect other circuits from failure caused by unstable VCC voltage or power failure at the power supply terminal.
[0044] Example 2
[0045] This utility model embodiment provides a power-down protection circuit for a programmable controller, referring to... Figure 3As shown, the detection circuit 400 includes: a first voltage divider resistor R8, one end of which is electrically connected to the power supply terminal VCC, and the other end of which is electrically connected to one end of a second voltage divider resistor R9 and the emitter of a second transistor Q3; the other end of the second voltage divider resistor R9 is grounded to GND; the base of the second transistor Q3 is electrically connected to the power supply terminal VCC through a first current-limiting resistor R10; the collector of the second transistor Q3 is electrically connected to the base of a third transistor Q4 through a second current-limiting resistor R11; the collector of the third transistor Q4 is electrically connected to the base of a first transistor Q1; the emitter of the third transistor Q4 is grounded to GND; the emitter of the second transistor Q3 is also electrically connected to the positive terminal of an electrolytic capacitor C6; the negative terminal of the electrolytic capacitor C6 is grounded.
[0046] As an example, in the detection circuit 400 described above, the first voltage divider resistor R8 and the second voltage divider resistor R9 are preferably 2.2kΩ and 33kΩ, respectively. The collector of the third transistor Q4 is also electrically connected to one end of the second voltage divider resistor R9 through the diode D4. The diode D4 is preferably a silicon transistor. The second transistor Q3 is preferably a PNP transistor. The first current-limiting resistor R10 is preferably 33kΩ. The electrolytic capacitor C6 is preferably 100μF. The second current-limiting resistor R11 is preferably 4.7kΩ. The third transistor Q4 is preferably an NPN transistor. For example, taking VCC voltage as 12V, (1) when VCC is powered on, capacitor C6 is charged through resistor R8 and diode D4. After VCC stabilizes at 12V, after the voltage division of R8 and R9, the left side of D4 is 11.25V. After passing through D4, the voltage drop across the diode is reduced by 0.7V, and the voltage across capacitor C6 is finally charged to 10.55V.
[0047] (2) After VCC stabilizes at 12V, the base of Q3 is directly connected to VCC through the first current-limiting resistor R10, and is also at 12V. Since the base voltage is higher than the emitter voltage, transistor Q3 does not conduct. If Q3 does not conduct, there is no voltage at the base of Q4, and Q2 also does not conduct.
[0048] (3) When VCC power drops, it needs to drop to a certain threshold before Q4 will turn on and output a VCC power-off signal. Specifically, when VCC power drops to a certain threshold (such as below 10.55V), capacitor C6 supplies power to the emitter of the second transistor Q3, making the base voltage of the second transistor Q3 lower than the emitter voltage, thus turning it on. After the second transistor Q3 turns on, the base voltage of the third transistor Q4 increases, turning on the collector and emitter of the third transistor Q4.
[0049] In addition, in the discharge circuit, for example when VCC drops to 9.85V, the voltage of capacitor C6 is 10.55V when fully charged, which is 0.7V higher than the base of Q3 (9.85V). C6 discharges through the base of Q3, resistor R10, and VCC circuit, so Q3 is turned on.
[0050] After Q1 is turned on, the voltage of capacitor C6 flows through the collector-exceeding terminal of Q3, resistor R11, and the base-below terminal of Q4 to ground GND. At this time, the base-below voltage of Q4 is 0.7V, so Q4 is turned on. After Q4 is turned on, it pulls the external circuit voltage to ground GND, that is, the collector of Q4 is grounded to GND, thus informing the external circuit that the VCC power supply terminal has lost power or that there is an unstable power supply, thereby controlling the power conversion circuit 100 to disconnect the power supply.
[0051] In a preferred embodiment, the power conversion circuit 100 includes: a first power chip U1, whose input terminal is electrically connected to the power supply terminal VCC and one end of the first inductor L1, whose output terminal LX is electrically connected to the other end of the first inductor L1 and the anode of the first diode D3, whose cathode of the first diode D3 is electrically connected to one end of the third voltage divider resistor R5, and is electrically connected to the input terminal of the second power chip U2 through the first MOSFET Q2; one end of the third voltage divider resistor R5 is electrically connected to one end of the fourth voltage divider resistor R6 and the feedback terminal FB of the first power chip U1, and the other end of the fourth voltage divider resistor R6 is grounded to GND; the output terminal SW of the second power chip U2 is electrically connected to the programmable control unit 300 through the second inductor L2.
[0052] The first power supply chip U1 is preferably a PW5300A chip, the first inductor is preferably 4.7-22μH, and the third and fourth voltage divider resistors R5 and R6 are preferably 82kΩ and 12kΩ, respectively. The PW5300A has a switching frequency of 1.2MHz, allowing the use of miniature, low-cost capacitors and inductors with a height of 2mm or less. Internal soft-start results in low inrush current and extended battery life. The PW5300A automatically switches to pulse frequency modulation mode under light loads. The PW5300A includes undervoltage lockout, current limiting, and thermal overload protection to prevent damage during output overload.
[0053] Furthermore, the charging pin BAT of the second power chip U2 is also electrically connected to the secondary battery BAT and the filter capacitor C2; the secondary battery BAT is also electrically connected to the second inductor L2 and the current feedback SEN of the second power chip U2 through the third current limiting resistor R15; the voltage feedback pin of the second power chip U2 is electrically connected to one end of the fifth voltage divider resistor R1, the sixth voltage divider resistor R2 and the NTC resistor; the other end of the fifth voltage divider resistor R1 is electrically connected to the location of the second inductor L2 used to provide VDD power supply, and the other end of the sixth voltage divider resistor R2 and the other end of the NTC resistor are grounded to GND.
[0054] As an example, the aforementioned second power chip U2 can preferably be the HE3342 chip, employing a 1.5MHz fixed-frequency synchronous buck converter, thus achieving a charging efficiency of over 90% with minimal heat generation. It integrates multiple functions such as reverse current protection, output short-circuit protection, and chip and battery temperature protection. This chip eliminates the need for a reverse current protection diode and external power MOSFETs or freewheeling diodes, utilizing its internal power transistors for trickle, constant current, and constant voltage charging of the battery. The charging current can be programmed using an external resistor, with a maximum continuous charging current of up to 2A, eliminating the need for an additional reverse current protection diode. It boasts a charging efficiency of over 90% and minimal heat generation. Figure 2 As shown, the HE3342E includes two open-drain output status indicators: CHRG (charging status) and STDBY (full charge status). The chip's internal power management circuit automatically reduces the charging current when the chip junction temperature exceeds 145°C. This function allows users to maximize the chip's processing power without worrying about overheating and damage to the chip or external components. When the input voltage exceeds the low-voltage detection threshold, the HE3342E begins charging the battery, and the CHRG pin outputs a low level, indicating that charging is in progress. When the charging cycle ends, the CHRG pin outputs a high-impedance state, and the STDBY pin outputs a low level. The charging end threshold is 10% of the constant-current charging current. When the battery voltage drops below the recharge threshold, the HE3342E automatically starts a new charging cycle. The chip's internal high-precision voltage reference, error amplifier, and resistor divider network ensure that the accuracy of the battery-side modulated voltage is within 1%, meeting the precise charging requirements of lithium-ion and lithium-polymer batteries. When the input voltage drops or falls below the battery voltage, the charger enters a low-power sleep mode, where the battery consumes less than 3uA of current, thus increasing standby time.
[0055] It should be noted that the aforementioned secondary battery, preferably a lithium battery, can be used to power the subsequent programmable controller, preventing the FPGA from completely losing power and failing to work properly when the VCC voltage is unstable. Moreover, the current waveform of the battery power supply is almost linear, which can maintain a stable power supply even after the VCC power is lost.
[0056] Example 3
[0057] This utility model embodiment provides a power-down protection circuit for a programmable controller, referring to... Figure 4 As shown, the programmable control unit 300 includes: at least one set of power chips U4, whose input terminal is electrically connected to the output terminal of the power conversion circuit 100, and whose output terminal is electrically connected to the FPGA unit U6 and the regulation circuit; the power supply terminal of the power management core unit U5 is electrically connected to the power conversion circuit 100 through the voltage regulation unit U3; the control terminal of the power management core unit U5 is electrically connected to the control terminal of the regulation circuit and the enable terminal EN of the power chip U4, and one set of the power chips can supply power to one FPGA unit U6; the voltage regulation unit U3 is preferably a three-terminal regulator, for example, a 7805 three-terminal regulator.
[0058] In a preferred embodiment, the regulation circuit includes: the gate of the second MOSFET Q5 is electrically connected to the enable terminal EN of the power chip U4; the source of the second MOSFET Q5 is electrically connected to the voltage regulation unit U3; the drain of the second MOSFET Q5 is electrically connected to the gate of the third MOSFET Q6, and the gate of the third MOSFET Q6 is also electrically connected to a pull-down resistor R13; the source of the third MOSFET Q6 is grounded to GND; and the drain of the third MOSFET Q6 is electrically connected to the output terminal of the power chip U4 through a fourth current-limiting resistor R12. Through the aforementioned power management core unit U5, multiple power chips U4 can be managed. When power is needed for the FPGA, the aforementioned power management core unit U5 sends an EN (enable) signal to the corresponding power chip U4, thereby controlling the operation of the power chip U4.
[0059] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. Although optional embodiments of this utility model have been described, those skilled in the art, once they understand the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including optional embodiments as well as all changes and modifications falling within the scope of this utility model.
[0060] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used merely to distinguish one entity from another, and do not necessarily require or imply any such actual relationship or order between these entities. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that an article or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such an article or terminal device. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or terminal device that includes that element.
[0061] The technical solution provided by this utility model has been described in detail above. Specific examples have been used to illustrate the principle and implementation of this utility model. At the same time, for those skilled in the art, there will be changes in the specific implementation and application scope based on the principle and implementation of this utility model. Therefore, the content of this specification should not be construed as a limitation of this utility model.
Claims
1. A power-down protection circuit for a programmable controller, characterized in that, include: The power conversion circuit has a protection circuit connected between its input and output terminals; The output of the power conversion circuit is electrically connected to the programmable control unit. The control terminal of the protection circuit is electrically connected to the detection circuit. The input terminal of the power conversion circuit and the input terminal of the protection circuit are electrically connected to the power supply terminal; The protection circuit includes a first MOSFET, the source and drain of which are electrically connected between the power supply circuit of the power conversion circuit. The gate of the first MOS transistor is electrically connected to the collector of the first transistor, the emitter of the first transistor is grounded, and the base of the first transistor is electrically connected to the detection circuit.
2. The power-off protection circuit according to claim 1, characterized in that, The detection circuit includes: The first voltage divider resistor has one end electrically connected to the power supply terminal and the other end electrically connected to one end of the second voltage divider resistor and the emitter of the second transistor. The other end of the second voltage divider resistor is grounded, and the base of the second transistor is electrically connected to the power supply terminal through the first current limiting resistor; The collector of the second transistor is electrically connected to the base of the third transistor through a second current-limiting resistor. The collector of the third transistor is electrically connected to the base of the first transistor. The emitter of the third transistor is grounded. The emitter of the second transistor is also electrically connected to the positive terminal of the electrolytic capacitor, and the negative terminal of the electrolytic capacitor is grounded.
3. The power-off protection circuit according to claim 1 or 2, characterized in that, The power conversion circuit includes: The first power chip has its input terminal electrically connected to the power supply terminal and one end of the first inductor, its output terminal electrically connected to the other end of the first inductor and the anode of the first diode, the cathode of the first diode electrically connected to one end of the third voltage divider resistor, and electrically connected to the input terminal of the second power chip through the first MOSFET; one end of the third voltage divider resistor is electrically connected to one end of the fourth voltage divider resistor and the feedback terminal of the first power chip, and the other end of the fourth voltage divider resistor is grounded. The output terminal of the second power chip is electrically connected to the programmable control unit through the second inductor.
4. The power-off protection circuit according to claim 3, characterized in that, The charging pin of the second power chip is also electrically connected to a secondary battery and a filter capacitor. The secondary battery is also electrically connected to the current feedback of the second inductor and the second power chip through a third current-limiting resistor; The voltage feedback single terminal of the second power chip is electrically connected to one end of the fifth voltage divider resistor, the sixth voltage divider resistor, and the NTC resistor; the other end of the fifth voltage divider resistor is electrically connected to the second inductor, and the other end of the sixth voltage divider resistor and the other end of the NTC resistor are grounded.
5. The power-off protection circuit according to claim 1, characterized in that, The programmable control unit includes: At least one set of power chips, the input of which is electrically connected to the output of the power conversion circuit, and the output of which is electrically connected to the FPGA unit and the regulation circuit; The power supply terminal of the power management core unit is electrically connected to the power conversion circuit through the voltage regulation unit; the control terminal of the power management core unit is electrically connected to the control terminal of the regulation circuit and the enable terminal of the power chip.
6. The power-off protection circuit according to claim 5, characterized in that, The regulating circuit includes: The gate of the second MOSFET is electrically connected to the enable terminal of the power chip, and the source of the second MOSFET is electrically connected to the voltage regulation unit; the drain of the second MOSFET is electrically connected to the gate of the third MOSFET, and the gate of the third MOSFET is also electrically connected to a pull-down resistor. The source of the third MOS transistor is grounded, and the drain of the third MOS transistor is electrically connected to the output terminal of the power chip through a fourth current-limiting resistor.