High-integration-level gallium arsenide S-waveband receiving multifunctional chip

Abstract

The utility model provides a high-integration-level gallium arsenide S-waveband receiving multifunctional chip. The high-integration-level gallium arsenide S-waveband receiving multifunctional chip comprises a low-noise amplification circuit, a numerical control attenuation circuit, a numerical control phase shift circuit, a gain adjustment circuit, a driving amplification circuit and a switching circuit which are connected in sequence, the chip is divided into a first area, a second area and a third area along the length direction; the low-noise amplification circuit and the numerical control attenuation circuit are arranged in the first area along the width direction of the chip, and the low-noise amplification circuit is connected with the input end of the chip; the numerical control phase shift circuit is independently arranged in the second area; the gain adjusting circuit, the driving amplifying circuit and the switching circuit are arranged in a third area in the width direction of the chip, and the third area is provided with a chip output end connected with the switching circuit. According to the scheme, the size of the circuit is greatly reduced, the assembly difficulty is reduced, the reliability of the circuit is improved, and the requirements of miniaturization, light weight, integration and low cost of the radio frequency microwave assembly are met.

Description

Technical Field

[0001] This utility model belongs to the field of microwave integrated circuit technology, and in particular relates to a highly integrated gallium arsenide S-band receiver multifunctional chip. Background Technology

[0002] Radio frequency (RF) receiving circuits typically include RF devices such as limiters, amplifiers, digitally controlled attenuators, digitally controlled phase shifters, and switches, which can perform functions such as amplification, digitally controlled phase shifting, digitally controlled attenuation, and switching of the received signal.

[0003] To achieve these functions, existing technologies employ discrete chips with different functions, such as low-noise amplifier chips, digitally controlled attenuator chips, and digitally controlled phase shifter chips, etc., which are connected on a circuit board via cascading transmission lines to form an RF receiving circuit. This type of RF receiving circuit has low integration, a large overall circuit size, and requires extensive matching work in its design. Furthermore, the need to assemble multiple independent chips individually increases the assembly workload and difficulty, leading to low assembly efficiency. On the other hand, the increased number of chip connection points reduces circuit reliability. Utility Model Content

[0004] To address the shortcomings of existing technologies, this invention provides a highly integrated gallium arsenide S-band receiver multifunctional chip, which greatly reduces the size of the circuit, lowers the assembly difficulty, and improves the reliability of the circuit, thus benefiting the needs for miniaturization, lightweighting, integration, and cost reduction of RF microwave components.

[0005] In order to achieve the purpose of this utility model, the following solution is proposed:

[0006] A highly integrated gallium arsenide S-band receiver multifunctional chip includes: a low-noise amplifier circuit, a digitally controlled attenuation circuit, a digitally controlled phase shift circuit, a gain adjustment circuit, a drive amplifier circuit, and a switching circuit connected in sequence.

[0007] The chip is divided into a first region, a second region, and a third region along its length.

[0008] The low-noise amplifier circuit and the digitally controlled attenuation circuit are arranged in the first region along the width direction of the chip, and the low-noise amplifier circuit is connected to the input terminal of the chip.

[0009] The numerically controlled phase-shifting circuit is separately located in the second area;

[0010] The gain adjustment circuit, drive amplifier circuit, and switching circuit are located in the third region along the width of the chip. The third region has a chip output terminal connected to the switching circuit.

[0011] The beneficial effects of this utility model are as follows: This solution integrates the radio frequency circuit that originally required a circuit board and multiple chips into a single multi-functional chip, which greatly reduces the size of the circuit, effectively reduces the number of chips installed, greatly improves assembly efficiency, greatly reduces the workload and difficulty of debugging, and thereby improves the reliability of the circuit. Furthermore, this solution is also beneficial to the needs of miniaturization, lightweighting, integration and low cost of radio frequency microwave components. Attached Figure Description

[0012] The drawings described herein are for illustrative purposes only of selected embodiments and not all possible implementations, and are not intended to limit the scope of the present invention.

[0013] Figure 1 The diagram shows the distribution of various functional circuits on the multifunctional chip of this application.

[0014] Figure 2 A circuit connection diagram of the multifunctional chip of this application is shown.

[0015] Figure 3 A schematic diagram of the pad pressure point distribution of the multifunctional chip of this application is shown.

[0016] The markings in the diagram are: chip input terminal-1, low noise amplifier circuit-2, digitally controlled attenuation circuit-3, digitally controlled phase shift circuit-4, gain adjustment circuit-5, drive amplifier circuit-6, switching circuit-7, and chip output terminal-8. Detailed Implementation

[0017] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the implementation methods of the present invention are described in detail below with reference to the accompanying drawings. However, the embodiments described in the present invention are only part of the embodiments of the present invention, rather than all the embodiments.

[0018] like Figure 1 As shown, a highly integrated gallium arsenide S-band receiver multifunctional chip includes: a low-noise amplifier circuit 2, a digitally controlled attenuation circuit 3, a digitally controlled phase shift circuit 4, a gain adjustment circuit 5, a drive amplifier circuit 6, and a switching circuit 7, connected in sequence. Gallium arsenide refers to the substrate used in the chip.

[0019] Specifically, the switching circuit 7 adopts an absorption-type single-pole double-throw structure, the digitally controlled attenuation circuit 3 is a 7-digit digitally controlled attenuation circuit, and the digitally controlled phase shifting circuit 4 is a 6-digit digitally controlled phase shifting circuit.

[0020] like Figure 1 As shown, the chip is divided into a first region, a second region, and a third region along its length.

[0021] Specifically, the low-noise amplifier circuit 2 and the digitally controlled attenuation circuit 3 are arranged along the width of the chip in the first region, and the low-noise amplifier circuit 2 is connected to the chip input terminal 1. Specifically, the chip input terminal 1 is located in the first region a. In practice, since the chip input terminal 1 is usually a solder joint or pad, after arranging the low-noise amplifier circuit 2 and the digitally controlled attenuation circuit 3, the chip input terminal 1 can be placed near the low-noise amplifier circuit 2 based on the remaining space in the first region. The reason for connecting the low-noise amplifier circuit 2 to the chip input terminal 1, and placing the low-noise amplifier circuit 2 at the front of the entire circuit, is that the coefficient of the low-noise amplifier circuit 2 needs to meet the requirement of ≤0.6dB. On the other hand, because the dimensions of the low-noise amplifier circuit 2 and the digitally controlled attenuation circuit 3 are relatively small, and the sum of their dimensions in the circuit transmission direction is comparable to the width of the chip, the digitally controlled attenuation circuit 3 and the low-noise amplifier circuit 2 are jointly arranged in the first region along the width of the chip.

[0022] Specifically, because the size of the numerically controlled phase-shifting circuit 4 is relatively large, and its size along the circuit transmission direction is close to the width of the chip, the numerically controlled phase-shifting circuit 4 is set separately in the second region.

[0023] Specifically, because the gain adjustment circuit 5, the drive amplifier circuit 6, and the switching circuit 7 are relatively small, they are all located in the third region along the width of the chip. The third region has a chip output terminal 8 connected to the switching circuit 7. The gain adjustment circuit has three pads. Changing the bonding method between the pads will generate different attenuation levels to adjust the chip gain, facilitating circuit debugging after chip assembly. Preferably, the gain adjustment circuit is designed with three attenuation levels: 0.5dB, 1dB, and 1.5dB. Due to the turn-off isolation requirements, the switching circuit 7 needs to be placed at the end of the circuit. If the switching circuit 7 is placed before the drive amplifier circuit 6, it cannot effectively block interference or self-oscillation signals when the drive amplifier circuit 6 is interfered with. Therefore, placing the switching circuit 7 at the end of the entire circuit ensures circuit stability to a certain extent.

[0024] In the above scheme, the numerically controlled phase shift circuit 4 and the numerically controlled attenuation circuit 3 have large losses. Therefore, arranging the numerically controlled phase shift circuit 4 and the numerically controlled attenuation circuit 3 between the low-noise amplifier circuit 2 and the drive amplifier circuit 6 can not only improve the situation of excessive gain concentration, but also reduce the amplification capability requirements of the drive amplifier circuit 6.

[0025] Because this solution integrates multiple circuits onto a small chip, the electromagnetic interference between the functional circuits becomes very severe due to the reduced distance. This solution reduces the electromagnetic interference between the functional circuits through the above structural layout, minimizing the chip area. The functional circuits here refer to the low-noise amplifier circuit 2, the digitally controlled attenuation circuit 3, the digitally controlled phase shift circuit 4, the gain adjustment circuit 5, the drive amplifier circuit 6, and the switching circuit 7. In actual implementation, EM simulation is used to minimize the electromagnetic interference between the functional circuits.

[0026] The chip works as follows: a signal enters from input terminal 1 of the chip, such as... Figure 2 As shown, the signal sequentially passes through the low-noise amplifier circuit 2 to amplify the input signal while ensuring minimal degradation of the RF signal noise figure before and after amplification; the digitally controlled attenuation circuit 3 implements digitally controlled attenuation, with a 7-bit control code, attenuating the RF signal in 0.25dB steps; the digitally controlled phase shift circuit 4 implements digitally controlled phase shift, with a 6-bit control code, adjusting the phase of the RF signal in 5.625° steps; the gain adjustment circuit 5 implements the link gain adjustment function, compensating for gain deviations in the low-noise amplifier circuit 2, the drive amplifier circuit 6, and other parts of the circuit within a small range; the drive amplifier circuit 6 further amplifies the RF signal; finally, the switching circuit 7 controls the entire circuit to turn on or off. When the circuit is off, it switches to the load port to absorb the RF signal and then outputs it from the chip output terminal 8.

[0027] This solution integrates the radio frequency circuit, which originally required a circuit board and multiple chips, into a single multi-functional chip, greatly reducing the size of the circuit and the number of chips required. This significantly improves assembly efficiency, reduces debugging workload and difficulty, and enhances circuit reliability. Furthermore, this solution is beneficial to meeting the needs for miniaturization, lightweighting, integration, and cost reduction of radio frequency microwave components.

[0028] During chip manufacturing, the traditional GaAs low-noise amplifier process and the switching device process for amplitude and phase chips differ due to varying performance requirements. Therefore, the ED process was chosen to integrate the specific process requirements of these two types of devices. On one hand, GaAs E-mode devices have a large Gm (transconductance) and extremely low Fmin, facilitating the design of low-noise amplifiers, which can also be understood as low-noise amplifier circuit 2. On the other hand, GaAs D-mode devices are the core of the switching circuit 7 and the drive amplifier circuit 6. Meanwhile, the digitally controlled attenuation circuit 3 and the digitally controlled phase shifting circuit 4, which adjust the amplitude and phase of the circuit, are both based on GaAs D-mode technology. Therefore, considering the characteristics of the processing technology required for different chips, the GaAs ED process was chosen as a compromise, enabling the integration of functional circuits such as low-noise amplifier circuit 2, switching circuit 7, digitally controlled attenuation circuit 3, digitally controlled phase shifting circuit 4, and drive amplifier circuit 6 onto a single chip.

[0029] The detailed technical specifications achievable by the multi-functional chip using the above solution are shown in the table below:

[0030]

[0031] Preferably, the length and width of the chip are 3mm to 4mm. In actual manufacturing, the length and width can be the same or different. As a conventional choice, the chip size can be set to the following specifications: 3.0mm×3.0mm, 3.5mm×3.55mm, 3.66mm×3.56mm, 3.7mm×3.8mm or 4.0mm×4.0mm.

[0032] Preferably, a low-frequency control line and a ground circuit are provided between the first region, the second region and the third region to isolate the first region, the second region and the third region, so as to increase the isolation between the front and rear stages of the radio frequency circuit and further reduce the electromagnetic interference between the functional links.

[0033] Preferably, the highly integrated gallium arsenide S-band receiver multifunctional chip also includes a control circuit, which is connected to the numerically controlled attenuation circuit 3, the numerically controlled phase shift circuit 4, the gain adjustment circuit 5, the drive amplifier circuit 6, and the switching circuit 7 respectively. By integrating the control circuit inside the chip, the external power supply control chip is eliminated, and the power-on and power-off functions can be directly realized using TTL signals.

[0034] Preferred, such as Figure 3 As shown, the chip's pads are distributed on both sides of the width direction to accommodate the circuit transmission direction of each functional circuit.

[0035] The above description is merely a preferred embodiment of this utility model and does not imply its uniqueness or limitation. Those skilled in the art should understand that various changes or equivalent substitutions made to this utility model without departing from its scope are all within the protection scope of this utility model.

Claims

1. A highly integrated gallium arsenide S-band receiver multifunctional chip, characterized in that, include: The low-noise amplifier circuit (2), the digitally controlled attenuation circuit (3), the digitally controlled phase shifting circuit (4), the gain adjustment circuit (5), the drive amplifier circuit (6), and the switching circuit (7) are connected in sequence. The chip is divided into a first region, a second region, and a third region along its length. The low-noise amplifier circuit (2) and the digitally controlled attenuation circuit (3) are arranged in the first region along the width direction of the chip, and the low-noise amplifier circuit (2) is connected to the chip input terminal (1). The numerically controlled phase-shifting circuit (4) is separately located in the second area; The gain adjustment circuit (5), the drive amplifier circuit (6) and the switch circuit (7) are located in the third region along the width direction of the chip. The third region is provided with a chip output terminal (8) connected to the switch circuit (7).

2. The highly integrated gallium arsenide S-band receiver multifunctional chip according to claim 1, characterized in that, The chip's length and width dimensions are 3mm to 4mm.

3. The highly integrated gallium arsenide S-band receiver multifunctional chip according to claim 1, characterized in that, A low-frequency control line and a ground circuit are provided between the first, second, and third regions to isolate them.

4. The highly integrated gallium arsenide S-band receiver multifunctional chip according to claim 1, characterized in that, It also includes a control circuit, which is connected to the numerically controlled attenuation circuit (3), the numerically controlled phase shifting circuit (4), the gain adjustment circuit (5), the drive amplifier circuit (6), and the switching circuit (7), respectively.

5. The highly integrated gallium arsenide S-band receiver multifunctional chip according to claim 1, characterized in that, The chip's pads are distributed on both sides of the width direction.

6. The highly integrated gallium arsenide S-band receiver multifunctional chip according to claim 1, characterized in that, The numerically controlled attenuation circuit (3) is a 7-digit numerically controlled attenuation circuit, and the numerically controlled phase shifting circuit (4) is a 6-digit numerically controlled phase shifting circuit.

7. The highly integrated gallium arsenide S-band receiver multifunctional chip according to claim 1, characterized in that, The gain adjustment circuit (5) can produce different attenuation by bonding different pads.

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