Semiconductor system and semiconductor device

Abstract

The utility model discloses a semiconductor system and a semiconductor device. The semiconductor device comprises a spiral inductor. In one embodiment, the semiconductor device includes a pattern ground shield (PGS) electrically coupled to the spiral inductor. The semiconductor device includes a filter configured to exchange energy with the pattern ground shield. In one embodiment, a semiconductor device includes a circuit vertically spaced from an inductor with a graphic ground shield disposed between the circuit and the spiral inductor.

Description

Technical Field

[0001] This utility model relates to a system, an apparatus and a method for manufacturing the same, and more particularly to a semiconductor system, a semiconductor apparatus and a method for manufacturing the same. Background Technology

[0002] The semiconductor industry has experienced rapid growth due to the increasing integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.). In most cases, this increase in integration density stems from the continuous reduction in the minimum feature size, allowing more components to be integrated into a given area. However, as devices continue to become more densely packed, various features of semiconductor devices can interact. For example, high-frequency signals can couple between different components of a semiconductor device, potentially interfering with the operation of one or more circuits. Therefore, some areas of a semiconductor device may include keep-out areas, parts of the device that are restricted in operation, or parts not used for active circuitry or their interconnections. This necessitates improvements to existing technologies. Utility Model Content

[0003] The purpose of this invention is to provide a semiconductor system and semiconductor device to solve at least one of the above-mentioned problems.

[0004] Some embodiments of this utility model provide a semiconductor device, including: a spiral inductor; a patterned ground shield (PGS) electrically coupled to the spiral inductor; a filter electrically coupled to the patterned ground shield; and a circuit perpendicularly spaced from the spiral inductor, wherein the patterned ground shield is disposed between the circuit and the spiral inductor.

[0005] According to one embodiment of the present invention, the spiral inductor includes a copper redistribution layer.

[0006] According to one embodiment of the present invention, at least a portion of the circuit is disposed in a layer, which is perpendicularly adjacent to the grounded shield of the pattern.

[0007] According to one embodiment of the present invention, the spiral inductor has a first terminal and a second terminal. The first terminal extends above the patterned ground shield along a layer identical to a coil of the spiral inductor, and the second terminal extends above the patterned ground shield along a layer disposed between the spiral inductor and the patterned ground shield.

[0008] According to one embodiment of the present invention, at least a portion of the circuit is disposed below a central region of the spiral inductor.

[0009] According to one embodiment of the present invention, at least a portion of the circuit is disposed below one winding of the spiral inductor.

[0010] Other embodiments of this utility model provide a semiconductor system including: a first inductor configured to operate at a frequency; a second inductor; and a capacitor including: a first conductive element with a patterned ground shield electrically coupled to the first inductor; a second conductive element with a patterned ground shield; and a dielectric disposed between the first conductive element and the second conductive element, wherein the capacitor and the second inductor form an LC cavity configured to resonate at the frequency.

[0011] According to one embodiment of the present invention, it further includes: a circuit vertically separated from the first inductor, wherein the pattern grounding shield is disposed between the circuit and the first inductor.

[0012] According to one embodiment of the present invention, a coil of the first inductor is disposed on a first layer of a semiconductor device; a coil of the second inductor is disposed on a second layer of the semiconductor device; and at least a portion of the patterned grounding shield is disposed on a third layer of the semiconductor device.

[0013] According to one embodiment of the present invention, the first layer of the semiconductor device is a redistribution layer, and the second layer of the semiconductor device is not a redistribution layer. Attached Figure Description

[0014] The various aspects of this utility model will be described in detail below with reference to the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale and are only used for illustrative purposes. In fact, the dimensions of the elements may be arbitrarily enlarged or reduced to clearly demonstrate the features of this utility model.

[0015] According to some embodiments of this utility model Figure 1 This is a view of a hybrid stack-up of semiconductor devices.

[0016] According to some embodiments of this utility model Figure 2 The accompanying diagram illustrates the application of filters to the isolation of a patterned grounds shield (PGS).

[0017] According to some embodiments of this utility model Figure 3 This is a cross-sectional view of a semiconductor device.

[0018] According to some embodiments of this utility model Figure 4 For spiral inductors with filters (e.g., Figure 1The exclusion region diagram of the spiral inductor.

[0019] According to some embodiments of this utility model Figure 5 This is a top view of a semiconductor device containing a multi-tap coil.

[0020] According to some embodiments of this utility model Figure 6 A top view of a semiconductor device containing various circuits.

[0021] According to some embodiments of this utility model Figure 7 A method for forming a semiconductor device.

[0022] The attached figures are labeled as follows:

[0023] 100: Device

[0024] 102: Inductor

[0025] 104:Terminal

[0026] 106:Terminal

[0027] 108: Coil

[0028] 110: Guide hole structure

[0029] 112: Graphical grounding shield / PGS

[0030] 114: Conductive elements

[0031] 116: Conductive interconnection

[0032] 118: Filter

[0033] 120: Resistor

[0034] 122: Inductor

[0035] 200: Attached Figure

[0036] 202: Axis

[0037] 204: Shaft

[0038] 206: Isolation Line

[0039] 208: Critical Line

[0040] 210: Isolation Line

[0041] 212: Center Frequency

[0042] 214: Intersection

[0043] 216: Isolation Line

[0044] 218: Center Frequency

[0045] 220: Intersection

[0046] 302: Redistribution Layer / RDL

[0047] 304: Metallization layer

[0048] 306: Metallization layer

[0049] 308: Metallization layer

[0050] 310: Area

[0051] 312: Area

[0052] 314: Surface

[0053] 316: Trap

[0054] 318: Trap

[0055] 400: Area Map

[0056] 402: Area

[0057] 502: Winding

[0058] 504:Terminal

[0059] 506:Terminal

[0060] 600: Top View

[0061] 602: Circuit

[0062] 604: Circuit

[0063] 606: Circuit

[0064] 608: Circuit

[0065] 610: Circuit

[0066] 700: Method

[0067] 702: Operation

[0068] 704: Operation

[0069] 706: Operation

[0070] 708: Operation Detailed Implementation

[0071] The following provides many different embodiments or examples to achieve different features of the present invention. Specific examples of components and configurations are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, the following description mentions forming a first component on or above a second component, which may include embodiments where the first and second components are formed in direct contact, and may also include embodiments where an additional component is formed between the first and second components, such that the first and second components do not need to be in direct contact. Furthermore, the present invention may repeat element symbols and / or letters in many examples. These repetitions are for simplification and clarity and do not in themselves represent a specific relationship between the various embodiments and / or configurations discussed.

[0072] Furthermore, spatially relative terms such as "below," "under," "lower," "above," and "higher" may be used here to facilitate the description of the relationship between one or more components or features in the accompanying drawings and another component or feature(s). Spatially relative terms are used to include different orientations of the device in use or operation, as well as the orientations described in the accompanying drawings. When the device is turned to different orientations (rotated 90 degrees or other orientations), the spatially relative adjectives used will also be interpreted according to the orientation after the turn.

[0073] "Or" can be interpreted as inclusive, such that any word described using "or" can mean one, multiple, or all of the stated words. At least one in the list of combinations of words can be interpreted as inclusive or to mean one, multiple, or all of the stated words. For example, "at least one of A and B" can include only "A", only "B", or both "A" and "B". Such words used in conjunction with "include" or other open-ended words can include additional items.

[0074] Generally, a graphical ground shield (PGS) can shield various circuit components from electromagnetically active components (e.g., a spiral inductor). The operation of a PGS can vary depending on its configuration. For example, providing additional vias or otherwise improving the grounding path can improve the isolation achieved between the spiral inductor and other circuit elements. In some cases, the isolation achieved using a PGS may be less than the isolation criticality for the relevant frequency or its range. For example, a PGS may not be connected to a filter configured to attenuate energy corresponding to the relevant frequency. A filter can be coupled to the PGS to improve operation with respect to such frequencies or frequency ranges (e.g., increase isolation). For example, the filter may include a series resistor-inductor (RL) filter. The combination of an RL filter with various transmission line effects or parasitic capacitances of the PGS can create an inductive-capacitive (LC) cavity, which can reduce coupling effects with other components of the semiconductor device. That is, the LC cavity can alternatively store and release energy between the inductor and the various elements contributing capacitance to it, which can reduce energy coupling to other circuitry. The selection of filter components can vary depending on the center frequency (e.g., resonant center) of the LC cavity. This selection or geometry of the filter elements can improve isolation at one or more desired frequencies.

[0075] According to some embodiments, Figure 1 This is a hybrid stacked view of the semiconductor device 100. The hybrid stacked view includes a depiction of the layout of various conductive elements forming the spiral inductor 102 and its shielding element, and a schematic diagram of a filter 118 connected to the shielding element. The spiral inductor 102 may refer to an assembly formed by conductive elements disposed on one or more layers of the semiconductor device 100. In detail, the spiral inductor 102 includes a first terminal 104 extending to a coil 108, which in turn extends to a second terminal 106. As shown, a portion of at least one of the terminals 104, 106 may include a vertical extension (depicted as extending into the page) such that the terminal 106 can pass above or below a portion of the coil 108 to connect to a signal, such as a power signal (e.g., may include a via structure 110). The spiral of the spiral inductor 102 may include various shapes, such as concentric circles, octagons, or other regular polygons. For example, the depicted square spiral inductor 102 includes a square coil 108 with chamfered corners, which can improve the quality factor of the inductance or contribute to manufacturability (e.g., reducing over-etching and stress accumulation at sharp corners). Various other instances of the spiral coil 108 can be employed, such as a multilayer spiral coil 108, a multi-tap spiral coil 108, etc.

[0076] The shielding element for the spiral inductor 102 includes a patterned ground shield 112 (sometimes referred to as a magnetic shield). Various patterned ground shield (PGS) 112 designs can be employed according to various embodiments of the present invention. The depicted designs include various conductive elements 114 positioned perpendicular to the direction of current flowing through the coil 108. Such positioning can trap magnetic flux from the coil 108, which can reduce coupling between the coil 108 and other devices (e.g., circuit elements located near the coil 108). This coupling may induce current in the PGS 112, which may in turn couple to other elements, such as circuit components. Therefore, the PGS 112 may include conductive interconnections 116 between the conductive elements 114 to control the location of the return current circulating around the PGS 112. Furthermore, various connections to a reference voltage (which may include a ground reference or a reference to another voltage, such as VCC) can help reduce current in the PGS, thereby contributing to isolation. While reducing the impedance between the PGS 112 and the ground plane can contribute to isolation, in some cases, adequate grounding to achieve isolation thresholds may not be practical. In addition, the ground plane may increase the capacitance of coil 108.

[0077] The filter 118 (e.g., a notch filter) can store energy according to the resonant circuit. For example, the filter 118 can form an LC cavity with an inductor 122 (or aggregate inductance) and an aggregate capacitor (based on the geometry of the PGS 112 and the dielectric disposed between the various parts to form a capacitor). The LC cavity stores energy at the system's resonant frequency and can then be dissipated depending on the resistance 120 of the filter 118 or another ground path. Therefore, the energy density at the resonant frequency can be reduced, thereby reducing the coupling between the coil 108 or the PGS 112 and the various circuit components. That is, the isolation between the coil 108 and the various circuit components nearby can be increased.

[0078] According to some embodiments of this utility model Figure 2Figure 200 shows the application of filter 118 to isolate PGS 112. Isolation is depicted along isolation axis 202, for example, on a decibel scale, extending from a greater isolation at the lowermost portion of isolation axis 202 to a lesser isolation at the uppermost portion of isolation axis 202. Isolation can refer to the isolation between coil 108 or PGS 112 and any components of the circuit, such as active components (e.g., diodes, transistors, or passive elements) or interconnections. Frequency axis 204 extends from low frequencies (e.g., DC state) to high frequencies. High frequencies can vary depending on the specific application. For example, according to various embodiments of the present invention, high frequency can refer to a frequency range in the gigahertz (GHz) range, such as tens of GHz, or a frequency range extending into an RF band of approximately 300 GHz.

[0079] The first frequency-dependent isolation line 206 extends from a high isolation (according to any scale) when in a DC state (e.g., corresponding to DC electrical isolation between coil 108 or PGS 112 and the circuit). As the frequency increases (e.g., into the GHz range), the isolation decreases, for example, according to the induced current in the PGS 112 coupled to the circuit elements. A specific curve of the first frequency-dependent isolation line 206 will vary depending on the drive strength, circuitry, PGS 112 or coil 108 geometry, bias voltage, etc. However, once it rises above the isolation critical line 208 at a relatively low frequency (according to some embodiments, this may correspond to frequencies in the MHz range or low GHz range, although various coil 108, PGS 112, or circuit geometry can produce various other frequency ranges), the first frequency-dependent isolation line 206 remains above the isolation critical line 208. Therefore, the isolation can be less than the critical, where the critical can correspond to design rules, calculated values, or other desired values.

[0080] The second frequency-dependent isolation line 210 depicts the isolation between coil 108 and the circuit, wherein filter 118 is connected to PGS 112. The first center frequency 212 of the second frequency-dependent isolation line 210 may correspond to the resonant frequency of the LC cavity. That is, as described above, the energy maintained within the PGS-filter complex or dissipated by the PGS-filter complex can be decoupled from the circuit elements, thereby increasing isolation. The second frequency-dependent isolation line 210 exhibits better isolation from the DC state to the first crossover point 214, wherein the parasitic capacitance and inductance 122 introduced by filter 118 overcome the energy mitigated by filter 118.

[0081] Both the first center frequency 212 and the first crossover point 214 can vary depending on filter characteristics, such as the routing, location, material, or any other characteristics of the filter 118 related to parasitic or leakage current paths. Figure 1The values ​​of the components of filter 118 depicted (e.g., changes in inductor 122 or resistor 120) are shown. For example, the second frequency-dependent isolation line 216 is depicted as having a second center frequency 218 higher than the first center frequency 212, and a second crossover point 220 higher than the first crossover point 214. Although the depicted first and second frequency-dependent isolation lines 210, 216 depict isolation representations corresponding to the alternative filter 118, in some embodiments, a multi-polar filter (e.g., a filter including first and second RL branches) may be connected to PGS 112. For example, the filter may operate at different frequencies at which the spiral inductor 102 operates, such as harmonics of a base frequency.

[0082] A simplified description of the center frequency can correspond to the cutoff frequency associated with filter 118. For example, for Figure 1 The cascaded RL filter 118 shown has an angular frequency defined as follows: f c =R / 2πL, where either R or L can correspond to a component or lump model. For example, resistor 120 may include various parts of semiconductor device 100 (e.g., resistor 120 may include a resistor implemented as a serpentine resistor, and series resistor 120 of inductor 122, as well as any interconnects, etc.).

[0083] While this relationship can provide a first-order approximation (e.g., an order of magnitude of the center frequency), further simulations or analyses can be used to determine the actual center frequency, such as a frequency of approximately 1 GHz. For example, a first series RL filter 118 may include a nanohenry (nH) inductor 122 and a 20-ohm resistor 120, exhibiting an angular frequency of approximately 3 GHz, but the corresponding center frequency of the notch filter 118 could be approximately 7.5 GHz. In another example, the first series RL filter 118 may include a 100 pH inductor 122 and a 10-ohm resistor 120, exhibiting an angular frequency of approximately 16 GHz, but the corresponding center frequency of the notch filter 118 could be approximately 14 GHz. The selection of components of filter 118 based on the frequency of interest can be referred to as the tuning of filter 118. The frequency of interest may include the center frequency or another frequency, or a frequency range not exceeding the intersection point.

[0084] According to some embodiments of this utility model Figure 3This is a cross-sectional view of semiconductor device 100. This cross-sectional view depicts the uppermost layer as a redistribution (RDL 302) layer. The RDL 302, which is thicker than other layers (larger in the vertical direction as shown), can form a spiral inductor 102 with relatively low series resistance; however, this is not intended to limit the invention. The RDL may include copper, aluminum, or other conductive materials. Furthermore, in various embodiments, additional layers may be disposed above the RDL 302, but these layers are not depicted for clarity and brevity. The RDL 302 includes various generally concentric portions of coil 108, and a first terminal 104 shown connected to coil 108, which is shown extending away from coil 108. That is, the cross-sectional view shown can be viewed along the extension... Figure 1 The cut line at the center of the depicted coil 108 passes through the first terminal 104 and the second terminal 106.

[0085] In addition to the second terminal 106, the coil 108 is shown coupled to the via structure 110 to extend vertically from RDL 302 to another layer of the semiconductor device 100, such as the third metallization layer 304. The second terminal 106 is depicted passing underneath the coil 108 within the third metallization layer 304 for connection to another element of the semiconductor device 100. Although no other conductive elements are depicted on the third metallization layer 304, in various embodiments, the layer may include additional conductive elements. For example, the area may include dummy fillers to meet design rules, or as... Figure 5 Further described filter components include, for example, taps, terminals, or coils 108 of inductor 122, resistive elements (e.g., serpentine, strip, or gate resistors), etc. These elements may be coupled to additional via structures (not depicted) to couple to PGS 112.

[0086] The second metallization layer 306 of the semiconductor device 100 includes the depicted conductive element 114 of the PGS 112. This conductive element 114 is shown parallel to the current flowing through the coil 108 (e.g., shown as a conductive element parallel to the coil 108) to depict another non-limiting example of the various geometries that the various portions of the PGS 112 may include. The second metallization layer 306 may be referred to as being "perpendicularly adjacent" to the third metallization layer 304 and the first metallization layer 308, even if there is a gap for the via structure 110 or the via structure 110 itself.

[0087] The first metallization layer 308 of the semiconductor device 100 is shown divided into a central region, displaying a restricted placement region 312, such as a region where the frequency, sensitivity, or other characteristics of circuit elements are limited. For example, the propagation of clock pulses, non-slewed probes, or other signals may not cross the restricted placement region 312, for example, to avoid coupling to the coil 108, interfering with its operation, or preventing the coil 108 from interfering with circuit elements (e.g., to avoid coupling signals from the coil 108 to clock pulses or data lines, which could subsequently interfere with those signals). The boundary of the restricted placement region 312 is an exclusion region 310, which may impose additional restrictions. For example, the region directly beneath the coil 108 element may correspond to the exclusion region 310, and the central region of the coil 108 may correspond to the restricted placement region 312. References below... Figure 4 Provided top view. The description of exclusion region 310 and restricted configuration region 312 is not intended to limit the present invention. Depending on various thresholds, one or more configurations may be restricted to the configuration of circuits under inductors (CUL).

[0088] Various additional layers (e.g., metallization layers) may lie beneath the depicted first metallization layer 308. For example, the first metallization layer 308 may be formed over a semiconductor substrate, having, for example, zero, one, two, or three metallization layers. The semiconductor substrate may include an active surface 314, which includes various n-wells 316 and p-wells 318 (along with other devices, depending on the planar or other process) that can be interconnected to form diodes, transistors, image sensors, etc., which in turn can be interconnected or connected to other terminals or devices to form circuits, such as logic circuits, memory devices, etc. Such interconnections may be formed in any metallization layer. Any one of the regions disposed along the active surface 314, or the interconnections between them, or the interconnections between other devices or terminals, may be referred to as a circuit. Therefore, the isolation between the coil 108 and the circuit may depend on various circuit portions.

[0089] Figure 4 Regarding the spiral inductor 102 with filter 118 (e.g., Figure 1The exclusion region diagram 400 of the spiral inductor 102 is shown. The exclusion region diagram 400 may correspond to various lateral planes of the semiconductor device 100, such as the active surface 314 of a semiconductor substrate containing p-wells and n-wells, perpendicularly spaced from the coil 108 of the spiral inductor 102, or metallization layers 304, 306, 308 including conductive elements, such as conductive elements for interconnecting the active surface 314 to form various circuits. In some embodiments, the various layers may have one or more corresponding exclusion region diagrams.

[0090] The filter 118 corresponding to the depicted exclusion region diagram 400 may include an RL filter 118 not tuned to the operating frequency, such that the isolation between the coil 108 and the circuitry exceeds a critical threshold. The restricted configuration region 312 may correspond to the central region of the coil 108 (e.g., a central opening defined by the winding). For example, the central opening may be defined based on a lateral offset from the innermost portion of the coil 108. The exclusion region 310 may correspond to a region located directly beneath the winding of the coil 108, or counteract its lateral offset. Other portions of the semiconductor device 100 may include an unrestricted configuration region 402 (at least relative to the helical coil 102). Different exclusion region diagrams 400 may correspond to various layers of the semiconductor device 100. For example, layers of the semiconductor device 100 located away from PGS 112 or coil 108 may be completely omitted or include fewer restricted configuration regions 312 or exclusion regions 310, or restrict fewer restricted configuration regions 312 or exclusion regions 310.

[0091] According to some embodiments of this utility model Figure 5 This is a top view of a semiconductor device 100 including a multi-tap coil 108. The depicted semiconductor device 100 implements at least a portion of a filter 118 along the same vertical plane (including its central region) of the coil 108. A multi-tap inductor can refer to or include an inductor comprising a first terminal, a second terminal, and at least one terminal between the first and second terminals. A multi-tap inductor can include a pattern for multiple inductors. For example, for at least some signals (e.g., DC signals), two intermediate terminals can electrically isolate two inductors from each other. Multi-tap inductor patterns are relatively space-saving or dense, even for functionally unrelated inductors. Furthermore, according to some embodiments, the proximity of the windings in a multi-tap inductor can facilitate mutual coupling between them.

[0092] In detail, coil 108 may include an additional winding 502, as shown, which is laterally bounded or bounding other windings of coil 108. The additional winding 502 may be disposed along the same layer as other portions of semiconductor device 100 and other coil 108 portions (e.g., RDL 302), or may be disposed on another layer (e.g., third metallization layer 304). The additional winding 502 may terminate at a first terminal 504, shown as terminating within the central region of coil 108. That is, the additional winding 502 may terminate at a via structure connected to another layer, or terminate at another conductive element disposed on the same layer (e.g., resistor 120 or a portion thereof). Another end of the additional winding 502 may extend to another via structure 110, such that a second terminal 506 of the additional winding 502 extends laterally outside coil 108. For example, the second terminal 506 of the additional winding 502 may extend along the same layer as the second terminal 106 of the coil 108, or along another layer (e.g., according to...). Figure 3 The depicted view extends on a layer positioned above RDL 302. Although one terminal 504 is depicted terminating within the central region of coil 108, and the other terminal 506 terminating outside coil 108, various embodiments may connect circuit portions at various locations. For example, the two terminals 504, 506 may begin and terminate inside or outside the central region of coil 108, or the two terminals 504, 506 may pass above or below other windings of coil 108.

[0093] Further depiction of the resistor 120 for filter 118, although shown as a serpentine resistor, may include various elements within or between layers of semiconductor device 100. In some embodiments, the resistor may include interlayer connections. For example, resistor 120 may include via structures 100 or via chains coupled to another element. Furthermore, although depicted separately, inductor 122 and resistor 120 of filter 118 may include coextensive elements. For example, instead of forming the resistor in a serpentine pattern, at least some portions may be formed as lateral or multilayer spirals configured to increase the series resistance 120. That is, in contrast to employing a “thick” RDL 302, inductor 122 may be formed in a relatively “thin” metallization layer to increase resistance 120. Similarly, depending on various configurations, the terminals of the resistor may begin, terminate, or pass through above or below the winding of coil 108. For example, in the case of implementing inductor 122 and resistor 120 according to integrated passive device (IPD), they can be connected to the external portion of PGS112 outside of coil 108.

[0094] Various combinations of elements can be implemented (e.g., adjusted) to achieve various filters 118 based on isolation thresholds at frequencies of interest. Furthermore, this exemplary paradigm is not intended to limit the invention; in various embodiments, either resistor 120 or inductor 122 may be formed in another portion of semiconductor device 100, for example, along active surface 314, from epitaxial silicon along another layer, or may include discrete devices (e.g., IPDs) connected thereto. Additionally, some filters 118 may include additional elements, such as capacitors or parallel resistors 120 or inductors 122, which can adjust or increase the center frequency (e.g., forming notch filters 118 corresponding to one or more frequencies of interest).

[0095] Now refer to Figure 6 According to some embodiments, a top view 600 of a semiconductor device 100 including various circuits is provided. For example, top view 600 may correspond to... Figure 4 The exclusion region diagram 400 shows that filter 118 is tuned to the frequency of interest. For example, spiral inductor 102 may be part of a power distribution network (PDN) operating at a predefined frequency, where the notch filter is configured with a center frequency corresponding to the operating frequency of spiral inductor 102.

[0096] The first circuit 602 or a portion thereof is shown positioned below the central region of the view, which may correspond to the region laterally defined by the winding of coil 108 (e.g., corresponding to...). Figure 4 The restricted configuration area 312) is vertically separated. The second circuit 604 or a portion thereof is shown positioned below the central region of the view and vertically separated from the winding of coil 108 (e.g., corresponding to the restricted configuration area 312). Figure 4 The exclusion region 310 and the restricted configuration region 312). The third circuit 606 or a portion thereof is shown as being perpendicularly spaced from the winding of coil 108 (e.g., corresponding to the exclusion region 310 and the restricted configuration region 312). Figure 4 Exclusion region 310). The fourth circuit 608 or a portion thereof is shown as being perpendicularly spaced from and outside the winding of coil 108 (e.g., corresponding to). Figure 4 (The restricted configuration area 312 and the unrestricted configuration area 402). The fifth circuit 610 or a portion thereof is shown below the central region of the view, which is perpendicularly spaced from the winding of coil 108 and located outside the winding (e.g., corresponding to the winding). Figure 4 Exclusion zone 310, restricted configuration zone 312, and unrestricted configuration zone 402).

[0097] Now refer to Figure 7According to some embodiments, a method 700 for forming a semiconductor device is provided. For example, at least some operations described in method 700 can produce the semiconductor device or view depicted in Figures 1-6. The method 700 is a non-limiting example and can be used in… Figure 7 Additional operations are provided before, during, and after method 700. Furthermore, some operations may only be briefly described in this invention; however, those skilled in the art will understand that these operations can be performed in combination with this invention or other methods known in the art. Moreover, the order of the operations is not intended to be limiting; some operations can be performed in a different order, and other operations can be ordered by appropriate modifications. Furthermore, at least a portion of some operations can be performed simultaneously. For example, a layer comprising the inductor 122 containing the filter 118 and the second terminal 106 of the spiral inductor 102 can be formed to simultaneously form two elements. Furthermore, various operation sequences can produce… Figure 3 Various numbers or relative positions of the depicted layers (e.g., their circuit portions may be positioned above or below PGS112, above or below RDL 302, etc.).

[0098] Method 700 includes operation 702, forming interconnect layers between various portions of an active surface 314 of a semiconductor device 100. For example, interconnects may be formed in, or extend from, one or more metallization layers above, the active surface 314 (e.g., a plane or other active surface 314). Interconnects may include connections between portions of the active surface (e.g., n-wells, p-wells, gate structures, oxides, etc.). A portion of the interconnect may be disposed vertically above the active surface 314. A portion of the interconnect may extend laterally from the active surface 314, for example, to connect to additional elements of the semiconductor device 100 (e.g., redistribution layers, terminals, such as microbumps, another active surface, etc.). For example, the first interconnect layer may include via structures (e.g., well contact vias).

[0099] A second interconnect layer may be formed above the first interconnect layer. The second interconnect layer includes lateral conductive elements to connect one or more via structures in the first interconnect layer, or to junction sites of via structures in the third interconnect layer. Additional interconnect layers may be formed above the surface of the semiconductor device 100. These interconnect layers include alternating via structures and lateral conductive elements. The nomenclature used for interconnect layers or metallization layers is not intended to be limiting and is provided only for distinction. Figure 7 The other layers of method 700, which correspond to Figure 3The depicted layers. These layers may be referred to as any of the following: interconnect or metallization layers according to the present invention. These interconnect layers may be formed by alternately forming metal layers, patterning on metal layers, and selectively removing portions of metal layers (e.g., according to photolithography processes, such as positive or negative photoresist processes). Dielectrics may be formed between interconnects to electrically isolate their portions. Interconnects or elements on active surfaces may be referred to individually or in combination as circuits, circuit portions, etc.

[0100] Method 700 includes operation 704, forming a first metallization layer 308 over the interconnect layer. The first metallization layer 308 may include exclusion regions 310 or restricted configuration regions 312. For example, lateral portions of the first metallization layer 308 may include dielectric or conductive elements (e.g., metallization dummy fillers) that are not connected to the network. According to some embodiments, the first metallization layer 308 may include a portion of an RL filter 118. The filter 118 may be electrically connected to a PGS 112.

[0101] Method 700 includes operation 706, forming a second metallization layer 306 over the interconnect layer of operation 702. The second metallization layer 306 may include at least a portion of PGS 112. The second metallization layer 306 may be formed using the same or related process as the interconnect of operation 702. That is, a photomask may define a pattern in photoresist to define various conductive elements 114 and conductive interconnects 116 of PGS 112. In some embodiments, PGS 112 may be planar and disposed on a single metallization layer of semiconductor device 100. In some embodiments, PGS 112 may span multiple layers of semiconductor device 100, wherein PGS 112 may include via structures 110 for interconnecting the layers. In some embodiments, PGS 112 may include one or more signal paths to ground or another reference voltage, which may include, but are not limited to, RL filter 118. In some embodiments, PGS 112 may include capacitance between its various portions. A portion of RL filter 118 may be disposed on the second metallization layer 306, the first metallization layer 308, or another layer of semiconductor device 100.

[0102] In some embodiments, filter 118 is electrically connected to PGS 112 via a via structure 110 extending vertically therebetween (e.g., to a portion of resistor 120 or inductor 122 on another layer, such as first metallization layer 308 or third metallization layer 304). In some embodiments, filter 118 may be electrically connected to PGS 112 via a lateral connection, such as laterally connected to resistor 120 or inductor 122 laterally spaced from PGS 112. Thus, filter 118 assembly may be or include portions that are vertically or laterally spaced from PGS 112. Filter 118 may include resistor 120 formed by a metallization layer (e.g., a serpentine resistor). Filter 118 may include resistor 120 formed along the active surface 314 of semiconductor device 100, or resistor 120 formed by other non-metallic portions (e.g., oxide or epitaxial silicon formed perpendicularly spaced from active surface 314). At least a portion of the resistor may be a series resistor of the inductor 122 of filter 118, or an interlayer connection (e.g., via chain). Inductor 122 may be formed laterally spaced from PGS 112 or spiral inductor 102 of operation 708. For example, inductor 122 may be formed on the same layer as spiral inductor 102 of operation 708, or on a layer between spiral inductor 102 and PGS 112. For example, inductor 122 may be formed below the winding of spiral inductor 102, in a central region perpendicular to spiral inductor 102, or laterally spaced from spiral inductor 102.

[0103] Method 700 includes operation 708, forming a spiral inductor 102 over a second metallization layer 306. The spiral inductor 102 may be formed on one or more layers of a semiconductor device. For example, the coil 108 of the spiral inductor 102 may be formed in an RDL 302. The spiral inductor 102 may include terminals extending to another layer, for example, connected to another device disposed on another layer, or extending beneath the coil 108 to another region of the semiconductor device 100 laterally spaced from the coil 108. For example, the coil 108 may be a coil 108 for a PDN of the semiconductor device 100, wherein terminals 102, 104 are connected to additional PDN elements (e.g., additional PDN elements of RDL 302).

[0104] According to some embodiments, the present invention provides a semiconductor device, comprising: a spiral inductor; a patterned ground shield (PGS) electrically coupled to the spiral inductor; a filter configured to exchange energy with the patterned ground shield; and a circuit perpendicularly spaced from the spiral inductor, wherein the patterned ground shield is disposed between the circuit and the spiral inductor.

[0105] In some embodiments, the spiral inductor includes a copper redistribution layer.

[0106] In some embodiments, at least a portion of the circuitry is disposed in a single layer, which is vertically adjacent to the grounded shield.

[0107] In some embodiments, the spiral inductor has a first terminal and a second terminal, the first terminal extending above a patterned ground shield along the same layer as the coil of the spiral inductor, and the second terminal extending above a patterned ground shield along a layer disposed between the spiral inductor and the patterned ground shield.

[0108] In some embodiments, the filter includes a second inductor connected in series with the resistor, and the center frequency of the filter corresponds to the operating frequency of the spiral inductor.

[0109] In some embodiments, the spiral inductor is a multi-tap spiral inductor; and includes taps for a second inductor.

[0110] In some embodiments, the second inductor is laterally spaced from the patterned ground shield.

[0111] In some embodiments, at least a portion of the circuitry is disposed below the central region of the spiral inductor.

[0112] In some embodiments, at least a portion of the circuitry is disposed below the winding of the helical inductor.

[0113] In some embodiments, the filter is a notch filter, and its center frequency corresponds to the operating frequency of the circuit.

[0114] In some embodiments, the filter is a notch filter, the center frequency of which corresponds to the component of the signal passing through the spiral inductor.

[0115] In some embodiments, the filter is a notch filter having a center frequency exceeding approximately 1 GHz.

[0116] According to other embodiments, the present invention provides a semiconductor system comprising: a first inductor configured to operate at a frequency; a second inductor; and a capacitor comprising: a first conductive element with a patterned ground shield electrically coupled to the first inductor; a second conductive element with a patterned ground shield; and a dielectric disposed between the first conductive element and the second conductive element, wherein the capacitor and the second inductor form an LC cavity configured to resonate at the aforementioned frequency.

[0117] In other embodiments, it further includes: a circuit vertically spaced from the first inductor, with a patterned ground shield disposed between the circuit and the first inductor.

[0118] In other embodiments, the coil of the first inductor is disposed on a first layer of the semiconductor device; the coil of the second inductor is disposed on a second layer of the semiconductor device; and at least a portion of the patterned ground shield is disposed on a third layer of the semiconductor device.

[0119] In other embodiments, the first layer of the semiconductor device is an RDL layer, and the second layer of the semiconductor device is not an RDL layer.

[0120] In other embodiments, the first inductor is part of the power distribution network (PDN) of the semiconductor device.

[0121] In other embodiments, the frequency described above exceeds a frequency range.

[0122] One aspect of this invention relates to a filter. The filter includes an inductor. The filter includes a series resistor associated with the inductor (e.g., coupled to, co-extended with, etc.). A first terminal of the filter is connected to a patterned ground shield (PGS). The PGS is electrically coupled to a spiral inductor. A second terminal of the filter is connected to a reference voltage. The center frequency of the filter is greater than 1 GHz.

[0123] According to yet another embodiment, the present invention provides a method for manufacturing a semiconductor device, comprising: forming a metallization layer on an active surface of a semiconductor substrate, the metallization layer including a first terminal of a patterned ground shield, the first terminal being connected to a shunt resistor of a filter having a center frequency exceeding 1 GHz; and forming an inductor on the metallization layer, the inductor being electrically coupled to the patterned ground shield.

[0124] In some other embodiments, the filter includes: a graphically grounded shielded aggregate capacitor; an inductor; and a series resistor, the filter having an LC cavity at the center frequency.

[0125] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand the viewpoints of the present invention. Those skilled in the art should understand that other processes and structures can be easily designed or modified based on the embodiments of the present invention to achieve the same purpose and / or advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent structures do not depart from the spirit and scope of the embodiments of the present invention, and various changes, substitutions, and replacements can be made without departing from the spirit and scope of the embodiments of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A semiconductor device, characterized in that, include: A spiral inductor; The grounding shield, as shown in the diagram, is electrically coupled to the spiral inductor. A filter is electrically coupled to the grounding shield of the diagram. as well as A circuit is perpendicularly separated from the spiral inductor, and a grounding shield of this type is disposed between the circuit and the spiral inductor.

2. The semiconductor device as claimed in claim 1, characterized in that, The spiral inductor includes a copper redistribution layer.

3. The semiconductor device as claimed in claim 1, characterized in that, At least a portion of the circuit is located in a layer that is perpendicular to the grounded shield of the diagram.

4. The semiconductor device as claimed in claim 1, characterized in that, The spiral inductor has a first terminal and a second terminal. The first terminal extends above the patterned ground shield along a layer identical to that of a coil of the spiral inductor, and the second terminal extends above the patterned ground shield along a layer disposed between the spiral inductor and the patterned ground shield.

5. The semiconductor device according to any one of claims 1 to 4, characterized in that, At least a portion of the circuit is located below a central region of the spiral inductor.

6. The semiconductor device according to any one of claims 1 to 4, characterized in that, At least a portion of the circuit is located below one winding of the spiral inductor.

7. A semiconductor system, characterized in that, include: A first inductor, configured to operate at a frequency; A second inductor; as well as A capacitor, comprising: A first conductive element of a grounded shield type is electrically coupled to the first inductor; This diagram shows a second conductive element of a grounding shield. as well as A dielectric material is disposed between the first conductive element and the second conductive element, wherein The capacitor and the second inductor operatively form an LC cavity, which is configured to resonate at the frequency.

8. The semiconductor system as claimed in claim 7, characterized in that, Also includes: A circuit is perpendicularly separated from the first inductor, and a grounding shield is disposed between the circuit and the first inductor.

9. The semiconductor system as described in claim 7 or 8, characterized in that: One coil of the first inductor is disposed on a first layer of a semiconductor device; One coil of the second inductor is disposed on a second layer of the semiconductor device; and At least a portion of the grounding shield of this pattern is disposed on a third layer of the semiconductor device.

10. The semiconductor system as claimed in claim 9, characterized in that, The first layer of the semiconductor device is a redistribution layer, and the second layer of the semiconductor device is not a redistribution layer.

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