Maximum supply voltage selection circuit

Abstract

The utility model discloses a maximum power supply voltage selection circuit which comprises an analog amplification circuit, a logic circuit and a pair of NMOS (N-channel Metal Oxide Semiconductor) transistors, and the analog amplification circuit comprises an amplification module and a starting module. The analog amplification circuit adopts a three-stage amplification module cascading mode, so that the voltage comparison precision can be improved, and finally, the logic circuit selects the maximum power supply voltage. In addition, a starting circuit is arranged, when the voltages of the two power supplies are equal, the starting circuit works and forcibly assigns a voltage value to the output end, and it is guaranteed that the operational amplifier can work normally.

Description

Technical Field

[0001] This invention relates to the field of CMOS image sensor technology, and more specifically to a maximum power supply voltage selection circuit. Background Technology

[0002] In CMOS image sensors, charge pumps are commonly used to power pixel drive signals. Current is generated when the drive signal is at its rising and falling edges. Q = I * T = C * V, where Q is the charge, I is the average current during the signal rise and fall time, T is the signal rise and fall time, C is the pixel load capacitance, and V is the change in drive signal potential. Therefore, when the pixel load capacitance C and the change in drive signal potential V are large, a larger average current is required to maintain a fast rise time for the drive signal, necessitating a larger charge pump capacity. A common approach is to increase the number of bits in the charge pump, but this significantly increases the layout area and power consumption of the charge pump, which does not meet the design requirements of small-area, low-power products. Alternatively, a multi-power supply drive circuit can be used to reduce dependence on the charge pump. The design concept is that the rising and falling edges of the drive signal are powered by an external power supply (provided by the multi-power supply drive circuit), while the signal is stable and during pixel signal readout, the charge pump is used. This alternation between the multi-power supply drive circuit and the charge pump significantly reduces dependence on the charge pump while ensuring that the drive signal characteristics are not affected.

[0003] Figure 2 In a possible multi-supply drive circuit structure, when the drive signal switches, the voltage drop, crosstalk, and other factors can cause changes in the power supply potential, easily generating a through-current. For example, when SEL_N1 is low and MN_DRV1 is completely off, if V2 is used as the power supply (i.e., SEL_P2 is low and MP_DRV2 is fully on), the output node OUT is V2. At this time, the source, substrate, and gate voltages of MP_DRV1 are all V1, while its drain voltage is V2. Due to voltage drop, crosstalk, and other factors, the power supply voltage V2 > the power supply voltage V1. Therefore, MP_DRV1 undergoes source-drain swapping, and since neither the source nor the substrate potential is at its highest, a through-current is generated, flowing from V2 to V1 (e.g., ...). Figure 2 As shown, the through current will cause insufficient charge pump supply capacity, making the change of power supply potential more uncontrollable, and ultimately affecting the function and characteristics of the circuit. Summary of the Invention

[0004] Technical issues

[0005] In the case of a combined circuit of a multi-power supply drive circuit and a charge pump, when the drive signal is switched, the potential of the power supply will change due to voltage drop, crosstalk, and other factors, which can easily generate a through current. This current can lead to insufficient supply capacity of the charge pump, thereby affecting the characteristics of the circuit.

[0006] The purpose of this invention is to provide a maximum power supply voltage selection circuit that compares two power supplies and selects the larger one to supply power to the gate and substrate of the PMOS transistor in the drive circuit, thereby avoiding the generation of through current in the drive circuit and ultimately ensuring the circuit function and characteristics.

[0007] Solutions to technical problems

[0008] The maximum power supply voltage selection circuit provided by this invention includes an analog amplifier circuit, a logic circuit, an NMOS transistor MN13, and an NMOS transistor MN14; wherein, the analog amplifier circuit includes an amplification module and a startup module;

[0009] The amplifier module is connected to power supply V1 and power supply V2 at the same time, and the output signals SW_out1 and XSW_out1 are connected to the input terminal of the start-up module and the input terminal of the logic circuit, respectively.

[0010] The startup module is connected to power supply V2, and the logic circuit is connected to both power supply V1 and power supply V2. The logic circuit output signals SW_out2 and XSW_out2 are connected to the gates of NMOS transistor MN13 and NMOS transistor MN14, respectively.

[0011] The drain of NMOS transistor MN13 is connected to power supply V1, the drain of NMOS transistor MN14 is connected to power supply V2, and the common terminal of the source of NMOS transistor MN13 and the source of NMOS transistor MN14 outputs the signal Vout.

[0012] Furthermore, the analog amplifier circuit includes:

[0013] The bias module is used to provide the tail current source for the first-stage amplification module;

[0014] The first-stage amplification module is used to convert the differential between the two power supplies into a differential current.

[0015] The second-stage amplification module is used to compare the current difference and obtain two differential-mode voltage signals;

[0016] The third-stage amplification module is used to amplify the two differential signals and output two completely inverted analog switching signals.

[0017] The startup module is used to activate when the third-stage amplification module generates two in-phase analog signals, repeating the operation steps from the first-stage amplification module to the third-stage amplification module.

[0018] Furthermore, in the first stage amplification module, the common terminal of the source of PMOS transistor MP2 and the source of MP3 is connected to power supply V1, the common terminal of the drain of MP2 and the drain of MP3 is connected to the drain of NMOS transistor MN2, the gate of MP3 is connected to its drain, the common terminal of the source of MN2 and the source of MN3 is connected to the drain of MN9, the gate of MN2 is connected to its drain, the source of MN9 is grounded, and the gate of MN9 is connected to the gate of MN8.

[0019] The drain of MN3 is connected to the drain of PMOS transistor MP4, the gate of MN3 is connected to its drain, the gate of MP4 is connected to its drain, and the source of MP4 is connected to power supply V2.

[0020] Furthermore, in the second-stage amplification module, the source of PMOS transistor MP5 is connected to power supply V1, the gate of MP5 is connected to the common terminal of the drain of MP3 and the drain of MN2, the drain of MP5 is connected to the drain of NMOS transistor MN5, the common terminal of the source of MN5 and the source of MN4 is grounded, the drain of MN4 is connected to the drain of MN5, and the gate of MN4 is connected to the common terminal of the drain of MN4 and the drain of MN5.

[0021] The source of PMOS transistor MP6 is connected to power supply V2, the gate of MP6 is connected to the gate of MP4, the drain of MP6 is connected to the common terminal of the drains of MN6 and MN7, the gate of MN7 is connected to the drain of MN7, the common terminal of the source of MN6 and the source of MN7 is grounded, the common terminal of the source of MN5 and the source of MN6 is connected to the drain of MN10, the source of MN10 is grounded, the gate of MN5 is connected to the common terminal of the drain of MN6 and the drain of MP6, and the gate of MN6 is connected to the common terminal of the drain of MN5 and the drain of MP5.

[0022] Furthermore, the width of the NMOS transistor MN6 is N times the width of the NMOS transistor MN4, generating a voltage Vt+, and the width of the NMOS transistor MN7 is N times the width of the NMOS transistor MN5, generating a voltage Vt-.

[0023] Furthermore, the third-stage amplification module includes two operational amplifiers. The positive input terminal of the first operational amplifier OPAMP1 is connected to the negative input terminal of the second operational amplifier OPAMP2, and is simultaneously connected to the voltage signal Vd_MP5 generated by the second-stage amplification module. The negative input terminal of the first operational amplifier OPAMP1 is connected to the positive input terminal of the second operational amplifier OPAMP2, and is simultaneously connected to the voltage signal Vd_MP6 generated by the second-stage amplification module. The first operational amplifier OPAMP1 is connected to the power supply voltage V1, and the second operational amplifier OPAMP2 is connected to the power supply voltage V2. The first operational amplifier OPAMP1 and the second operational amplifier OPAMP2 are simultaneously connected to the gate of MN10.

[0024] Furthermore, in the startup module, the source of MP7 is connected to power supply V1, the drain of MP7 is connected to the drain of MN11, the gate of MP7 is connected to the drain of MP7, the source of MN11 is the drain of MN12, the gate of MN11 is connected to the output of the second operational amplifier OPAMP2, the source of MN12 is grounded, the gate of MN12 is connected to the output of the first operational amplifier OPAMP1, and the common terminal of the drain of MP7 and the drain of MN11 is connected to the gate of MP2.

[0025] Furthermore, the logic circuit includes an AND gate, an OR gate, an inverter, and an NMOS transistor. One input of the first AND gate AND1 is connected to the signal XSW_out1, the other input is connected to the signal XSEL1, and the output is connected to one input of the first OR gate OR1. The other input of the first OR gate OR1 is connected to the first inverter INV1. The output of the first OR gate OR1 is connected to the gate of the NMOS transistor MN15. The drain of MN15 is connected to the power supply V2. The common terminal of the source of MN15 and the source of MN16 is connected to the output terminal. The drain of MN16 is connected to the power supply V1, and the gate is connected to the output of the second OR gate OR2.

[0026] One input of the second AND gate AND2 is connected to the signal SW_out1, the other input is connected to the signal XSEL2, the output is connected to one input of the second OR gate OR2, and the other input of the second OR gate OR2 is connected to the second inverter INV2.

[0027] The first AND gate AND1, the first OR gate OR1, and the first inverter INV1 are all connected to power supply V2, while the second AND gate AND2, the second OR gate OR2, and the second inverter INV2 are all connected to power supply V1.

[0028] Beneficial effects

[0029] (1) The maximum power supply voltage selection circuit provided by the present invention improves the comparison accuracy of the power supply voltage through three-stage amplification;

[0030] (2) By setting a threshold voltage in the second-stage amplification module, the power supply switching caused by glitches is avoided.

[0031] (3) Introduce a startup circuit to avoid the situation where the operational amplifier cannot output an inverted differential signal when the difference between the two power supplies is small, which would cause the circuit to malfunction.

[0032] (4) By using a MOS transistor to control the power output, the output potential is V1-I*Ron or V2-I*Ron, where Ron is the turn-on resistance of the MOS transistor controlled by SW_ou2 and XSW_out2. In the drive circuit, since there is no current branch, the output power potential can be achieved with almost no loss. Attached Figure Description

[0033] The accompanying drawings provided herein are for further illustration of embodiments of the present invention to facilitate understanding, and are not intended to limit the scope of the present invention.

[0034] Figure 1 This is a schematic diagram of the maximum power supply voltage selection circuit of the present invention;

[0035] Figure 2 This is a schematic diagram of a multi-power supply drive circuit to achieve current flow.

[0036] Figure 3 This is a schematic diagram of the analog amplifier circuit of the present invention;

[0037] Figure 4 This is a schematic diagram of the logic circuit of the present invention;

[0038] Figure 5 This is a diagram showing the internal voltage changes of the second-stage amplifier circuit of the present invention;

[0039] Figure 6 This is a comparative schematic diagram showing the power switching caused by glitches in the second-stage amplifier circuit of the present invention under conditions of having and not having a set threshold.

[0040] Figure 7 This is a timing diagram of the control signals of the logic circuit of the present invention under normal operating conditions;

[0041] Figure 8 This is a timing diagram of the control signals for the logic circuit of the present invention in the disabled state. Detailed Implementation

[0042] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to embodiments and accompanying drawings. The illustrative embodiments and descriptions of this invention are for explanation only and are not intended to limit the invention. For the sake of brevity, this document will not describe technologies well-known in the art; any processes not specifically described in detail are those that can be implemented by those skilled in the art with reference to existing technology.

[0043] Figure 1 A schematic diagram of the maximum power supply voltage selection circuit of the present invention is shown in the figure. The circuit includes an analog amplifier circuit, a logic circuit, an NMOS transistor MN13, and an NMOS transistor MN14; wherein, the analog amplifier circuit includes an amplification module and a startup module.

[0044] The amplifier module is connected to power supply V1 and power supply V2 at the same time, and the output signals SW_out1 and XSW_out1 are connected to the input terminal of the start-up module and the input terminal of the logic circuit, respectively.

[0045] The startup module is connected to power supply V2, and the logic circuit is connected to both power supply V1 and power supply V2. The logic circuit output signals SW_out2 and XSW_out2 are connected to the gates of NMOS transistor MN13 and NMOS transistor MN14, respectively.

[0046] The drain of NMOS transistor MN13 is connected to power supply V1, the drain of NMOS transistor MN14 is connected to power supply V2, and the common terminal of the source of NMOS transistor MN13 and the source of NMOS transistor MN14 outputs the signal Vout.

[0047] The working principle of the maximum power supply voltage selection circuit of this invention is to improve the accuracy of voltage comparison through analog amplification circuit, and then the logic circuit selects the maximum power supply voltage. The startup circuit is introduced to deal with the situation where the two power supply voltages are equal. If the two power supply voltages are equal, the startup circuit will activate and forcibly assign a voltage value to the output terminal.

[0048] Figure 3 The structure of the analog amplifier circuit of the present invention is shown in the figure. The analog amplifier circuit includes:

[0049] The bias module is used to provide the tail current source for the first-stage amplification module;

[0050] The first-stage amplification module is used to convert the differential between the two power supplies into a differential current.

[0051] The second-stage amplification module is used to compare the current difference and obtain two differential-mode voltage signals;

[0052] The third-stage amplification module is used to amplify the two differential signals and output two completely inverted analog switching signals.

[0053] The startup module is used to activate when the third-stage amplification module generates two in-phase analog signals, repeating the operation steps from the first-stage amplification module to the third-stage amplification module.

[0054] This invention employs a cascaded three-stage amplification module to improve the accuracy of power supply voltage comparison. The circuit principle is as follows: the first-stage amplification circuit converts the voltage difference into a current difference, amplifying the difference and improving comparison accuracy. Furthermore, PMOS transistors MP5 and MP3, and MP6 and MP4 form a current mirror structure. The dimensions of these four transistors are adjustable, allowing for further current amplification and improved comparison accuracy within power consumption limits. Since the analog differential signal output from the second-stage amplifier cannot be directly used to control subsequent switches, a third-stage amplification module is used to amplify it, increasing the slew rate, and finally outputting a clamped power supply potential, enabling the signal to be used for logic control.

[0055] Furthermore, in the bias module, the source of PMOS transistor MP1 is connected to power supply V1, the drain is connected to the drain of NMOS transistor MN1, and the gate is connected to the drain. The source of NMOS transistor MN1 is connected to the drain of NMOS transistor MN8, and the gate of MN1 is connected to its drain. The source of MN8 is grounded, and the gate of MN8 is connected to its drain. The gate of MN8 is used as the output terminal and connected to the first stage amplification module.

[0056] It should be noted that the bias module is a conventional technique in this field. Those skilled in the art can design circuits with different structures to meet their needs, and are not limited to this one circuit structure.

[0057] Furthermore, in the first-stage amplification module, the common terminal of the source of PMOS transistor MP2 and the source of MP3 is connected to power supply V1, the common terminal of the drain of MP2 and the drain of MP3 is connected to the drain of NMOS transistor MN2, the gate of MP3 is connected to its drain, the common terminal of the source of MN2 and the source of MN3 is connected to the drain of MN9, the gate of MN2 is connected to its drain, the source of MN9 is grounded, and the gate of MN9 is connected to the gate of MN8.

[0058] The drain of MN3 is connected to the drain of PMOS transistor MP4, the gate of MN3 is connected to its drain, the gate of MP4 is connected to its drain, and the source of MP4 is connected to power supply V2.

[0059] The working principle of the first-stage amplification module of this invention is as follows: MP3 and MN2 constitute the first branch, and MP4 and MN3 constitute the second branch. When V1 and V2 are different, and the resistance values ​​are approximately equal (i.e., the resistance values ​​of MP3 and MP4 are approximately equal, and the resistance values ​​of MN2 and MN3 are approximately equal), the tail current sources of the two branches are approximately equal, and the sum of the currents is fixed. The power supply difference will be converted into the difference between the currents of the two branches. When the current in one branch increases, the current in the other branch decreases. The PMOS transistor MP2 is controlled by the startup circuit and is normally off. MP2 is only turned on when the power supply V1 = V2 to avoid outputting an intermediate voltage.

[0060] Furthermore, in the second-stage amplification module, the source of PMOS transistor MP5 is connected to power supply V1, the gate of MP5 is connected to the common terminal of the drain of MP3 and the drain of MN2, the drain of MP5 is connected to the drain of NMOS transistor MN5, the common terminal of the source of MN5 and the source of MN4 is grounded, the drain of MN4 is connected to the drain of MN5, and the gate of MN4 is connected to the common terminal of the drain of MN4 and the drain of MN5.

[0061] The source of PMOS transistor MP6 is connected to power supply V2, the gate of MP6 is connected to the gate of MP4, the drain of MP6 is connected to the common terminal of the drains of MN6 and MN7, the gate of MN7 is connected to the drain of MN7, the common terminal of the source of MN6 and the source of MN7 is grounded, the common terminal of the source of MN5 and the source of MN6 is connected to the drain of MN10, the source of MN10 is grounded, the gate of MN10 is connected to its drain, the gate of MN5 is connected to the common terminal of the drain of MN6 and the drain of MP6, and the gate of MN6 is connected to the common terminal of the drain of MN5 and the drain of MP5.

[0062] The working principle of the second-stage amplification module of this invention is as follows: MN4 and MN6 are interconnected by their gates, and MN5 and MN7 are interconnected by their gates. Furthermore, the width of the MOS transistor MN6 is N times the width of the MOS transistor MN4, generating a voltage Vt+; similarly, the width of the MOS transistor MN7 is N times the width of the MOS transistor MN5, generating a voltage Vt-. The second-stage amplification circuit only performs a comparison when the current in the two branches of the first-stage amplification circuit exceeds the threshold voltage range of Vt+ to Vt-. Figure 6 As shown, when the second-stage amplification module does not have a threshold voltage set, power supply jitter may cause invalid comparisons, resulting in an unstable output signal. When the second-stage amplification module has a threshold voltage set, voltage differences within this range will be ignored, avoiding the adverse effects caused by power supply jitter. Figure 5 The second-stage amplification module shows that when the difference between power supplies V1 and V2 reaches the set threshold voltage, the output potentials Vd_MP5 and Vd_MP6 will change, thereby outputting the corresponding differential signal.

[0063] Furthermore, the third-stage amplification module includes two operational amplifiers. The positive input terminal of the first operational amplifier OPAMP1 is connected to the negative input terminal of the second operational amplifier OPAMP2, and is also connected to the voltage signal Vd_MP5 generated by the second-stage amplification module. The negative input terminal of the first operational amplifier OPAMP1 is connected to the positive input terminal of the second operational amplifier OPAMP2, and is also connected to the voltage signal Vd_MP6 generated by the second-stage amplification module. The first operational amplifier OPAMP1 is connected to the power supply voltage V1, and the second operational amplifier OPAMP2 is connected to the power supply voltage V2. The first operational amplifier OPAMP1 and the second operational amplifier OPAMP2 are both connected to the gate of MN10.

[0064] It should be noted that the operational amplifier adopts a structure known in the art, and operational amplifiers that can meet the basic signal comparison and amplification functions all meet the design requirements of this invention, and will not be described in detail here.

[0065] Furthermore, in the startup module, the source of MP7 is connected to power supply V1, the drain of MP7 is connected to the drain of MN11, the gate of MP7 is connected to the drain of MP7, the source of MN11 is connected to the drain of MN12, the gate of MN11 is connected to the output of the second operational amplifier OPAMP2, the source of MN12 is grounded, the gate of MN12 is connected to the output of the first operational amplifier OPAMP1, and the common terminal of the drain of MP7 and the drain of MN11 is connected to the gate of MP2.

[0066] The working principle of the startup module is as follows: when the difference between the two power supplies is small, and the signals SW_out1 and XSW_out2 output by the operational amplifier are both 1, the final output after transmission to the logic circuit is an intermediate voltage, and the system will not work properly. In the improved circuit of this invention, when both output signals SW_out1 and XSW_out2 are 1, the startup circuit is activated, the output signal V_START is pulled to zero potential, the PMOS transistor MP2 in the first-stage amplifier circuit is turned on, the current on the MP3 side increases rapidly, causing the current difference between it and the MP4 side to also increase, forcibly giving the two branches of the first-stage amplifier circuit a current difference, ultimately outputting a larger power supply voltage V1.

[0067] Figure 4 The structure of the logic circuit of the present invention is shown in the figure. The logic circuit includes an AND gate, an OR gate, an inverter, and an NMOS transistor. One input of the first AND gate AND1 is connected to the signal XSW_out1, the other input is connected to the signal XSEL1, and the output is connected to one input of the first OR gate OR1. The other input of the first OR gate OR1 is connected to the first inverter INV1. The output of the first OR gate OR1 is connected to the gate of the NMOS transistor MN15. The drain of MN15 is connected to the power supply V2. The common terminal of the source of MN15 and the source of MN16 is connected to the output terminal. The drain of MN16 is connected to the power supply V1, and the gate is connected to the output of the second OR gate OR2.

[0068] One input of the second AND gate AND2 is connected to the signal SW_out1, the other input is connected to the signal XSEL2, the output is connected to one input of the second OR gate OR2, and the other input of the second OR gate OR2 is connected to the second inverter INV2.

[0069] The first AND gate AND1, the first OR gate OR1, and the first inverter INV1 are all connected to power supply V2, while the second AND gate AND2, the second OR gate OR2, and the second inverter INV2 are all connected to power supply V1.

[0070] The working principle of this logic circuit is as follows:

[0071] When SEL1 = 0 and SEL2 = 0, SW_out2 = SW_out1 and XSW_out2 = XSW_out1, the final power supply output is the maximum value between V1 and V2;

[0072] When SEL1 = 1 and SEL2 = 0, SW_out2 = 1 and XSW_out2 = 0, the final power supply output is V1;

[0073] When SEL1 = 0 and SEL2 = 1, SW_out2 = 0 and XSW_out2 = 1, the final power supply output is V2;

[0074] When SEL1=1 and SEL2=1, SW_out2=1 and XSW_out2=1, the logic circuit is disabled. The timing of the control signals in normal operation mode and disabled mode is as follows: Figure 7 , Figure 8 As shown.

[0075] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A maximum power supply voltage selection circuit, characterized in that, The selection circuit includes an analog amplifier circuit, a logic circuit, an NMOS transistor MN13, and an NMOS transistor MN14; wherein, the analog amplifier circuit includes an amplification module and a startup module; The amplifier module is connected to power supply V1 and power supply V2 at the same time, and the output signals SW_out1 and XSW_out1 are connected to the input terminal of the start-up module and the input terminal of the logic circuit, respectively. The startup module is connected to power supply V2, and the logic circuit is connected to both power supply V1 and power supply V2. The logic circuit output signals SW_out2 and XSW_out2 are connected to the gates of NMOS transistor MN13 and NMOS transistor MN14, respectively. The drain of NMOS transistor MN13 is connected to power supply V1, the drain of NMOS transistor MN14 is connected to power supply V2, and the common terminal of the source of NMOS transistor MN13 and the source of NMOS transistor MN14 outputs the signal Vout.

2. The maximum power supply voltage selection circuit according to claim 1, characterized in that, The analog amplifier circuit includes: The bias module is used to provide the tail current source for the first-stage amplification module; The first-stage amplification module is used to convert the differential between the two power supplies into a differential current. The second-stage amplification module is used to compare the current difference and obtain two differential-mode voltage signals; The third-stage amplification module is used to amplify the two differential signals and output two completely inverted analog switching signals. The startup module is used to activate when the third-stage amplification module generates two in-phase analog signals, repeating the operation steps from the first-stage amplification module to the third-stage amplification module.

3. The maximum power supply voltage selection circuit according to claim 2, characterized in that, In the first-stage amplification module, the common terminal of the source of PMOS transistor MP2 and the source of PMOS transistor MP3 is connected to power supply V1. The common terminal of the drain of PMOS transistor MP2 and the drain of PMOS transistor MP3 is connected to the drain of NMOS transistor MN2. The gate of PMOS transistor MP3 is connected to its drain. The common terminal of the source of NMOS transistor MN2 and the source of NMOS transistor MN3 is connected to the drain of NMOS transistor MN9. The gate of NMOS transistor MN2 is connected to its drain. The source of NMOS transistor MN9 is grounded. The gate of NMOS transistor MN9 is connected to the gate of NMOS transistor MN8. The drain of NMOS transistor MN3 is connected to the drain of PMOS transistor MP4, the gate of NMOS transistor MN3 is connected to its drain, the gate of PMOS transistor MP4 is connected to its drain, and the source of PMOS transistor MP4 is connected to power supply V2.

4. The maximum power supply voltage selection circuit according to claim 2, characterized in that, In the second-stage amplification module, the source of PMOS transistor MP5 is connected to power supply V1, the gate of PMOS transistor MP5 is connected to the common terminal of the drain of PMOS transistor MP3 and the drain of NMOS transistor MN2, the drain of PMOS transistor MP5 is connected to the drain of NMOS transistor MN5, the common terminal of the source of NMOS transistor MN5 and the source of NMOS transistor MN4 is grounded, the drain of NMOS transistor MN4 is connected to the drain of NMOS transistor MN5, and the gate of NMOS transistor MN4 is connected to the common terminal of the drain of NMOS transistor MN4 and the drain of NMOS transistor MN5. The source of PMOS transistor MP6 is connected to power supply V2. The gate of PMOS transistor MP6 is connected to the gate of PMOS transistor MP4. The drain of PMOS transistor MP6 is connected to the common terminal of the drain of PMOS transistor MN6 and the drain of NMOS transistor MN7. The gate of NMOS transistor MN7 is connected to the drain of NMOS transistor MN7. The common terminal of the source of NMOS transistor MN6 and the source of NMOS transistor MN7 is grounded. The common terminal of the source of NMOS transistor MN5 and the source of NMOS transistor MN6 is connected to the drain of NMOS transistor MN10. The source of NMOS transistor MN10 is grounded. The gate of NMOS transistor MN5 is connected to the common terminal of the drain of NMOS transistor MN6 and the drain of PMOS transistor MP6. The gate of NMOS transistor MN6 is connected to the common terminal of the drain of NMOS transistor MN5 and the drain of PMOS transistor MP5.

5. The maximum power supply voltage selection circuit according to claim 4, characterized in that, The width of NMOS transistor MN6 is N times the width of NMOS transistor MN4, generating voltage Vt+. The width of NMOS transistor MN7 is N times the width of NMOS transistor MN5, generating voltage Vt-.

6. The maximum power supply voltage selection circuit according to claim 2, characterized in that, The third-stage amplification module includes two operational amplifiers. The positive input terminal of the first operational amplifier OPAMP1 is connected to the negative input terminal of the second operational amplifier OPAMP2, and is also connected to the voltage signal Vd_MP5 generated by the second-stage amplification module. The negative input terminal of the first operational amplifier OPAMP1 is connected to the positive input terminal of the second operational amplifier OPAMP2, and is also connected to the voltage signal Vd_MP6 generated by the second-stage amplification module. The first operational amplifier OPAMP1 is connected to the power supply voltage V1, and the second operational amplifier OPAMP2 is connected to the power supply voltage V2. The first operational amplifier OPAMP1 and the second operational amplifier OPAMP2 are both connected to the gate of MN10.

7. The maximum power supply voltage selection circuit according to claim 2, characterized in that, In the startup module, the source of PMOS transistor MP7 is connected to power supply V1, the drain of PMOS transistor MP7 is connected to the drain of NMOS transistor MN11, the gate of PMOS transistor MP7 is connected to the drain of PMOS transistor MP7, the source of NMOS transistor MN11 is the drain of NMOS transistor MN12, the gate of NMOS transistor MN11 is connected to the output of the second operational amplifier OPAMP2, the source of NMOS transistor MN12 is grounded, the gate of NMOS transistor MN12 is connected to the output of the first operational amplifier OPAMP1, and the common terminal of the drain of PMOS transistor MP7 and the drain of NMOS transistor MN11 is connected to the gate of PMOS transistor MP2.

8. The maximum power supply voltage selection circuit according to claim 2, characterized in that, The logic circuit includes an AND gate, an OR gate, an inverter, and an NMOS transistor. One input of the first AND gate AND1 is connected to the signal XSW_out1, the other input is connected to the signal XSEL1, and the output is connected to one input of the first OR gate OR1. The other input of the first OR gate OR1 is connected to the first inverter INV1. The output of the first OR gate OR1 is connected to the gate of the NMOS transistor MN15. The drain of MN15 is connected to the power supply V2. The common terminal of the source of MN15 and the source of MN16 is connected to the output terminal. The drain of MN16 is connected to the power supply V1, and the gate is connected to the output of the second OR gate OR2. One input of the second AND gate AND2 is connected to the signal SW_out1, the other input is connected to the signal XSEL2, the output is connected to one input of the second OR gate OR2, and the other input of the second OR gate OR2 is connected to the second inverter INV2. The first AND gate AND1, the first OR gate OR1, and the first inverter INV1 are all connected to power supply V2, while the second AND gate AND2, the second OR gate OR2, and the second inverter INV2 are all connected to power supply V1.

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