Electronic equipment capable of simultaneously upgrading on line and dynamically loading FPGA (Field Programmable Gate Array)

Abstract

The utility model discloses an electronic device simultaneously satisfying on-line upgrading and dynamic loading of FPGA, comprising a processor, an FPGA A1, an FPGA A2 and a FLASH, the processor is connected with the FPGA A1 through a PCIE interface, the FPGA A1 and the FPGA A2 are both provided with MGT high-speed interfaces and are connected with each other through the MGT high-speed interfaces, the FPGA A1 is connected with the FLASH through a Slave SelectMap loading mode, the FPGA A2 is connected with the FLASH and the FPGA A1 through a special configuration pin, and the FPGA A1 is connected with the FLASH through a special configuration pin. And the special configuration pin can be reused in a Master SPI / BPI loading mode and a Slave SelectMap loading mode. According to the utility model, the problems of single FPGA loading mode and blue screen in the FPGA program updating process in an FPGA active loading mode in the prior art are solved; and the problem that the FPGA program is inconvenient to update after the equipment is installed in the box is solved.

Description

Technical Field

[0001] This utility model relates to the field of electronic device upgrade technology, specifically, it is an electronic device that simultaneously satisfies online upgrade and dynamic FPGA loading. Background Technology

[0002] FPGA (Field Programmable Gate Array) is a programmable digital circuit whose logic circuitry can be modified and erased under relatively undemanding conditions, allowing for field programming. The flexibility and high speed of FPGAs give them significant advantages in digital signal processing, leading to their wide range of applications. Traditional FPGA loading methods typically involve using the JTAG port to burn firmware into the FLASH memory, followed by the FPGA actively loading data from the FLASH memory via BPI or SPI interfaces. This traditional single-method loading approach has several drawbacks:

[0003] First, when the device is in a confined space or enclosed environment, debugging requires updating the FPGA program. Traditional loading methods require navigating through the confined space or breaking through the enclosed environment to locate the FPGA's JTAG debug port, then burning the program into the FLASH memory, and finally having the FPGA actively load the program via the BPI or SPI interface. This process is overly cumbersome and can easily damage or affect the device.

[0004] Secondly, in digital signal processing, FPGAs typically need to be used in conjunction with CPUs, DSPs, etc. The FPGA communicates with the CPU via a PCIe interface connected to the CPU's PCIe bus. In this case, if the FPGA's loading program needs to be updated, the CPU's PCIe bus will lose this PCIe device when the FPGA is being loaded, which may cause a bus error and lead to a blue screen of death for the CPU system.

[0005] Chinese utility model patent entitled "Electronic Device Simultaneously Meeting Online Upgrade and Dynamic FPGA Loading Requirements," authorized publication number CN221827315U, discloses a solution to the aforementioned technical problem by adding FPGA2, connecting the original FPGA1 and FPGA2 via a high-speed interface, and adding a loading mode switching switch between FPGA1 and FPGA2 to switch the connection of FPGA2's dedicated configuration pins with FPGA1 or with FLASH memory. This utility model provides a new solution. Utility Model Content

[0006] The purpose of this invention is to provide an electronic device that simultaneously satisfies online upgrades and dynamic FPGA loading, in order to solve the problem that in the existing technology, the FPGA loading method commonly uses the JTAG port to burn firmware into the FLASH memory, and then the FPGA actively loads the data in the FLASH memory using the BPI or SPI interface. This method is limited by the space of the device and is prone to causing the system CPU to blue screen.

[0007] The present invention solves the above problems through the following technical solution:

[0008] An electronic device that simultaneously supports online upgrades and dynamic FPGA loading includes a processor, FPGA1, FPGA2, and FLASH. The processor is connected to FPGA1 via a PCIe interface. Both FPGA1 and FPGA2 have MGT high-speed interfaces and are interconnected through the MGT high-speed interfaces. FPGA1 is connected to the FLASH via a Slave SelectMap loading method. FPGA2 is connected to the FLASH and FPGA1 via dedicated configuration pins. These dedicated configuration pins can be reused for both Master SPI / BPI loading and Slave SelectMap loading methods.

[0009] Furthermore, the pin in FPGA1 that is connected to the dedicated configuration pin of FPGA2 is configured as an input pin when not dynamically loaded.

[0010] Furthermore, the PUDC_B pin of the FPGA1 is connected to a pull-up resistor. The PUDC_B pin is used to affect the state of the IO pins after the FPGA1 is powered on and during the configuration process of the FPGA1.

[0011] Furthermore, the PCIE interface is replaced with an SGMII interface or an RGMII interface.

[0012] Furthermore, the processor is a CPU or an APU.

[0013] Furthermore, the FPGA1 is replaced with a microprocessor or CPLD.

[0014] Compared with the prior art, this utility model has the following advantages and beneficial effects:

[0015] (1) This utility model can realize two ways of loading FPGA programs. After the logic code is burned into FPGA1 for the first time, the program of FPGA2 can be updated at any time in subsequent use. The external CPU / APU processor platform will not have a series of problems such as blue screen caused by PCIE bus failure when using PCIE interface communication.

[0016] (2) This utility model does not require disassembling the chassis to use the JTAG port or finding additional debugging tools such as emulators, making the operation more convenient and time-saving.

[0017] (3) This utility model only uses the conventional interface resources of FPGA, without additional components, making the design simpler and the cost more controllable. Attached Figure Description

[0018] Figure 1 This is the circuit schematic diagram of this utility model. Detailed Implementation

[0019] The present invention will be further described in detail below with reference to the embodiments, but the implementation of the present invention is not limited thereto.

[0020] Example:

[0021] Combined with appendix Figure 1 As shown, an electronic device that simultaneously satisfies online upgrades and dynamic FPGA loading includes a processor (such as a CPU / APU / DSP), FPGA1, FPGA2, and FLASH. The processor and FPGA1 are connected via interfaces such as PCIE / SGMII / RGMII. FPGA1 and the dynamically loaded or online upgraded FPGA2 both have MGT high-speed interfaces and are interconnected through the MGT high-speed interfaces. FPGA1 is connected to the FLASH via the Slave SelectMap loading method. FPGA2 is connected to the FLASH and FPGA1 via dedicated configuration pins. These dedicated configuration pins can be reused for both Master SPI / BPI loading methods and Slave SelectMap loading methods.

[0022] Working principle:

[0023] In typical digital signal processing equipment, an FPGA2 is used in conjunction with a CPU / DSP to perform signal encoding, decoding, modulation, and demodulation. The FPGA2 and CPU transmit large amounts of data at high speed via a PCIe port. This invention adds an FPGA1 because the dedicated interfaces required for FPGA2's self-loading from FLASH and loading from FPGA1 can be reused and connected in parallel. Therefore, no additional components are needed between FPGA1 and the traditionally designed FPGA2; only the MGT high-speed interface for online upgrades and the GPIO interface (i.e., dedicated configuration pins) for dynamic loading need to be added during the hardware design.

[0024] Data flow in dynamically loaded SelectMap mode: The logic bit file that needs to be updated is handled by host computer software within the CPU operating system. Data from the host computer is first transmitted to the FPGA1 cache via the high-speed PCIe interface between the CPU and FPGA1. Then, FPGA1 controls the loading of FPGA2 via the GPIO interface connected to the dedicated SelectMap mode interface of FPGA2. In this design, FPGA1 is only used to load FPGA2 and does not perform signal processing or other business functions. Therefore, FPGA1 does not need frequent program updates. The program is fixed before the chassis is installed and is generally not easily changed, thus avoiding blue screens when updating the FPGA2 program.

[0025] The data flow for online upgrades is as follows: The necessary updates to the fixed logic MCS / BIN file are performed via host computer software within the CPU operating system. Data from the host computer is first transmitted to the FPGA1 cache via the high-speed PCIe interface between the CPU and FPGA1. FPGA1 and FPGA2 are interconnected via a high-speed MGT interface, through which FPGA1 transmits data to FPGA2. Then, FPGA2 writes the data into the FLASH memory via the BPI / QSPI interface. During the data writing process, FPGA2 checks and reads back the data in the FLASH memory. By reading the data status in the FLASH, it determines whether the upgrade is complete. FPGA2 then transmits the status to FPGA1 via the high-speed interconnection interface, and FPGA1 reports it to the host computer. When FPGA2 performs a self-booting automatic load, it loads the data stored in the FLASH memory again via the BPI / QSPI interface. This method ensures data integrity even when power is lost.

[0026] This invention does not improve the loading method, upgrade method, or loading mode itself. Instead, it utilizes existing methods and solves the problems of single FPGA loading mode and blue screen during FPGA program update in the prior art by using the connection method of FPGA1, PGA2, and FLASH and the reuse of dedicated configuration pins of PFGA2. It also solves the problem of inconvenience in updating FPGA program after the device is installed in the chassis.

[0027] Detailed design specifications for reusable pins:

[0028] Online upgrades primarily refer to directly embedding the required logic program into the target FPGA2's FLASH memory chip via the operating system. This ensures that the target FPGA2 can automatically load the updated logic program into the FLASH memory after a power outage or reset via Master SPI / Master BPI. Dynamic loading refers to the target FPGA2 being dynamically loaded with the required logic program by a newly added FPGA1 / CPLD or microprocessor via Slave SelectMap. Because Master SPI / Master BPI and Slave SelectMap share the same dedicated pins for FPGA2, pin reuse can be implemented for different loading methods.

[0029] In the hardware design, the PUDC_B pin of FPGA1 is pulled up to ensure that all pins of FPGA1 are in a high-impedance state during initialization and loading. The configuration pin of FPGA2 is connected to FPGA1 and pulled up or down to the Master SPI / Master BPI loading mode. Since the physical state of the high-impedance pin of FPGA1 does not affect the level attributes of external signals, FPGA2 will not be affected in reading data from the FLASH from the multiplexed pin when FPGA1 and FPGA2 are powered on simultaneously. In the logic design, the pins connected to the dedicated pins configured in the Slave SelectMap of FPGA1 and FPGA2 are configured as inputs during non-dynamic loading, and then FPGA2 is actively reset after FPGA1 finishes loading. This ensures that even if FPGA1 loads before FPGA2 when powered on simultaneously, it will not affect the self-starting of FPGA2.

[0030] This invention provides two methods for loading FPGA programs. After the initial logic code is programmed onto FPGA1, subsequent updates to the FPGA2 program will not cause blue screen errors or other problems when using the PCIe interface for communication with an external CPU / APU. Updating the FPGA2 program can be done via SelectMap mode or online upgrade mode, eliminating the need to disassemble and locate the device's JTAG port, making the operation more convenient and time-saving.

[0031] Although the present invention has been described herein with reference to illustrative embodiments, the above embodiments are merely preferred embodiments of the present invention, and the implementation of the present invention is not limited to the above embodiments. It should be understood that those skilled in the art can design many other modifications and implementations, which will fall within the scope and spirit of the principles disclosed in this application.

Claims

1. An electronic device that simultaneously satisfies online upgrades and dynamic FPGA loading, comprising a processor, FPGA1, FPGA2, and FLASH, characterized in that, The processor is connected to FPGA1 via a PCIe interface. Both FPGA1 and FPGA2 have MGT high-speed interfaces and are interconnected through the MGT high-speed interface. FPGA1 is connected to the FLASH via Slave SelectMap loading mode. FPGA2 is connected to the FLASH and FPGA1 via dedicated configuration pins. The dedicated configuration pins can be reused for Master SPI / BPI loading mode and Slave SelectMap loading mode.

2. An electronic device that simultaneously satisfies online upgrade and dynamic FPGA loading according to claim 1, characterized in that, The pins in FPGA1 that are connected to the dedicated configuration pins of FPGA2 are configured as input pins when not dynamically loaded.

3. An electronic device that simultaneously satisfies online upgrade and dynamic FPGA loading according to claim 2, characterized in that, The PUDC_B pin of FPGA1 is connected to a pull-up resistor. The PUDC_B pin is used to affect the state of the IO pins after FPGA1 is powered on and during the configuration process of FPGA1.

4. An electronic device that simultaneously satisfies online upgrade and dynamic FPGA loading according to claim 1, characterized in that, The PCIE interface is replaced with an SGMII interface or an RGMII interface.

5. An electronic device that simultaneously satisfies online upgrade and dynamic FPGA loading according to claim 1, characterized in that, The processor is either a CPU or an APU.

6. An electronic device that simultaneously satisfies online upgrade and dynamic FPGA loading according to claim 1, characterized in that, The FPGA1 is replaced with a microprocessor or CPLD.

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