Planar transformer
By introducing a second via in the planar transformer, the current transmission path of the intermediate capacitor is enhanced, which solves the problem of uneven current distribution during miniaturization and ensures the working performance of the device.
Patent Information
- Application Number
- CN202422558435.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-22
- Publication Date
- 2025-10-31
- Estimated Expiration
- 2034-10-22
AI Technical Summary
During the miniaturization process of planar transformers, the overcurrent capacity of the intermediate capacitor is limited, resulting in uneven current distribution, which may damage the capacitors at both ends.
Introducing a second via into the planar transformer allows the intermediate capacitor to be electrically connected to the third output port through the second via, providing more current transmission paths and enhancing the overcurrent capability of the intermediate capacitor.
When the current is large, the current balance is ensured, avoiding the problem of the capacitors at both ends being damaged due to excessive current, and maintaining the working performance of the device.
Smart Images
Figure CN223501667U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of planar transformer technology, and more particularly to a planar transformer. Background Technology
[0002] With the miniaturization and cost reduction of modern electronic devices, the switching power supplies inside these devices are constantly evolving towards lighter, thinner, smaller, and higher-frequency designs. As a key component of switching power supplies, the size of the transformer significantly impacts the overall size of the power supply. Traditional high-frequency transformers are relatively large and require sophisticated winding processes.
[0003] A planar transformer is a type of transformer with high frequency Transformers, characterized by their small size and low profile, are typically constructed using a PCB board with copper-clad traces as windings and a corresponding magnetic core. Using copper-clad traces on a PCB as windings effectively achieves size reduction, making planar transformers crucial for the miniaturization of electronic devices. However, the increasing miniaturization of planar transformers also impacts the performance of devices mounted on them. Therefore, maintaining or even improving the performance of devices mounted on planar transformers while miniaturizing them has become a key focus for those skilled in the art. Utility Model Content
[0004] In view of this, this application provides a planar transformer, the scheme of which is as follows:
[0005] A planar transformer includes: a multilayer circuit board and a magnetic core. The multilayer circuit board includes a bottom circuit board, a top circuit board, and N layers of winding circuit boards stacked between the bottom circuit board and the top circuit board, where N ≥ 3. The multilayer circuit board has a first via through which the first via penetrates the multilayer circuit board, and the magnetic core is disposed in the first via.
[0006] The surface of the underlying circuit board has a first capacitor, a second capacitor, and at least one intermediate capacitor between the first capacitor and the second capacitor; the underlying circuit board also has a first output port and a second output port, the first capacitor is electrically connected to the first output port, the second capacitor is electrically connected to the second output port, and the intermediate capacitor is electrically connected to at least one of the first output port and the second output port.
[0007] The N-layer winding circuit board includes a first winding circuit board with a third output port. The multilayer circuit board also has a second via, and the intermediate capacitor is electrically connected to the third output port through the second via.
[0008] Optionally, the surface of the bottom circuit board has a first metal layer and a second metal layer arranged along a first direction, and the first metal layer and the second metal layer extend along a second direction; the first metal layer and the second metal layer constitute the first capacitor, the second capacitor and the intermediate capacitor; the first output port and the second output port are respectively disposed at both ends of the first metal layer;
[0009] The first direction extends from the edge of the multilayer circuit board toward its inner side and is parallel to the mounting surface of the multilayer circuit board. The second direction is perpendicular to the first direction and parallel to the mounting surface of the multilayer circuit board.
[0010] Optionally, the second via includes a first sub-via and a second sub-via, the first sub-via penetrating the first metal layer, the second sub-via penetrating the N-layer winding circuit board, and the intermediate capacitor being electrically connected to the third output port in sequence through the first sub-via and the second sub-via.
[0011] Optionally, the first capacitor includes a first sub-capacitor and a second sub-capacitor, the second capacitor includes a third sub-capacitor and a fourth sub-capacitor, and the at least one intermediate capacitor includes at least one first intermediate capacitor and at least one second intermediate capacitor, the first intermediate capacitor being located between the first sub-capacitor and the third sub-capacitor, and the second intermediate capacitor being located between the second sub-capacitor and the fourth sub-capacitor.
[0012] The first metal layer includes a first sub-metal layer and a second sub-metal layer, and the second metal layer includes a third sub-metal layer and a fourth sub-metal layer. The first sub-metal layer and the third sub-metal layer are arranged along the first direction and located on a first side of the multilayer circuit board. The second sub-metal layer and the fourth sub-metal layer are arranged along the first direction and located on a second side of the multilayer circuit board. The first side and the second side are opposite to each other and are located on both sides of the axis of the multilayer circuit board. The extension direction of the axis is parallel to the mounting surface of the multilayer circuit board. The first sub-metal layer and the third sub-metal layer constitute a first sub-capacitor, a third sub-capacitor, and a first intermediate capacitor. The second sub-metal layer and the fourth sub-metal layer constitute a second sub-capacitor, a fourth sub-capacitor, and a second intermediate capacitor.
[0013] The first output port includes a first sub-output port and a second sub-output port, and the second output port includes a third sub-output port and a fourth sub-output port. The first sub-output port and the third sub-output port are respectively disposed at both ends of the first sub-metal layer, and the second sub-output port and the fourth sub-output port are respectively disposed at both ends of the second sub-metal layer.
[0014] Optionally, the at least one first intermediate capacitor includes three first intermediate capacitors, the at least one second intermediate capacitor includes three second intermediate capacitors, and the second via includes three first sub-vias and three second sub-vias located on the first side, as well as three first sub-vias and three second sub-vias located on the second side; wherein, the first intermediate capacitor is electrically connected to the third output port in sequence through the first sub-vias and second sub-vias located on the first side, and the second intermediate capacitor is electrically connected to the third output port in sequence through the first sub-vias and second sub-vias located on the second side.
[0015] Optionally, the third output port includes a first sub-output port located on the first side and a second sub-output port located on the second side, wherein the second sub-via located on the first side is electrically connected to the first sub-output port, and the second sub-via located on the second side is electrically connected to the second sub-output port.
[0016] Optionally, the first via includes four third sub-vias arranged in a matrix, the magnetic core includes a first magnetic sheet and a second ceramic sheet, the first magnetic sheet includes four first magnetic pillars, the second magnetic sheet includes four second magnetic pillars, the four first magnetic pillars correspond one-to-one with the four third sub-vias, the four second magnetic pillars correspond one-to-one with the four third sub-vias, and the first magnetic pillars and the second magnetic pillars are connected in the third sub-vias.
[0017] Optionally, N=6, and the N-layer winding circuit board includes a second winding circuit board, a third winding circuit board, a fourth winding circuit board, a fifth winding circuit board, a sixth winding circuit board, and a first winding circuit board stacked sequentially. The second winding circuit board is adjacent to the bottom circuit board, and the first winding circuit board is adjacent to the top circuit board. The first winding circuit board has a first secondary winding, the second winding circuit board has a second secondary winding, the third and sixth winding circuit boards have primary windings, and the fourth and fifth winding circuit boards have a third secondary winding. The second winding circuit board has a fourth output port, and the fourth and fifth winding circuit boards have a fifth output port.
[0018] The multilayer circuit board also has a third via distributed around the first via, the third via penetrating the multilayer circuit board, including a fourth sub-via and a fifth sub-via. One end of the first secondary winding is electrically connected to the fourth sub-via, and the other end is electrically connected to the fourth output port or the fifth output port through the fifth sub-via. The third via also includes a sixth sub-via, one end of the second secondary winding is electrically connected to the sixth sub-via, and the other end is electrically connected to the fourth output port. The third via also includes a seventh sub-via, one end of the third secondary winding is electrically connected to the seventh sub-via, and the other end is electrically connected to the fifth output port.
[0019] The multilayer circuit board also includes a fourth via located on the third side, which is located between the first side and the second side. The fourth via includes an eighth sub-via and a ninth sub-via. One end of the primary winding is electrically connected to the eighth sub-via, and the other end is electrically connected to the ninth sub-via.
[0020] Optionally, the primary winding includes a first primary winding and a second primary winding. The first primary winding is arranged around any two of the four third sub-vias, and the second primary winding is arranged around the remaining two third sub-vias.
[0021] The first secondary winding, the second secondary winding, and the third secondary winding are arranged around each third sub-via, and the current directions of the first secondary winding and the second secondary winding are the same, while the current directions of the first secondary winding and the third secondary winding are opposite.
[0022] Optionally, the eighth sub-via includes the tenth sub-via and the eleventh sub-via, and the ninth sub-via includes the twelfth sub-via and the thirteenth sub-via. One end of the first primary winding is electrically connected to the tenth sub-via and the other end is electrically connected to the twelfth sub-via. One end of the second primary winding is electrically connected to the eleventh sub-via and the other end is electrically connected to the thirteenth sub-via.
[0023] Compared with the prior art, the beneficial effects of the technical solution of this application are as follows:
[0024] The planar transformer includes a multilayer circuit board and a magnetic core. The multilayer circuit board includes a bottom circuit board, a top circuit board, and N winding circuit boards stacked between the bottom and top circuit boards, where N ≥ 3. The multilayer circuit board has a first via, and the magnetic core is disposed in the first via. The surface of the bottom circuit board has a first capacitor, a second capacitor, and at least one intermediate capacitor between the first and second capacitors. The bottom circuit board also has a first output port and a second output port. The first capacitor is electrically connected to the first output port, the second capacitor is electrically connected to the second output port, and the intermediate capacitor is electrically connected to at least one of the first and second output ports. The N-layer winding circuit board includes a first winding circuit board with a third output port. The multilayer circuit board also has a second via, and the intermediate capacitor is also electrically connected to the third output port through the second via. As described above, compared to related technologies, the planar transformer provided in this application has a second via, allowing the intermediate capacitor to be electrically connected not only to at least one of the first and second output ports on the underlying circuit board, but also to a third output port via the second via. This provides the intermediate capacitor with more current transmission paths, effectively increasing its overcurrent capacity. Consequently, it ensures balanced current flow through the capacitors when the current is high, suppressing uneven current distribution. Furthermore, the enhanced overcurrent capacity of the intermediate capacitor effectively prevents damage caused by excessive current carrying by the two capacitors (i.e., the first and second capacitors) when the current is high. Attached Figure Description
[0025] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments or prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.
[0026] The structures, proportions, sizes, etc., shown in the accompanying drawings are only for the purpose of assisting those skilled in the art in understanding and reading the content disclosed in the specification, and are not intended to limit the implementation conditions of this application. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportions, or adjustments to the size should still fall within the scope of the technical content disclosed in this application, provided that they do not affect the effects and purposes that this application can produce.
[0027] Figure 1 This is a schematic diagram of the structure of a planar transformer in the prior art;
[0028] Figure 2A cross-sectional view of a planar transformer provided in this application;
[0029] Figure 3 This application provides a schematic diagram of the structure of a planar transformer;
[0030] Figure 4 A schematic diagram of another planar transformer provided in this application;
[0031] Figure 5 A schematic diagram of the structure of another planar transformer provided in this application;
[0032] Figure 6 A cross-sectional view of another planar transformer provided in this application;
[0033] Figure 7 A cross-sectional view of yet another planar transformer provided in this application;
[0034] Figure 8 A schematic diagram of the structure of another planar transformer provided in this application;
[0035] Figure 9 A schematic diagram of the structure of another planar transformer provided in this application;
[0036] Figure 10 A schematic diagram of the structure of another planar transformer provided in this application;
[0037] Figure 11 This is a schematic diagram of another planar transformer provided in this application. Detailed Implementation
[0038] The embodiments of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are merely one area of this application, and not all of the embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.
[0039] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments.
[0040] As described in the background section, the increasingly miniaturized planar transformers also experience reduced performance of their components due to their smaller size. Specifically, for example... Figure 1 As shown, Figure 1The circuit board layer shown can be the top or bottom layer of a multilayer circuit board. For example, the bottom layer circuit board contains multiple capacitors A. Among these capacitors A1, the two end capacitors A1 can be directly electrically connected to the output port B through copper pours on the bottom layer circuit board, and can also be electrically connected to adjacent copper layers through numerous vias C, exhibiting a large current carrying capacity. However, the middle capacitor A2 can only be electrically connected to the output port B through copper pours on the bottom layer circuit board, and its current carrying capacity is affected by the width of the copper pour. Due to the miniaturization of planar transformers, the copper pour width is also limited, further restricting the current carrying capacity of the middle capacitor. Therefore, when the current continuously increases, or becomes excessively high, it leads to uneven current distribution and causes the two end capacitors A1 to bear a large current, resulting in damage to capacitor A1.
[0041] Based on the above, this application provides a planar transformer, such as... Figure 2 As shown, the planar transformer includes a multilayer circuit board 100 and a magnetic core 200. The multilayer circuit board 100 includes a bottom circuit board 110, a top circuit board 120, and N layers of winding circuit boards 130 stacked between the bottom circuit board 110 and the top circuit board 120, where N ≥ 3. Furthermore, the multilayer circuit board 100 has a first via 310 that penetrates the multilayer circuit board 100, and the magnetic core 200 is disposed within the first via 310, i.e., the magnetic core 200 is disposed through the first via 310. It should be noted that, as the name suggests, the winding circuit board 130 has copper-clad traces laid on it as windings.
[0042] like Figure 3 As shown, the surface of the aforementioned bottom circuit board 110 has a first capacitor C1, a second capacitor C2, and at least one intermediate capacitor C3 located between the first capacitor C1 and the second capacitor C2. The bottom circuit board 110 also has a first output port 101 and a second output port 102. The first capacitor C1 is electrically connected to the first output port 101, the second capacitor C2 is electrically connected to the second output port 102, and the intermediate capacitor C3 is electrically connected to at least one of the first output port 101 and the second output port 102. Specifically, the first capacitor C1 is electrically connected to the first output port 101 through copper pouring of the bottom circuit board 110, the second capacitor C2 is also electrically connected to the second output port 102 through copper pouring of the bottom circuit board 110, and the intermediate capacitor C3 is electrically connected to the first output port 101 through copper pouring of the bottom circuit board 110, or the intermediate capacitor C3 is electrically connected to the second output port 102 through copper pouring of the bottom circuit board 110, or the intermediate capacitor C3 is electrically connected to both the first output port 101 and the second output port 102 through copper pouring of the bottom circuit board 110. It should be noted that the surface of the bottom circuit board 110 is the same as the surface of the bottom circuit board 110 facing the top circuit board 120, and will not be described again below.
[0043] like Figure 4 As shown, the above-mentioned N-layer winding circuit board 130 includes a first winding circuit board 131, which has a third output port 103. The multilayer circuit board 100 also has a second via 320. The above-mentioned intermediate capacitor C3 is also electrically connected to the third output port 103 through the second via 320. Specifically, the intermediate capacitor C3 is electrically connected to the third output port 103 through the second via and the copper pour of the first winding circuit board 131.
[0044] As described above, compared to related technologies, the planar transformer provided in this application is equipped with a second via 102, allowing the intermediate capacitor C3 to be electrically connected not only to at least one of the first output ports 101 and 102 on the bottom circuit board 110, but also to the third output port 103 via the second via 320. This provides more current transmission paths for the intermediate capacitor C3, effectively increasing its overcurrent capacity. This ensures a more balanced current flow through the capacitors when the current is high, suppressing uneven current distribution. Furthermore, the enhanced overcurrent capacity of the intermediate capacitor C3 effectively prevents damage caused by excessive current carrying by the capacitors at both ends (i.e., the first capacitor C1 and the second capacitor C2) when the current is high. Therefore, the planar transformer provided in this application, while minimizing its size, still maintains the overcurrent capacity of its capacitors, thus contributing to the performance of the devices on it.
[0045] Based on the foregoing embodiments, in one embodiment of this application, such as Figure 3As shown, the surface of the bottom circuit board 110 has a first metal layer 111 and a second metal layer 112 arranged along a first direction. The first metal layer 111 and the second metal layer 112 extend along a second direction, forming a first capacitor C1, a second capacitor C2, and an intermediate capacitor C3. A first output port 101 and a second output port 102 are respectively disposed at both ends of the first metal layer 101. The first direction extends from the edge of the multilayer circuit board 100 inwards and is parallel to the mounting surface of the multilayer circuit board 100. The second direction is perpendicular to the first direction and parallel to the mounting surface of the multilayer circuit board 100. It should be noted that the multilayer circuit board 100 is known to be composed of a bottom circuit board 110, a winding circuit board 130, and a top circuit board 120 stacked together. Therefore, the mounting planes of the bottom circuit board 110, the winding circuit board 130, and the top circuit board 120 are all parallel, and all parallel to the mounting plane of the multilayer circuit board 100. That is to say, the first metal layer 111 is located at the edge of the bottom circuit board 110, while the second metal layer 112 is located closer to the inside of the bottom circuit board 110 relative to the first metal layer 111. It should also be noted that the first metal layer 111 and the second metal layer 112 are also formed by copper pouring. Therefore, the first output port 101 and the second output port 102 are respectively located at both ends of the first metal layer 111, which allows the first capacitor C1, the second capacitor C2, and the intermediate capacitor C3 to be electrically connected to the first output port 101 and the second output port 102 through copper pouring. It should be noted that the arrangement direction of the first capacitor C1, the intermediate capacitor C3, and the second capacitor C2 is parallel to the extension direction of the first metal layer 111 and the second metal layer 112, that is, the arrangement direction of the first capacitor C1, the intermediate capacitor C3, and the second capacitor C2 is parallel to the second direction.
[0046] Based on the foregoing embodiments, in one embodiment of this application, the following continues... Figure 3 As shown, the second via 320 includes a first sub-via 321 and a second sub-via 322. The first sub-via 321 penetrates the first metal layer 111, and the second sub-via 322 penetrates the N-layer winding circuit board 130. The intermediate capacitor C3 is electrically connected to the third output port 103 through the first sub-via 321 and the second sub-via 322 in sequence, thereby realizing the electrical connection of the intermediate capacitor C3 to the third output port 103 through the second via 320. It should be noted that... Figure 3 The first sub-via 321 and the second sub-via 322 in the diagram are only schematic diagrams. The specific layout and number of the first sub-via 321 and the second sub-via 322 are not limited.
[0047] Based on the foregoing embodiments, in one embodiment of this application, such as Figure 5As shown, the first capacitor C1 includes a first sub-capacitor C11 and a second sub-capacitor C12, the second capacitor C2 includes a third sub-capacitor C21 and a fourth sub-capacitor C22, and the at least one intermediate capacitor C3 includes at least one first intermediate capacitor C31 and at least one second intermediate capacitor C32, wherein the first intermediate capacitor C31 is located between the first sub-capacitor C11 and the third sub-capacitor C21, and the second intermediate capacitor C32 is located between the second sub-capacitor C12 and the fourth sub-capacitor C22.
[0048] Based on the above, in this embodiment of the application, the first metal layer 111 includes a first sub-metal layer 1111 and a second sub-metal layer 1112, and the second metal layer 112 includes a third sub-metal layer 1121 and a fourth sub-metal layer 1122. Specifically, the first sub-metal layer 1111 and the third sub-metal layer 1121 are arranged sequentially along the first direction, and the first sub-metal layer 1111 and the third sub-metal layer 1121 are located on the first side 11 of the multilayer circuit board 100. The second sub-metal layer 1112 and the fourth sub-metal layer 1122 are arranged sequentially along the first direction, and the second sub-metal layer 1112 and the fourth sub-metal layer 1122 are located on the second side 12 of the multilayer circuit board 100. The first side 11 and the second side 12 are opposite to each other and are located on both sides of the axis 1 of the multilayer circuit board 100. The extension direction of the axis 1 of the multilayer circuit board 100 is parallel to the mounting surface of the multilayer circuit board 100. Thus, the first sub-metal layer 1111 and the second sub-metal layer 1112 are symmetrically distributed along the axis 1 in the bottom circuit board 110, and the third sub-metal layer 1121 and the fourth sub-metal layer 1122 are symmetrically distributed along the axis 1 in the bottom circuit board 110. Based on this, the first sub-metal layer 1111 and the third sub-metal layer 1121 constitute the first sub-capacitor C11, the first intermediate capacitor C31 and the third sub-capacitor C21, and the second sub-metal layer 1112 and the fourth sub-metal layer 1122 constitute the second sub-capacitor C12, the second intermediate capacitor C32 and the fourth sub-capacitor C22.
[0049] Accordingly, in this embodiment, the first output port 101 may include a first sub-output port 1011 and a second sub-output port 1012, and the second output port 102 may include a third sub-output port 1021 and a fourth sub-output port 1022. The first sub-output port 1011 and the third sub-output port 1021 are respectively disposed at both ends of the first sub-metal layer 1111, and the second sub-output port 1012 and the fourth sub-output port 1022 are respectively disposed at both ends of the second sub-metal layer 1112. Thus, the first sub-capacitor C11 and the third sub-capacitor C21 can be electrically connected to the first sub-output port 1011 and the third sub-output port 1021, respectively, and the second sub-capacitor C12 and the fourth sub-capacitor C22 can be electrically connected to the second sub-output port 1012 and the fourth sub-output port 1022, respectively. It should be noted that the area of the first sub-metal layer 1111 corresponding to the first sub-capacitor C11 has a through hole (not shown in the figure) to electrically connect the first sub-capacitor C11 to the metal layer of the adjacent circuit board. Similarly, the area of the second sub-metal layer 1112 corresponding to the second sub-capacitor C12 has a through hole to electrically connect the second sub-capacitor C12 to the metal layer of the adjacent circuit board.
[0050] Based on the foregoing embodiments, in one embodiment of this application, the following continues... Figure 5 As shown, the aforementioned at least one first intermediate capacitor C31 includes three first intermediate capacitors C31, and the aforementioned at least one second intermediate capacitor C32 includes three second intermediate capacitors C32. Correspondingly, the second via 320 includes three first sub-vias 321 and three second sub-vias 322 located on the first side 11, and the second via 320 also includes three first sub-vias 321 and three second sub-vias 322 located on the second side 12. In this configuration, a first intermediate capacitor C31 corresponds to a first sub-via 321 and a second sub-via 322 located on the first side 11. That is, a first intermediate capacitor C31 corresponds to a pair of first sub-vias 321 and second sub-vias 322 located on the first side, so that the first intermediate capacitor C31 is electrically connected to the third output port 103 in sequence through the pair of first sub-vias 321 and second sub-vias 322 located on the first side 11. Similarly, a second intermediate capacitor C32 corresponds to a pair of first sub-vias 321 and second sub-vias 322 located on the second side 12, so that the second intermediate capacitor C32 is electrically connected to the third output port 103 in sequence through the pair of first sub-vias 321 and second sub-vias 322 located on the second side 12.
[0051] Based on the foregoing embodiments, in one embodiment of this application, such as Figure 4As shown, the third output port 103 includes a first sub-output port 1031 located on the first side 11 and a second sub-output port 1032 located on the second side 12. The second sub-via 322 located on the first side 11 is electrically connected to the first sub-output port 1031, and the second sub-via 322 located on the second side 12 is electrically connected to the second sub-output port 1032. Thus, the first intermediate capacitor C31 located on the first side 11 is electrically connected to the first sub-output port, and the second intermediate capacitor C32 located on the second side 12 is electrically connected to the second sub-output port 1032. In other words, the intermediate capacitor C3 located on the first side 11 and the intermediate capacitor C3 located on the second side 12 can both be electrically connected to their respective output ports, providing more current paths for the intermediate capacitor C3.
[0052] Based on the foregoing embodiments, in one embodiment of this application, such as Figure 6 As shown, the first via 310 includes four third sub-vias 311 arranged in a matrix. The magnetic core 200 includes a first magnetic sheet 210 and a second magnetic sheet 220. Corresponding to the four third sub-vias 311, the first magnetic sheet 210 includes four first magnetic pillars 211 arranged in a matrix, and the second magnetic sheet 220 includes four second magnetic pillars 221 arranged in a matrix. The four first magnetic pillars 211 correspond one-to-one with the four third sub-vias 311 and are embedded in the third sub-vias 311. The four second magnetic pillars 221 correspond one-to-one with the four third sub-vias 311 and are embedded in the third sub-vias 311. The four first magnetic pillars 211 and the four second magnetic pillars 221 are connected in the third sub-vias 311 so that the first magnetic sheet 210 and the second magnetic sheet 220 are sandwiched to form a closed magnetic circuit, and the formed closed magnetic circuit passes through the four third sub-vias 311. It should be noted that, in order for the first magnetic sheet 210 and the second magnetic sheet 220 to be sandwiched in the four third sub-vias 311, the diameter of the third sub-vias 311 is slightly larger than the diameter of the first magnetic post 211 and the second magnetic post 221. It should also be noted that the number of the aforementioned third sub-vias 311 does not have to be four. That is, assuming the number of first magnetic posts 211 and second magnetic posts 221 is the same, in other embodiments of this application, the number of first magnetic posts 211 and second magnetic posts 221 does not have to be four, but not less than two, depending on the specific circumstances. Furthermore, the shapes of the aforementioned first magnetic sheet 210 and second magnetic sheet 220 can be the same or different, depending on the specific circumstances.
[0053] Based on the foregoing embodiments, in one embodiment of this application, such as Figure 7As shown, N=6, meaning the N-layer winding circuit board 130 has 6 layers. The N-layer winding circuit board 130 includes a second winding circuit board 132, a third winding circuit board 133, a fourth winding circuit board 134, a fifth winding circuit board 135, a sixth winding circuit board 136, and the aforementioned first winding circuit board 131. The second winding circuit board 132 is adjacent to the bottom circuit board 110, and the first winding circuit board 131 is adjacent to the top circuit board 120. In other words, the multi-layer circuit board 100 includes the bottom circuit board 110, the second winding circuit board 132, the third winding circuit board 133, the fourth winding circuit board 134, the fifth winding circuit board 135, the sixth winding circuit board 136, the first winding circuit board 131, and the top circuit board 120, which are stacked from bottom to top. The first winding circuit board 131 has a first secondary winding 1311, the second winding circuit board 132 has a second secondary winding 1321, the third winding circuit board 133 and the sixth winding circuit board 136 have primary windings, specifically the third winding circuit board 133 and the sixth winding circuit board 136 have primary windings 1331 and 1361 respectively, the fourth winding circuit board 134 and the fifth winding circuit board 135 have third secondary windings, specifically the fourth winding circuit board 134 and the fifth winding circuit board 135 have third secondary windings 1341 and 1351 respectively, and the second winding circuit board 132 has a fourth output port 104, and the fourth winding circuit board 134 has a fifth output port 105.
[0054] Based on the above, the multilayer circuit board 100 also has third vias 330 distributed around the first via 310, which penetrate the multilayer circuit board 100. For example... Figure 8 As shown, the third via 330 includes a fourth sub-via 331 and a fifth sub-via 332. One end of the first secondary winding 1311 is electrically connected to the fourth sub-via 331, and the other end is electrically connected to the fourth output port 104 or the fifth output port 105 through the fifth sub-via 332, thereby forming a path for the first secondary winding 1311. Figure 9 As shown, the third via 330 also includes a sixth sub-via 333. One end of the second secondary winding 1321 is electrically connected to the sixth sub-via 333, and the other end is electrically connected to the fourth output port 104 to form a path for the second secondary winding 1321. Figure 10As shown, the third via 330 also includes a seventh sub-via 334. One end of the third secondary winding (including the third secondary winding 1341 located on the fourth winding circuit board 134 and the third secondary winding 1351 located on the fifth winding circuit board 135) is electrically connected to the seventh sub-via 334, and the other end is electrically connected to the fifth output port 105 to form a path for the third secondary winding. It should be noted that the electrical connection between the third via through the multilayer circuit board 100 and different layers is well known to those skilled in the art and will not be described in detail here.
[0055] Based on the above, such as Figure 11 As shown, the multilayer circuit board 100 also includes a fourth via 340 located on the third side 13, wherein the third side 13 is located between the first side 11 and the second side 12. Specifically, the third side 13 is connected to the first side 11 and also connected to the second side 12, and is located between the first side 11 and the second side 12. The fourth via 340 includes an eighth sub-via 341 and a ninth sub-via 342. One end of the primary winding (including the primary winding 1331 on the third winding circuit board 133 and the primary winding 1361 on the sixth winding circuit board 136) is electrically connected to the eighth sub-via 341, and the other end is electrically connected to the ninth sub-via 342 to form a passage for the primary winding.
[0056] Based on the foregoing embodiments, in one embodiment of this application, the following continues... Figure 11 As shown, the primary winding includes a first primary winding 501 and a second primary winding 502. The first primary winding 501 is arranged around any two of the four third sub-vias 311, and the second primary winding 502 is arranged around the other two third sub-vias 311.
[0057] The first secondary side winding 1311, the second secondary side winding 1321, and the third secondary side winding are all arranged around each third sub-via 311, and the current direction of the first secondary side winding 1311 and the second secondary side winding 1321 is the same, while the current direction of the first secondary side winding 1311 and the third secondary side winding is opposite.
[0058] Based on the foregoing embodiments, in one embodiment of this application, the following continues... Figure 11 As shown, the eighth sub-via 341 includes the tenth sub-via 3411 and the eleventh sub-via 3412, and the ninth sub-via 342 includes the twelfth sub-via 3421 and the thirteenth sub-via 3422. One end of the first primary winding 501 is electrically connected to the tenth sub-via 3411, and the other end is electrically connected to the twelfth sub-via 3412. One end of the second primary winding 502 is electrically connected to the eleventh sub-via 3421, and the other end is electrically connected to the thirteenth sub-via 3422.
[0059] In summary, this application provides a planar transformer, comprising: a multilayer circuit board and a magnetic core. The multilayer circuit board includes a bottom circuit board, a top circuit board, and N layers of winding circuit boards stacked between the bottom and top circuit boards, where N ≥ 3. The multilayer circuit board has a first via, and the magnetic core is disposed in the first via. The surface of the bottom circuit board has a first capacitor, a second capacitor, and at least one intermediate capacitor between the first and second capacitors. The bottom circuit board also has a first output port and a second output port. The first capacitor is electrically connected to the first output port, the second capacitor is electrically connected to the second output port, and the intermediate capacitor is electrically connected to at least one of the first and second output ports. The N-layer winding circuit board includes a first winding circuit board, which has a third output port. The multilayer circuit board also has a second via, and the intermediate capacitor is also electrically connected to the third output port through the second via. As described above, compared to related technologies, the planar transformer provided in this application has a second via, allowing the intermediate capacitor to be electrically connected not only to at least one of the first and second output ports on the underlying circuit board, but also to a third output port via the second via. This provides the intermediate capacitor with more current transmission paths, effectively increasing its overcurrent capacity. Consequently, it ensures balanced current flow through the capacitors when the current is high, suppressing uneven current distribution. Furthermore, the enhanced overcurrent capacity of the intermediate capacitor effectively prevents damage caused by excessive current carrying by the two capacitors (i.e., the first and second capacitors) when the current is high.
[0060] The various embodiments in this specification are described in a progressive, parallel, or combined manner. Each embodiment focuses on its differences from other embodiments, and similar or identical areas between embodiments can be referred to interchangeably. For the apparatuses disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple, and relevant details can be found in the description of the method area.
[0061] It should be noted that, in the description of this application, the terms "upper," "lower," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. When a component is considered to be "connected" to another component, it can be directly connected to the other component or there may be a component centrally located at the same time.
[0062] It should also be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that an article or apparatus comprising a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such an article or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or apparatus that includes the aforementioned element.
[0063] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. A planar transformer, characterized in that, include: A multilayer circuit board and a magnetic core, wherein the multilayer circuit board includes a bottom circuit board, a top circuit board, and N layers of winding circuit boards stacked between the bottom circuit board and the top circuit board, where N≥3; the multilayer circuit board has a first via hole that penetrates the multilayer circuit board, and the magnetic core is disposed in the first via hole. The surface of the underlying circuit board has a first capacitor, a second capacitor, and at least one intermediate capacitor between the first capacitor and the second capacitor; the underlying circuit board also has a first output port and a second output port, the first capacitor is electrically connected to the first output port, the second capacitor is electrically connected to the second output port, and the intermediate capacitor is electrically connected to at least one of the first output port and the second output port. The N-layer winding circuit board includes a first winding circuit board with a third output port. The multilayer circuit board also has a second via, and the intermediate capacitor is electrically connected to the third output port through the second via.
2. The planar transformer according to claim 1, characterized in that, The surface of the bottom circuit board has a first metal layer and a second metal layer arranged along a first direction, and the first metal layer and the second metal layer extend along a second direction; the first metal layer and the second metal layer constitute the first capacitor, the second capacitor and the intermediate capacitor; the first output port and the second output port are respectively disposed at both ends of the first metal layer; The first direction extends from the edge of the multilayer circuit board toward its inner side and is parallel to the mounting surface of the multilayer circuit board. The second direction is perpendicular to the first direction and parallel to the mounting surface of the multilayer circuit board.
3. The planar transformer according to claim 2, characterized in that, The second via includes a first sub-via and a second sub-via. The first sub-via penetrates the first metal layer, and the second sub-via penetrates the N-layer winding circuit board. The intermediate capacitor is electrically connected to the third output port through the first sub-via and the second sub-via in sequence.
4. The planar transformer according to claim 3, characterized in that, The first capacitor includes a first sub-capacitor and a second sub-capacitor, the second capacitor includes a third sub-capacitor and a fourth sub-capacitor, and the at least one intermediate capacitor includes at least one first intermediate capacitor and at least one second intermediate capacitor, the first intermediate capacitor being located between the first sub-capacitor and the third sub-capacitor, and the second intermediate capacitor being located between the second sub-capacitor and the fourth sub-capacitor; The first metal layer includes a first sub-metal layer and a second sub-metal layer, and the second metal layer includes a third sub-metal layer and a fourth sub-metal layer. The first sub-metal layer and the third sub-metal layer are arranged along the first direction and located on a first side of the multilayer circuit board. The second sub-metal layer and the fourth sub-metal layer are arranged along the first direction and located on a second side of the multilayer circuit board. The first side and the second side are opposite to each other and are located on both sides of the axis of the multilayer circuit board. The extension direction of the axis is parallel to the mounting surface of the multilayer circuit board. The first sub-metal layer and the third sub-metal layer constitute a first sub-capacitor, a third sub-capacitor, and a first intermediate capacitor. The second sub-metal layer and the fourth sub-metal layer constitute a second sub-capacitor, a fourth sub-capacitor, and a second intermediate capacitor. The first output port includes a first sub-output port and a second sub-output port, and the second output port includes a third sub-output port and a fourth sub-output port. The first sub-output port and the third sub-output port are respectively disposed at both ends of the first sub-metal layer, and the second sub-output port and the fourth sub-output port are respectively disposed at both ends of the second sub-metal layer.
5. The planar transformer according to claim 4, characterized in that, The at least one first intermediate capacitor includes three first intermediate capacitors, the at least one second intermediate capacitor includes three second intermediate capacitors, the second via includes three first sub-vias and three second sub-vias located on the first side, and includes three first sub-vias and three second sub-vias located on the second side; wherein, the first intermediate capacitor is electrically connected to the third output port in sequence through the first sub-vias and second sub-vias located on the first side, and the second intermediate capacitor is electrically connected to the third output port in sequence through the first sub-vias and second sub-vias located on the second side.
6. The planar transformer according to claim 5, characterized in that, The third output port includes a first sub-output port located on the first side and a second sub-output port located on the second side. The second sub-via located on the first side is electrically connected to the first sub-output port, and the second sub-via located on the second side is electrically connected to the second sub-output port.
7. The planar transformer according to claim 4, characterized in that, The first via includes four third sub-vias arranged in a matrix. The magnetic core includes a first magnetic sheet and a second magnetic sheet. The first magnetic sheet includes four first magnetic pillars, and the second magnetic sheet includes four second magnetic pillars. The four first magnetic pillars correspond one-to-one with the four third sub-vias, and the four second magnetic pillars correspond one-to-one with the four third sub-vias. The first magnetic pillars and the second magnetic pillars are connected in the third sub-vias.
8. The planar transformer according to claim 7, characterized in that, N=6, the N-layer winding circuit board includes a second winding circuit board, a third winding circuit board, a fourth winding circuit board, a fifth winding circuit board, a sixth winding circuit board, and a first winding circuit board stacked sequentially. The second winding circuit board is adjacent to the bottom circuit board, and the first winding circuit board is adjacent to the top circuit board. The first winding circuit board has a first secondary winding, the second winding circuit board has a second secondary winding, the third and sixth winding circuit boards have primary windings, and the fourth and fifth winding circuit boards have a third secondary winding. The second winding circuit board has a fourth output port, and the fourth and fifth winding circuit boards have a fifth output port. The multilayer circuit board also has a third via distributed around the first via, the third via penetrating the multilayer circuit board, including a fourth sub-via and a fifth sub-via. One end of the first secondary winding is electrically connected to the fourth sub-via, and the other end is electrically connected to the fourth output port or the fifth output port through the fifth sub-via. The third via also includes a sixth sub-via, one end of the second secondary winding is electrically connected to the sixth sub-via, and the other end is electrically connected to the fourth output port. The third via also includes a seventh sub-via, one end of the third secondary winding is electrically connected to the seventh sub-via, and the other end is electrically connected to the fifth output port. The multilayer circuit board also includes a fourth via located on the third side, which is located between the first side and the second side. The fourth via includes an eighth sub-via and a ninth sub-via. One end of the primary winding is electrically connected to the eighth sub-via, and the other end is electrically connected to the ninth sub-via.
9. The planar transformer according to claim 8, characterized in that, The primary winding includes a first primary winding and a second primary winding. The first primary winding is arranged around any two of the four third sub-vias. The second primary winding is arranged around the remaining two third sub-vias. The first secondary winding, the second secondary winding, and the third secondary winding are arranged around each third sub-via, and the current directions of the first secondary winding and the second secondary winding are the same, while the current directions of the first secondary winding and the third secondary winding are opposite.
10. The planar transformer according to claim 9, characterized in that, The eighth sub-via includes the tenth sub-via and the eleventh sub-via, and the ninth sub-via includes the twelfth sub-via and the thirteenth sub-via. One end of the first primary winding is electrically connected to the tenth sub-via and the other end is electrically connected to the twelfth sub-via. One end of the second primary winding is electrically connected to the eleventh sub-via and the other end is electrically connected to the thirteenth sub-via.