Novel integrated circuit product

Abstract

The utility model relates to the technical field of packaging technology, in particular to a novel integrated circuit product, which comprises a chip, a connecting layer is arranged on the surface of the chip, a solder mask layer is arranged at the upper end of the connecting layer, a solder layer is arranged at the upper end of the solder mask layer, and the solder layer is AuSn alloy. According to the utility model, the solder layer is designed by adopting the AuSn alloy, and the mass ratio of the materials in the AuSn alloy is 8: 2, so that the solder layer not only has a lower melting point, but also has high thermal conductivity of 57W / m.k, which is obviously superior to that of the traditional solder material, and the high thermal conductivity is also beneficial to quickly and effectively transferring heat, reducing the temperature rise when the chip works, and improving the service life of the chip. And the thermal stability and the reliability of the integrated circuit in a high-power application occasion are further improved.

Description

Technical Field

[0001] This utility model relates to the field of packaging technology, specifically to a novel integrated circuit product. Background Technology

[0002] With the rapid development of power electronics technology, power devices are increasingly widely used in various fields such as automobiles, renewable energy, and high-performance computing, placing higher demands on their performance, efficiency, and reliability. Currently, the packaging process for power devices mainly relies on soft soldering or sintered silver technology. Although these processes are widely used in the field of electronic packaging, their respective limitations are gradually becoming bottlenecks for technological progress. Soft soldering processes suffer from significant power loss, poor thermal conductivity, and difficulty in effectively controlling void formation, thus limiting the heat dissipation capacity and long-term stability of the devices. While sintered silver technology can provide better thermal conductivity, its complex process flow and high cost restrict its widespread application, especially in cost-sensitive large-scale production.

[0003] Of particular note is the increasing prominence of thermal management issues as chip size grows. According to the principle of thermal deformation, large-size chips experience more significant thermal deformation during operation, resulting in greater internal stress. This directly leads to increased susceptibility to cracking, peeling, and other damage, severely impacting device reliability and lifespan. Furthermore, when using a back gold layer as the solder interface, maintaining the high flatness requirement of the thin solder layer becomes extremely difficult to control during the high-temperature processing of large-size chips, further exacerbating packaging challenges and quality risks. Therefore, a new type of integrated circuit product is urgently needed to address these problems. Utility Model Content

[0004] The purpose of this invention is to provide a new integrated circuit product to solve the problems mentioned in the background art.

[0005] The technical solution of this utility model is: a novel integrated circuit product, including a chip, a connection layer is disposed on the surface of the chip, a solder resist layer is disposed on the upper end of the connection layer, and a solder layer is disposed on the upper end of the solder resist layer, wherein the solder layer is an AuSn alloy.

[0006] Furthermore, the mass ratio of the various materials in the AuSn alloy is 7.5:2.5 to 8:2.

[0007] Furthermore, when the mass ratio of the materials in the AuSn alloy is 8:2, the thermal conductivity of the AuSn alloy is set to 57 W / mk.

[0008] Furthermore, the thickness of the connecting layer is set to 80-400nm, the thickness of the solder resist layer is set to 100-500nm, and the thickness of the solder layer is set to 1-3μm.

[0009] Furthermore, the upper surface of the connecting layer is electroplated with an aluminum layer.

[0010] Furthermore, the solder layer is an AgSn alloy.

[0011] This utility model provides a novel integrated circuit product through improvements, which, compared with the prior art, have the following improvements and advantages:

[0012] Firstly, the solder layer of this utility model adopts an AuSn alloy design, and the mass ratio of each material in the AuSn alloy is 8:2. This not only has a low melting point, but also a high thermal conductivity of up to 57W / m·k, which is significantly better than traditional soldering materials. The high thermal conductivity also helps to transfer heat quickly and effectively, reduce the temperature rise of the chip during operation, and thus improve the thermal stability and reliability of integrated circuits in high-power applications.

[0013] Secondly, the mass ratio of Au and Sn in this invention is 8:2, which ensures good wettability and mechanical strength after welding, while reducing the risk of void formation, improving the integrity of the welded joint, enhancing the reliability of the electrical connection, and extending the service life of the product.

[0014] Thirdly, by strictly controlling the thickness of the connection layer, solder mask layer and solder layer, this utility model can effectively reduce the problem of chip tilting during the packaging process, thereby ensuring precise alignment between the chip and the packaging substrate and improving the overall packaging quality and performance consistency. Attached Figure Description

[0015] The present invention will be further explained below with reference to the accompanying drawings and embodiments:

[0016] Figure 1 This is a schematic diagram of the structure of the novel integrated circuit product of this utility model;

[0017] Explanation of reference numerals in the attached figures:

[0018] 1. Connecting layer; 2. Solder resist layer; 3. Solder layer. Detailed Implementation

[0019] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0020] It should be noted that in the description of this utility model, the terms "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", and "outer" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this utility model.

[0021] refer to Figure 1 This embodiment provides a novel integrated circuit product, which includes a chip. A connection layer 1 is bonded to the surface of the chip, a solder resist layer 2 is bonded to the upper end of the connection layer 1, and a solder layer 3 is deposited on the upper end of the solder resist layer 2. In this embodiment, the thickness of the connection layer 1 is set to 80-400 nm, the thickness of the solder resist layer 2 is set to 100-500 nm, and the thickness of the solder layer 3 is set to 1-3 μm. Specifically, the connection layer 1 is made of Ti metal. Ti metal has excellent properties such as chemical stability, high hardness, corrosion resistance, and oxidation resistance, and it bonds well with Si material, but it cannot eutectic with Sn metal. Therefore, when the Ti metal is thin, the diffusion of Sn metal will affect the solderability between the Ti metal and Si material. However, when the Ti metal is too thick, the resistance of the Ti metal will be relatively high, that is, the thicker it is, the more it will affect the conductivity. Therefore, the thickness of the connection layer 1 is set to 80-400 nm, and in this embodiment, the thickness of the connection layer 1 is preferably set to 100-200 nm. Similarly, the solder resist layer 2 is made of Ni metal. Ni metal has corrosion resistance, high temperature resistance and good mechanical properties. It is used to prevent the diffusion of Sn metal. The thicker the Ni metal layer, the safer it will be. However, the thicker the Sn metal layer, the more it will affect the conductivity. It will also be affected by the soldering temperature and time. Therefore, the thickness of the solder resist layer 2 is set to 100-500nm, and in this embodiment, the thickness of Ni metal is preferably set to 200nm.

[0022] Furthermore, when the chip needs to meet the requirements of high voltage and high current, an aluminum layer can be electroplated on the upper surface of the connection layer 1 to improve its conductivity.

[0023] Furthermore, the solder layer 3 of the chip is set as an AuSn alloy, and the mass ratio of each material in the AuSn alloy is 8:2, that is, the mass ratio between metallic Au and metallic Sn is 7.5:2.5 to 8:2. Specifically, when the mass ratio of each material in the AuSn alloy is 8:2, the thermal conductivity of the AuSn alloy is 57 W / mK. It is worth noting that the thermal conductivity of traditional soft solder is 50 W / mK, therefore the AuSn alloy in this embodiment can be used as solder. At the same time, since the mass ratio between metallic Au and metallic Sn is 7.5:2.5 to 8:2, it has a high gold content. Therefore, using the AuSn alloy as solder will not only not affect the soldering performance, but also make it less prone to oxidation.

[0024] Specifically, the manufacturing method of the novel integrated circuit product in this embodiment is as follows:

[0025] Step 1: Select a logic chip manufactured using a high-performance silicon-based CMOS process and ensure that its surface is clean and free of contaminants.

[0026] Step 2: Using electron beam evaporation technology, a 150nm thick Ti / Au solder layer with a Sn content of 20% is uniformly deposited on the chip surface as the interconnect layer 1. It is worth noting that this 150nm thickness ensures good solder adhesion for the interconnect layer 1.

[0027] Step 3: On the bonding layer 1, a green epoxy resin solder resist layer 2 is coated by photolithography and development process, with the thickness controlled at 200nm. Only the necessary soldering areas are left open, and the rest are completely covered to prevent solder overflow.

[0028] Step 4: Using magnetron sputtering technology, a layer of AuSn alloy with a mass ratio of 8:2 is precisely deposited in the open area of ​​the solder resist layer 2 as solder layer 3 with a thickness of 2μm to ensure high thermal conductivity and good solderability.

[0029] Step 5: To enhance the performance of the bonding layer 1, the upper surface of the bonding layer 1 is electroplated, that is, a 10nm thick aluminum layer is added to improve its corrosion resistance and conductivity.

[0030] Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the present invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A novel integrated circuit product, characterized in that, The device includes a chip, on the surface of which a connection layer (1) is provided, a solder resist layer (2) is provided at the upper end of the connection layer (1), and a solder layer (3) is provided at the upper end of the solder resist layer (2), wherein the solder layer (3) is an AuSn alloy.

2. The novel integrated circuit product according to claim 1, characterized in that, The thickness of the connecting layer (1) is set to 80-400nm, the thickness of the solder resist layer (2) is set to 100-500nm, and the thickness of the solder layer (3) is set to 1-3μm.

3. The novel integrated circuit product according to claim 1 or 2, characterized in that, The upper surface of the connecting layer (1) is electroplated with an aluminum layer.

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