Chip packaging structure and chip packaging module

Abstract

The utility model provides a chip packaging structure and a chip packaging module, the chip packaging structure is provided with a salient point and a welding column between a packaging body and a first substrate, and the welding column is at least partially arranged around the salient point, so that after the packaging body and the first substrate are connected through the salient point and the welding column, the packaging body and the first substrate are connected through the salient point and the welding column; the shear stress caused by thermal mismatch between the packaging body and the first substrate can be released by using the bending (rotational degree of freedom in a first plane) or stretching (stretching degree of freedom in a first direction) deformation of the welding columns, so that the situation that the stress generated by thermal mismatch between the packaging body and the first substrate cannot be released is reduced; therefore, the probability of packaging failure between the packaging body and the first substrate is reduced, and the reliability of the chip packaging structure is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, specifically to a chip packaging structure and a chip packaging module. Background Technology

[0002] Chip packaging is a crucial step in semiconductor manufacturing. It isolates the bare die (Die, hereinafter referred to as chip) from the external environment and provides electrical connectivity and physical protection. Therefore, the chip packaging structure is of great significance for ensuring chip reliability.

[0003] Currently, in chip packaging structures, chips can be connected to substrates so that the chip's pins can connect to the traces on the substrate, thereby receiving signals from the outside or outputting signals to the outside. However, the reliability of chip packaging structures still faces significant challenges, limiting their normal use in harsh environments. Utility Model Content

[0004] In view of this, this application provides a chip packaging structure and a chip packaging module to improve the reliability of the chip packaging structure. Furthermore, this application also provides a chip packaging module having the above-mentioned chip packaging structure.

[0005] To achieve the above objectives, this application provides the following technical solution:

[0006] In a first aspect, this application discloses a chip packaging structure, including:

[0007] First substrate;

[0008] A package located on one side of the first substrate, the package comprising a bare die;

[0009] A connection structure located between the first substrate and the package body, the connection structure including bumps and solder pillars, the solder pillars being at least partially disposed around the bumps, the solder pillars having a degree of extensional freedom in a first direction, or the solder pillars having a degree of rotational freedom in a first plane; the first direction is perpendicular to the surface of the first substrate, and the first plane is parallel to the surface of the first substrate.

[0010] In this embodiment, after the package and the first substrate are connected by bumps and solder pillars, the bending (rotational degree of freedom in the first plane) or stretching (stretching degree of freedom in the first direction) deformation of the solder pillars themselves can be used to release the shear stress caused by thermal mismatch between the package and the first substrate. This reduces the probability of package failure between the package and the first substrate due to the inability to release the stress caused by thermal mismatch between the package and the first substrate, and improves the reliability of the chip package structure.

[0011] Meanwhile, in the chip packaging structure provided in this application, the solder pillars are arranged around the bumps, so that the solder pillars are placed in areas where stress is more obvious. While giving full play to the function of the solder pillars in relieving stress, the number of costly solder pillars used is reduced, which helps to reduce the overall cost of the chip packaging structure.

[0012] In some embodiments, the die includes a first die, the first die including a raised region and a recessed region surrounding the raised region;

[0013] The protrusion is disposed in the raised area, and the weld post is disposed in the recessed area.

[0014] In this embodiment, the raised area of ​​the first die can be connected to the first substrate through the protrusion, and the recessed area of ​​the first die can be connected to the first substrate through the solder post. In this way, the solder post is set in the recessed area at the corner, which can not only relieve stress, but also take advantage of the high degree of freedom of the adjustable height of the solder post to meet the connection requirements of the irregular die and the first substrate.

[0015] In some embodiments, the bare die includes: a second bare die and a third bare die;

[0016] The second die includes a central region and an edge region. The third die is disposed between the second die and the first substrate. The orthographic projection of the third die on the second die is located in the central region. The protrusion is provided between the second die and the third die.

[0017] The protrusion is provided between the third die and the first substrate, and the solder post is provided between the edge region of the second die and the first substrate.

[0018] In this embodiment, the package contains multiple bare dies of different sizes, allowing multiple dies to be stacked. Bumps are used to connect the dies (e.g., between the second and third dies), and solder posts are used to connect the area of ​​the top dies not covered by other dies to the first substrate. This allows the solder posts to relieve stress and also provides a high degree of freedom in adjusting their height, thus meeting the connection requirements between the top dies and the first substrate in a multi-layer stacked die package.

[0019] In some embodiments, the die includes a plurality of fourth dies, and the package further includes an interposer layer; wherein...

[0020] The bumps and the solder posts are disposed on the side of the interlayer facing the first substrate;

[0021] The plurality of fourth bare dies are disposed on the side of the interposer layer opposite to the first substrate;

[0022] The package further includes a redistribution layer and vias, and the fourth die is electrically connected to the bumps and / or the solder posts through the redistribution layer and the vias.

[0023] In this embodiment, a feasible method for combining solder pillars and bumps in 2.5D and 3D packaging structures is provided, which aims to solve the problem of bump cracking in 2.5D and 3D packaging structures. By setting the solder pillars at the edge of the package, the stress-relieving properties of the solder pillars are utilized to solve the problem that the bumps located in the edge area of ​​the package are prone to cracking due to CTE mismatch. At the same time, bumps can be used in areas with lower stress, such as the center of the package, to reduce the number of solder pillars used and reduce the overall cost.

[0024] In some embodiments, the plurality of fourth dies are arranged side by side on the side of the interposer layer opposite to the first substrate;

[0025] or

[0026] At least a portion of the fourth die stack is disposed on the side of the interposer layer opposite to the first substrate.

[0027] In this embodiment, multiple dies are packaged within the same chip package structure using 2.5D packaging. This allows for direct connections between the dies through a more compact wiring design, reducing signal transmission resistance and power consumption between dies. Simultaneously, the stress relief function of the solder pillars enhances the reliability of the chip package structure. Alternatively, vertically stacking a fourth die achieves higher space utilization and a smaller package volume. Again, the stress relief function of the solder pillars improves the reliability of the chip package structure.

[0028] In some embodiments, the ratio of the diameter to the height of the weld column ranges from 1:0.8 to 1:10.

[0029] Setting the ratio of the diameter to the height of the solder post within this range ensures that the solder post can fulfill its stress-relieving function while meeting the packaging requirements of various scenarios.

[0030] In some embodiments, the chip packaging structure further includes:

[0031] A filler adhesive is located between the first substrate and the package body, the filler adhesive wrapping the bumps and the solder posts.

[0032] Filler adhesive can isolate external impurities such as water and oxygen from eroding bumps and solder pillars, which helps improve the reliability of chip packaging structure.

[0033] In some embodiments, the chip packaging structure further includes: a metal cap or a reinforcing ring; wherein,

[0034] The metal cap covers the surface of the package body opposite to the first substrate and is connected to the first substrate;

[0035] The reinforcing ring is disposed on the surface of the first substrate and surrounds the package.

[0036] Metal caps or reinforcing rings provide additional mechanical protection to the package, resisting external physical impacts or vibrations and improving the package's mechanical strength. Furthermore, metals have excellent thermal conductivity; metal caps help dissipate heat generated by the die within the package quickly, effectively reducing the probability of electronic component failure due to overheating.

[0037] In some embodiments, solder is pre-applied to the side of the first substrate facing the package, and the solder is used to connect the bumps or the solder pillars. Pre-applying solder to the side of the first substrate facing the package enhances the soldering stability of the connection structure during the reflow soldering stage. This is because the pre-applied solder ensures sufficient contact between the bumps or solder pillars and the pads, and can better guarantee soldering quality even if the first substrate has warpage or diameter tolerances.

[0038] Secondly, this application provides a chip packaging module, including: a chip packaging structure as described in any of the preceding claims. Because the solder pillars of the chip packaging structure can alleviate shear stress, thereby improving reliability, the yield of the chip packaging module can be relatively high.

[0039] The chip packaging structure provided in this application has bumps and solder pillars between the package body and the first substrate, and the solder pillars are at least partially arranged around the bumps. In this way, after the package body and the first substrate are connected by the bumps and solder pillars, the shear stress caused by thermal mismatch between the package body and the first substrate can be released by the bending (rotational degree of freedom in the first plane) or stretching (stretching degree of freedom in the first direction) deformation of the solder pillars themselves. This reduces the probability of package failure between the package body and the first substrate due to the inability to release the stress caused by thermal mismatch between the package body and the first substrate, and improves the reliability of the chip packaging structure.

[0040] Meanwhile, in the chip packaging structure provided in this application, the solder pillars are arranged around the bumps, so that the solder pillars are placed in areas where stress is more obvious. While giving full play to the function of the solder pillars in relieving stress, the number of costly solder pillars used is reduced, which helps to reduce the overall cost of the chip packaging structure. Attached Figure Description

[0041] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0042] Figure 1 This is a cross-sectional schematic diagram of a chip packaging structure disclosed in an embodiment of this application.

[0043] Figure 2 This is a schematic diagram of the structure of a micro-spiral welding column disclosed in an embodiment of this application.

[0044] Figure 3 This is a schematic diagram of the structure of a micro-spring welding column disclosed in an embodiment of this application.

[0045] Figure 4 This is a cross-sectional schematic diagram of another chip packaging structure disclosed in an embodiment of this application.

[0046] Figure 5 This is a cross-sectional schematic diagram of another chip packaging structure disclosed in an embodiment of this application.

[0047] Figure 6 This is a cross-sectional schematic diagram of another chip packaging structure disclosed in an embodiment of this application.

[0048] Figure 7 This is a cross-sectional schematic diagram of another chip packaging structure disclosed in an embodiment of this application.

[0049] Figure 8 This is a cross-sectional schematic diagram of another chip packaging structure disclosed in an embodiment of this application.

[0050] Figure 9 This is a cross-sectional schematic diagram of another chip packaging structure disclosed in an embodiment of this application.

[0051] Figure 10 This is a cross-sectional schematic diagram of another chip packaging structure disclosed in an embodiment of this application.

[0052] Figure 11 This is a cross-sectional schematic diagram of another chip packaging structure disclosed in an embodiment of this application.

[0053] Figure 12 This is a schematic diagram illustrating the fabrication process of a chip packaging structure disclosed in an embodiment of this application.

[0054] exist Figures 1-12 middle:

[0055] 100 - Package, 200 - First substrate, 300 - Solder ball;

[0056] 101-Bond post, 1011-Micro spiral weld post, 1012-Micro spring weld post, 102-Filling adhesive, 103-Bump, 104-First die, 1041-Recessed area, 1042-Raised area, 105-Second die, 1051-Edge area, 1052-Center area, 106-Third die, 107-Fourth die, 108-Rewiring layer, 109-Intermediate layer, 110-Dielectric layer, 111-Via, 112-Molding compound, 113-Solder, 114-Passivation layer, 115-Metal cap, 116-Reinforcing ring. Detailed Implementation

[0057] This application provides a chip packaging structure to improve packaging reliability and reduce packaging costs. Furthermore, this application also provides a chip packaging module having the above-described chip packaging structure.

[0058] The technical solutions of the embodiments of this application will be described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0059] In chip packaging structures, the package and substrate are connected via bumps, which can include C4 bumps (Controlled Collapse of Chip Connection Bumps) and C2 bumps (Chip Connection Bumps). During production and use, it has been found that bump cracking failures are prone to occur when the package and substrate are connected via bumps, leading to a decrease in the reliability of the chip packaging structure.

[0060] Research on packaging materials and processes revealed that the Coefficient of Thermal Expansion (CTE) of the die (using silicon wafers as an example) in the package is 3 ppm / ℃, while the CTE of the substrate (using organic substrates as an example) is 10–11 ppm / ℃. After flip-chip reflow of the die and substrate with bumps, a CTE mismatch occurs, causing cracks in the bumps of the die due to shear stress generated during thermal transitions, leading to reliability issues. Analysis of chip package structures of different sizes shows that this problem is particularly pronounced in large-size chip packages, where the probability of cracks due to CTE mismatch is significantly higher.

[0061] To address this issue, the inventors discovered that a bonding post can be placed between the package and the substrate. This bonding post has a degree of freedom of extension in a first direction or a degree of freedom of rotation in a first plane. The first direction is perpendicular to the surface of the first substrate, and the first plane is parallel to the surface of the first substrate. Thus, after the package is connected to the substrate via the bonding post, even if stress is generated between the package and the substrate due to CTE mismatch, the shear stress caused by thermal mismatch between the package and the first substrate can be released by the bending (degree of freedom of rotation in the first plane) or extension (degree of freedom of extension in the first direction) deformation of the bonding post itself. This reduces the probability of package failure between the package and the first substrate due to the inability to release stress caused by thermal mismatch between the package and the first substrate, thereby improving the reliability of the chip package structure.

[0062] Further research revealed that due to the relatively high cost of solder posts, and by observing and analyzing the distribution of bumps causing cracks in the chip package structure, the stress caused by CTE mismatch around the perimeter of the package is significantly greater than that in the central area. This results in cracked bumps being more prevalent around the perimeter of the package. Therefore, to reduce the number of solder posts, they can be positioned at least partially around the bumps, placing them in areas of greater stress. This approach retains the stress-relieving function of the solder posts while reducing their overall cost, thus lowering the overall cost of the chip package structure.

[0063] Based on the above concept, this application provides a chip packaging structure, which will be described in illustrative terms below with reference to the accompanying drawings.

[0064] Compared to the chip packaging structures of related technologies, the chip packaging structure provided in this application is as follows: Figure 1 As shown, it includes:

[0065] First substrate 200;

[0066] A package 100 located on one side of the first substrate 200, the package 100 including a bare die;

[0067] A connection structure located between the first substrate 200 and the package 100, the connection structure including a solder post 101, the solder post 101 having a stretching degree of freedom in a first direction, or the solder post 101 having a rotational degree of freedom in a first plane; the first direction is perpendicular to the surface of the first substrate 200, and the first plane is parallel to the surface of the first substrate 200.

[0068] The weld post 101 may include at least one of a micro-spiral weld post 1011 and a micro-spring weld post 1012. (Reference) Figure 2 and Figure 3 , Figure 2 A schematic diagram of the structure of the micro-spiral welding post 1011 is shown. The micro-spiral welding post 1011 can have rotational degrees of freedom in the first plane. When subjected to external stress, the micro-spiral welding post 1011 can release the stress through its own rotation, avoiding reliability problems such as cracks caused by excessive stress. Figure 3 A schematic diagram of the micro-spring welding post 1012 is shown. The micro-spring welding post 1012 can have a degree of freedom of extension and contraction in the first direction F1. When subjected to external stress, the micro-spring welding post 1012 can release the stress through its own extension and contraction in the first direction, avoiding reliability problems such as cracks caused by excessive stress. The first substrate 200 may include an organic substrate, which has the characteristics of high flexibility and low cost. In addition to organic substrates, the first substrate 200 may also include inorganic substrates, which are not limited in this application.

[0069] In summary, by providing a solder post 101 between the package 100 and the first substrate 200, after the package 100 and the first substrate 200 are connected by the bump 103 and the solder post 101, the bending (rotational degree of freedom in the first plane) or stretching (stretching degree of freedom in the first direction) deformation of the solder post 101 itself can be used to release the shear stress caused by thermal mismatch between the package 100 and the first substrate 200. This reduces the probability of package failure between the package 100 and the first substrate 200 due to the inability to release the stress caused by thermal mismatch between the package 100 and the first substrate 200, and improves the reliability of the chip package structure.

[0070] To reduce the cost of chip packaging structures, in one embodiment, reference is made to... Figure 4 and Figure 5 The connection structure further includes a protrusion 103, and the weld post 101 is at least partially arranged around the protrusion 103.

[0071] like Figure 4 As shown, the bump 103 may include a C4 bump, and the C4 bump may include an under-bump metallization layer and a solder bump; as Figure 5 As shown, the bump 103 may also include a C2 bump, which may include a copper pillar and a solder cap. This application does not limit the type of the bump 103, but it depends on the actual situation.

[0072] In this embodiment, the solder post 101 is partially arranged around the bump 103, so that the solder post 101 is located in the area where stress is more obvious. While giving full play to the stress relief function of the solder post 101, the number of solder posts 101 used, which is more expensive, is reduced, which helps to reduce the overall cost of the chip packaging structure.

[0073] In one embodiment, to meet the packaging reliability and cost requirements of irregularly shaped dies, such as Figure 6 As shown, the bare die includes a first bare die 104, which includes a raised region 1042 and a recessed region 1041 surrounding the raised region 1042;

[0074] The protrusion 103 is disposed in the protruding area 1042, and the welding post 101 is disposed in the recessed area 1041.

[0075] In this embodiment, the protruding area 1042 of the first die 104 can be connected to the first substrate 200 through the protrusion 103, and the recessed area 1041 of the first die 104 can be connected to the first substrate 200 through the solder post 101. In this way, by setting the solder post 101 in the recessed area 1041 located at the corner, the solder post 101 can relieve stress on the one hand, and the high degree of freedom of the height adjustment of the solder post 101 can be taken advantage of to meet the connection requirements between the irregular die and the first substrate 200.

[0076] In one embodiment, such as Figure 7 As shown, the bare die includes: a second bare die 105 and a third bare die 106;

[0077] The second die 105 includes a central region 1052 and an edge region 1051. The third die 106 is disposed between the second die 105 and the first substrate 200. The orthographic projection of the third die 106 on the second die 105 is located in the central region 1052. The bump 103 is disposed between the second die 105 and the third die 106.

[0078] The third die 106 is provided with the bump 103 between it and the first substrate 200, and the edge region 1051 of the second die 105 is provided with the solder post 101 between it and the first substrate 200.

[0079] In this embodiment, the package 100 contains multiple bare dies of different sizes, allowing multiple bare dies to be stacked. The bumps 103 are used to connect the bare dies (e.g., between the second bare die 105 and the third bare die 106), and the solder posts 101 are used to connect the area of ​​the topmost bare die that is not covered by other bare dies to the first substrate 200. In this way, the solder posts 101 can relieve stress, and the adjustable height of the solder posts 101 can meet the connection requirements between the topmost bare die and the first substrate 200 in a multi-layer stacked die configuration.

[0080] In one embodiment, such as Figure 8 and Figure 9 As shown, the bare die includes a plurality of fourth bare dies 107, and the package 100 further includes an interposer layer 109; wherein,

[0081] The bump 103 and the weld post 101 are disposed on the side of the intermediary layer 109 facing the first substrate 200;

[0082] The plurality of fourth bare dies 107 are disposed on the side of the interposer layer 109 opposite to the first substrate 200;

[0083] The package 100 further includes a redistribution layer 108 and a via 111, and the fourth die 107 is electrically connected to the bump 103 and / or the solder post 101 through the redistribution layer 108 and the via 111.

[0084] In this embodiment, a feasible method for combining solder pillars 101 and bumps 103 in 2.5D and 3D packaging structures is provided to solve the problem of cracking of bumps 103 in 2.5D and 3D packaging structures. By setting the solder pillars 101 at the edge of the package body 100, the stress-relieving properties of the solder pillars 101 are utilized to solve the problem that the bumps located in the edge region 1051 of the package body 100 are prone to cracking due to CTE mismatch. At the same time, the bumps 103 can be used in areas with lower stress, such as the central part of the package body 100, to reduce the number of solder pillars 101 used and reduce the overall cost.

[0085] refer to Figure 8 , Figure 8A schematic diagram of a 2.5D package structure is shown. Multiple fourth dies 107 are arranged side-by-side on the side of the interposer 109 facing away from the first substrate 200. The fourth dies 107 are electrically connected to each other and to the first substrate 200 via a redistribution layer 108 and vias 111. Depending on the interposer 109 (e.g., silicon interposer 109, glass interposer 109), the vias 111 can be classified as TSV (Through Silicon Via) or TGV (Through Glass Via).

[0086] exist Figure 8 In the chip packaging structure shown, multiple dies are packaged together in a single chip package using 2.5D packaging. This allows for direct connections between the dies through a more compact wiring design, reducing signal transmission resistance and power consumption between dies. Simultaneously, the stress relief function of the solder pillars 101 enhances the reliability of the chip packaging structure.

[0087] refer to Figure 9 , Figure 9 A schematic diagram of a 3D packaging structure is shown, in which at least a portion of the fourth die 107 is stacked on the side of the interposer 109 facing away from the first substrate 200.

[0088] In this embodiment, by vertically stacking the fourth die 107, higher space utilization and a smaller package volume 100 are achieved. Simultaneously, the stress relief function of the solder pillars 101 improves the reliability of the chip package structure.

[0089] exist Figure 8 and Figure 9 In the chip packaging structure shown, the fourth die 107 can be electrically connected to the redistribution layer 108 via bumps 103. A filler adhesive 102 can be provided between the bumps 103 of the fourth die 107 to protect the bumps 103 from water and oxygen corrosion. The fourth die 107 can be encapsulated in the package 100 using molding compound 112 to improve its reliability. The redistribution layer 108 can be a multilayer structure, with a dielectric layer 110 between adjacent redistribution layers 108 to prevent accidental short circuits between different redistribution layers 108. On the side of the interposer layer 109 facing the first substrate 200, solder pillars 101 or bumps 103 can be provided with solder 113 on the side facing the interposer layer 109. A passivation layer 114 can be filled between adjacent solder pillars 113. Simultaneously, the connection structure can be encapsulated with filler adhesive 102 to prevent corrosion from water and oxygen. In some embodiments, solder balls 300 may be provided on the side of the first substrate 200 away from the package 100 as required.

[0090] In one embodiment, the ratio of the diameter to the height of the weld pillar 101 ranges from 1:0.8 to 1:10. Setting the ratio of the diameter to the height of the weld pillar 101 within this range ensures that the weld pillar 101 can effectively relieve stress while meeting other requirements. Figures 5-9 The encapsulation requirements are shown in various scenarios.

[0091] In one embodiment, such as Figure 1 , Figure 8 and Figure 9 As shown, the chip packaging structure further includes a filler adhesive 102 located between the first substrate 200 and the package body 100, the filler adhesive 102 wrapping the bump 103 and the solder post 101.

[0092] As mentioned above, the filler adhesive 102 can isolate external impurities such as water and oxygen from eroding the bumps 103 and the solder pillars 101, which is beneficial to improving the reliability of the chip packaging structure.

[0093] In one embodiment, such as Figure 10 and Figure 11 As shown, the chip packaging structure further includes: a metal cover 115 or a reinforcing ring 116; wherein,

[0094] The metal cover 115 covers the surface of the package 100 opposite to the first substrate 200 and is connected to the first substrate 200.

[0095] The reinforcing ring 116 is disposed on the surface of the first substrate 200, and the reinforcing ring 116 is disposed around the package 100.

[0096] refer to Figure 10 and Figure 11 The chip packaging structure may further include a metal cover 115 or a reinforcing ring 116, which provides additional mechanical protection to the package 100, resisting external physical impacts or vibrations and improving the mechanical strength of the package. Furthermore, metal has excellent thermal conductivity, and the metal cover 115 can help quickly dissipate the heat generated by the bare die in the package 100, effectively reducing the probability of electronic component failure due to overheating.

[0097] In one embodiment, such as Figure 10 As shown, the first substrate 200 has solder 113 pre-deposited on the side facing the package 100, and the solder 113 is used to connect the bump 103 or the solder post 101.

[0098] In this embodiment, solder 113 is pre-applied on the side of the first substrate 200 facing the package 100, which enhances the soldering stability of the connection structure during the reflow soldering stage. This is because the pre-applied solder 113 ensures sufficient contact between the bump 103 or solder post 101 and the pad, and can better guarantee the soldering quality even if the first substrate 200 has warping or diameter tolerances.

[0099] refer to Figure 12 , Figure 12 The diagram illustrates a soldering process between a package 100 and a first substrate 200 pre-applied with solder 113. First, solder 113 is applied to the package 100. The solder 113 can be applied by methods such as silver plating, tin deposition using physicochemical methods, stencil printing, or spraying solder paste. Then, an interconnect structure is formed above the solder 113. Figure 12 The following description uses an example where all components are solder pillars 101. In some embodiments, the connection structure may include solder pillars 101 and bumps 103. The solder pillars 101 can be placed using surface mounting or a template fixture. After placement, reflow soldering is used to connect the solder pillars 101 to the solder 113. Finally, the package 100 is flip-chip mounted onto the first substrate 200 pre-soldered with 113, and reflow soldering or thermoforming bonding is used to electrically connect the package 100 to the first substrate 200. Subsequent encapsulation steps complete the encapsulation process.

[0100] Based on the chip packaging structure described above, this application embodiment also provides a chip packaging module, which includes the chip packaging structure described above.

[0101] Since the chip packaging module includes the chip packaging structure described above, please refer to the above content for the beneficial effects brought by the chip packaging module by the chip packaging structure, which will not be repeated here.

[0102] The basic principles of this application have been described above with reference to specific embodiments. However, it should be noted that the advantages, benefits, and effects mentioned in this application are merely examples and not limitations, and should not be considered as essential features of each embodiment of this application. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the application to the necessity of employing the aforementioned specific details for implementation.

[0103] The block diagrams of devices, apparatuses, devices, and systems involved in this application are merely illustrative examples and are not intended to require or imply that they must be connected, arranged, or configured in the manner shown in the block diagrams. As those skilled in the art will recognize, these devices, apparatuses, devices, and systems can be connected, arranged, and configured in any manner. Words such as “comprising,” “including,” “having,” etc., are open-ended terms meaning “including but not limited to,” and are used interchangeably with them. The terms “or” and “and” as used herein refer to the terms “and / or,” and are used interchangeably with them unless the context clearly indicates otherwise. The term “such as” as used herein refers to the phrase “such as but not limited to,” and is used interchangeably with it.

[0104] It should also be noted that in the apparatus, equipment, and methods of this application, the components or steps can be disassembled and / or recombined. These disassemblies and / or recombinations should be considered as equivalent solutions of this application.

[0105] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use this application. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein can be applied to other aspects without departing from the scope of this application. Therefore, this application is not intended to be limited to the aspects shown herein, but rather to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0106] It should be understood that the qualifiers “first,” “second,” “third,” “fourth,” “fifth,” and “sixth” used in the description of the embodiments of this application are only used to more clearly illustrate the technical solutions and are not intended to limit the scope of protection of this application.

[0107] The above description has been given for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of this application to the forms disclosed herein. Although numerous exemplary aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, alterations, additions, and sub-combinations thereof.

Claims

1. A chip packaging structure, characterized in that, include: First substrate; A package located on one side of the first substrate, the package comprising a bare die; A connection structure located between the first substrate and the package body, the connection structure including bumps and solder pillars, the solder pillars being at least partially disposed around the bumps, the solder pillars having a degree of extensional freedom in a first direction, or the solder pillars having a degree of rotational freedom in a first plane; The first direction is perpendicular to the surface of the first substrate, and the first plane is parallel to the surface of the first substrate.

2. The chip packaging structure according to claim 1, characterized in that, The die includes a first die, which includes a raised region and a recessed region surrounding the raised region; The protrusion is disposed in the raised area, and the weld post is disposed in the recessed area.

3. The chip packaging structure according to claim 1, characterized in that, The bare film includes: a second bare film and a third bare film; The second die includes a central region and an edge region. The third die is disposed between the second die and the first substrate. The orthographic projection of the third die on the second die is located in the central region. The protrusion is provided between the second die and the third die. The protrusion is provided between the third die and the first substrate, and the solder post is provided between the edge region of the second die and the first substrate.

4. The chip packaging structure according to claim 1, characterized in that, The bare die includes multiple fourth bare dies, and the package further includes an interposer layer; wherein... The bumps and the solder posts are disposed on the side of the interlayer facing the first substrate; The plurality of fourth bare dies are disposed on the side of the interposer layer opposite to the first substrate; The package further includes a redistribution layer and vias, and the fourth die is electrically connected to the bumps and / or the solder posts through the redistribution layer and the vias.

5. The chip packaging structure according to claim 4, characterized in that, The plurality of fourth bare dies are arranged side by side on the side of the interposer layer opposite to the first substrate; or At least a portion of the fourth die stack is disposed on the side of the interposer layer opposite to the first substrate.

6. The chip packaging structure according to any one of claims 1 to 5, characterized in that, The ratio of the diameter to the height of the weld column ranges from 1:0.8 to 1:

10.

7. The chip packaging structure according to any one of claims 1 to 5, characterized in that, Also includes: A filler adhesive is located between the first substrate and the package body, the filler adhesive wrapping the bumps and the solder posts.

8. The chip packaging structure according to any one of claims 1 to 5, characterized in that, Also includes: Metal cap or reinforcing ring; among which, The metal cap covers the surface of the package body opposite to the first substrate and is connected to the first substrate; The reinforcing ring is disposed on the surface of the first substrate and surrounds the package.

9. The chip packaging structure according to any one of claims 1 to 5, characterized in that, The first substrate has solder pre-applied to the side facing the package, and the solder is used to connect the bumps or the solder pillars.

10. A chip packaging module, characterized in that, include: The chip packaging structure as described in any one of claims 1 to 9.

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