Substrate fabrication method
The method of lamination and curing a resin layer on a laminate to induce shape change allows for easy separation of the carrier and device layer, addressing the complexity and reliability issues in conventional carrier detachment methods.
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- MITSUI MINING & SMELTING CO LTD
- Filing Date
- 2025-10-09
- Publication Date
- 2026-04-23
AI Technical Summary
Conventional methods for separating the carrier from a carrier-mounted device layer in coreless build-up methods require specialized equipment or complex processes, leading to potential disconnection or peeling issues that reduce the reliability of the wiring layer connection.
A method involving lamination of a resin layer containing a curable resin on a laminate comprising a carrier, release layer, and device layer, followed by a curing treatment to induce shape change and generate shear stress for easy separation of the carrier and device layer without mechanical peeling means.
Facilitates easy and reliable separation of the carrier and device layer, reducing the risk of disconnection and peeling, and enabling the production of substrates with improved connection reliability.
Smart Images

Figure JP2025035804_23042026_PF_FP_ABST
Abstract
Description
Method for manufacturing a substrate
[0001] The present disclosure relates to a method for manufacturing a substrate.
[0002] In recent years, in order to increase the mounting density and miniaturize printed wiring boards, multi-layered printed wiring boards have been widely used. Such multi-layer printed wiring boards are used in many portable electronic devices for the purpose of reducing weight and size. And for such multi-layer printed wiring boards, further reduction in the thickness of the interlayer insulating layer and further weight reduction as a wiring board are required.
[0003] As a technique to meet such requirements, a method for manufacturing a multi-layer printed wiring board using a coreless build-up method has been adopted. The coreless build-up method is a method of alternately laminating (building up) an insulating layer and a wiring layer without using a so-called core substrate to form a multi-layer structure. In the coreless build-up method, it has been proposed to use a carrier-attached metal foil so that the carrier and the multi-layer printed wiring board can be easily peeled off. For example, Patent Document 1 (Japanese Patent Application Laid-Open No. 2005-101137) discloses a method for manufacturing a package substrate for mounting a semiconductor element, which includes attaching an insulating resin layer to the carrier surface of a copper foil with a carrier to form a support, forming a first wiring conductor on the ultra-thin copper layer side of the copper foil with a carrier by processes such as photoresist processing, pattern electrolytic copper plating, and resist removal, then forming a build-up wiring layer, peeling off the carrier-attached support substrate, and removing the ultra-thin copper layer.
[0004] Furthermore, in order to miniaturize embedded circuits as shown in Patent Document 1, a carrier-mounted metal foil with a metal layer thickness of 1 μm or less is desired. Therefore, in order to reduce the thickness of the metal layer, it has been proposed to form the metal layer by a vapor phase method such as sputtering. For example, Patent Document 2 (International Publication No. 2017 / 150283) discloses a carrier-mounted copper foil in which a release layer, an anti-reflective layer, and an ultrathin copper layer (e.g., a film thickness of 300 nm) are formed by sputtering on a carrier such as a glass sheet. Patent Document 3 (International Publication No. 2017 / 150284) also discloses a carrier-mounted copper foil in which an intermediate layer (e.g., an adhesive metal layer and a release assist layer), a release layer, and an ultrathin copper layer (e.g., a film thickness of 300 nm) are formed by sputtering on a carrier such as a glass sheet. Patent documents 2 and 3 also teach that interposing an intermediate layer made of a predetermined metal provides excellent stability in the mechanical peel strength of the carrier, and that the anti-reflective layer exhibits a desirable dark color, thereby improving visibility in image inspection (e.g., automated image inspection (AOI)).
[0005] In particular, with the increasing miniaturization and power saving of electronic devices, there is a growing need for higher integration and thinner semiconductor chips and printed circuit boards. To meet these needs, the adoption of FO-WLP (Fan-Out Wafer Level Packaging) and PLP (Panel Level Packaging) has been considered in recent years as next-generation packaging technologies. Furthermore, the adoption of coreless build-up methods is also being considered for FO-WLP and PLP. One such method is called the RDL-First (Reduction Layer-First) method, in which a wiring layer and, if necessary, a build-up wiring layer are formed on the surface of a coreless support, the chip is mounted and sealed, and then the support is peeled off. For example, Patent Document 4 (Japanese Patent Application Publication No. 2015-35551) discloses a method for manufacturing a semiconductor device, which includes forming a metal delamination layer on the main surface of a support made of glass or a silicon wafer, forming an insulating resin layer thereon, forming a redisting layer (Redistrib Layer) including a build-up layer thereon, mounting and sealing a semiconductor integrated circuit thereon, exposing the delamination layer by removing the support, exposing secondary mounting pads by removing the delamination layer, forming solder bumps on the surface of the secondary mounting pads, and secondary mounting.
[0006] Incidentally, when peeling a carrier with a wiring layer fabricated using a coreless build-up method or the like, the device layer including the wiring layer may bend significantly, causing disconnection or peeling, which can reduce the reliability of the wiring layer connection. Therefore, methods for removing carriers that address this problem have been proposed. For example, Patent Document 5 (International Publication No. 2018 / 173807) discloses a method for manufacturing a wiring board, in which a composite laminate (including a support, a release layer, and a multilayer wiring board) is brought into close contact with a stage, and the support or multilayer wiring board is peeled from the release layer to form a predetermined convex curved surface. According to this method, cracks in the support and defects such as cracks and disconnections in the multilayer wiring board can be prevented, and stable peeling is possible.
[0007] Japanese Patent Publication No. 2005-101137, International Publication No. 2017 / 150283, International Publication No. 2017 / 150284, Japanese Patent Publication No. 2015-35551, International Publication No. 2018 / 173807
[0008] However, conventional carrier detachment methods sometimes require specialized equipment or complex processes to separate the device layer from the carrier, and there is room for improvement from the perspective of simpler carrier detachment.
[0009] The inventors have now discovered that in a laminate comprising a carrier, a release layer, and a device layer in that order, a resin layer containing a curable resin is laminated onto the carrier surface and a curing treatment is performed. By utilizing the change in the shape of the carrier due to the curing shrinkage of the resin layer, the carrier and the device layer can be easily separated, and a substrate can be manufactured.
[0010] Therefore, an object of the present invention is to provide a method for manufacturing a substrate that allows for easy separation of the carrier and the device layer.
[0011] The following embodiments are provided according to this disclosure: [Embodiment 1] A method for manufacturing a substrate, comprising the steps of: preparing a laminate having a release layer and a device layer in order on a carrier; laminating a resin layer containing a curable resin on the carrier-side surface of the laminate to obtain a resin-layered laminate; performing a curing treatment of the curable resin on the resin-layered laminate to shrink the resin layer, thereby causing the carrier to be pulled in a direction following the shrinkage of the resin layer, and thereby changing the shape of the carrier or the resin-layered laminate; and utilizing the change in the shape of the carrier to generate shear stress between the carrier and the device layer, thereby peeling the device layer from the resin-layered laminate at the position of the release layer. [Embodiment 2] The method for manufacturing a substrate according to Embodiment 1, wherein the peeling of the device layer from the resin-layered laminate is performed solely by utilizing the change in the shape of the carrier, without using any mechanical peeling means. [Aspect 3] A method for manufacturing a substrate according to aspect 1 or 2, further comprising a step of trimming the device layer before laminating the resin layer, wherein the trimming is performed by making cuts such that, when the laminate is viewed from above, the cuts pass inside the contour of the device layer, and when the laminate is viewed in cross-section, the cuts penetrate the device layer. [Aspect 4] A method for manufacturing a substrate according to any one of aspects 1 to 3, further comprising a step of laminating a reinforcing sheet on the device layer before curing the curable resin. [Aspect 5] A method for manufacturing a substrate according to aspect 4, wherein when the shape of the carrier is changed, the reinforcing sheet and the device layer supported by it are not curved, and the device layer is peeled off the resin-layered laminate by changing the shape of the portion of the resin-layered laminate other than the device layer. [Aspect 6] A method for manufacturing a substrate according to any one of aspects 1 to 5, wherein the laminate further comprises a metal layer provided between the release layer and the device layer. [Aspect 7] A method for manufacturing a substrate according to any one of aspects 1 to 6, further comprising a step of priming the carrier before laminating the resin layer.[Aspect 8] A method for manufacturing a substrate according to any one of aspects 1 to 7, wherein the curable resin includes a thermosetting resin. [Aspect 9] A method for manufacturing a substrate according to aspect 8, wherein the curing treatment includes a heat treatment of the resin layer and a subsequent heat dissipation treatment, and the maximum difference between the temperature of the heat treatment and the ambient temperature of the heat dissipation treatment is 50°C or more. [Aspect 10] A method for manufacturing a substrate according to aspect 8 or 9, wherein the thermosetting resin has a thermal expansion coefficient of 10 ppm / K or more. [Aspect 11] A method for manufacturing a substrate according to any one of aspects 8 to 10, wherein the thermosetting resin includes at least one resin selected from the group consisting of (meth)acrylic resins, vinyl resins, allyl resins, melamine resins, urethane resins, epoxy resins, silicone resins, polyester resins, polyamic acid resins, polyimide resins, styrene maleic acid resins, styrene maleic anhydride resins, maleimide resins, and cyanate resins. [Aspect 12] The method for manufacturing a substrate according to any one of aspects 1 to 11, wherein the curable resin has a maximum curing shrinkage rate of 0.0010% or more as measured in accordance with JIS K 6941:2019. [Aspect 13] The method for manufacturing a substrate according to any one of aspects 1 to 12, wherein the resin layer is provided in the form of a resin film. [Aspect 14] The method for manufacturing a substrate according to any one of aspects 1 to 13, wherein the resin layer has a thickness of 0.01 μm or more and 1 mm or less. [Aspect 15] The method for manufacturing a substrate according to any one of aspects 1 to 14, wherein the carrier is composed of glass, silicon, metal, or ceramics. [Aspect 16] The method for manufacturing a substrate according to any one of aspects 1 to 15, wherein the carrier has a thickness of 3000 μm or less. [Aspect 17] The method for manufacturing a substrate according to any one of aspects 1 to 16, wherein the device layer includes a wiring layer, an electronic element provided on the wiring layer, and a molded resin layer that embeds the electronic element.
[0012] This is a schematic cross-sectional flowchart showing an example of a substrate manufacturing method of the present invention, corresponding to the initial steps ((i) to (iii)). This is a schematic cross-sectional flowchart showing an example of a substrate manufacturing method of the present invention, corresponding to the later steps ((iv) to (vi)) following the steps shown in Figure 1. This is a schematic cross-sectional flowchart showing an example of a device layer formation method, corresponding to the initial steps ((i) to (iii)). This is a schematic cross-sectional flowchart showing an example of a device layer formation method, corresponding to the later steps ((iv) to (vi)) following the steps shown in Figure 3. This is a schematic cross-sectional flowchart showing another example of a substrate manufacturing method of the present invention, illustrating an embodiment in which the curvature of the device layer is suppressed using a reinforcing sheet. This is a schematic diagram for explaining the mechanism by which the carrier and the device layer separate.
[0013] Substrate Manufacturing Method The present invention relates to a method for manufacturing a substrate. The method of the present invention may include the steps of (1) preparing a laminate, (2) optionally trimming the device layer, (3) laminating a resin layer, (4) optionally laminating a reinforcing sheet, (5) curing the resin layer, and (6) separating the carrier and device layer. Steps (1) to (6) will be described below with reference to the drawings. In this specification, a substrate means a substrate that includes at least one of wiring, electronic devices, materials for forming electronic devices, and those manufactured by electroforming (e.g., metal patterns).
[0014] (1) Examples of the manufacturing method of the substrate of the present invention are shown in the first and second uses of the laminate. First, as shown in Figure 1(i), a laminate 10 is prepared in which a release layer 16 and a device layer 20 are provided in order on a carrier 12. The release layer 16 is a layer provided on the carrier 12 that contributes to the separation of the carrier 12 and the device layer 20. The device layer 20 is a layer provided on the release layer 16 that has a device function. As shown in Figure 4(vi), it is preferable that the laminate 10 further includes a metal layer 18 between the release layer 16 and the device layer 20. The laminate 10 may further include an intermediate layer 14 between the carrier 12 and the release layer 16.
[0015] The material of the carrier 12 is not particularly limited, but it is preferably made of glass, silicon, metal, ceramics, or a combination thereof. Furthermore, the carrier 12 is preferably 3000 μm or less in thickness, more preferably 2000 μm or less, and even more preferably 1600 μm or less in thickness. This makes it easier to control the shape change of the carrier 12 within a desired range in the process described later. From the viewpoint of making it easy to change the shape of the carrier 12, a thinner carrier is preferable, and although the lower limit is not particularly limited, it is typically 50 μm or more when made of metal, and typically 300 μm or more when made of glass, silicon, or ceramics.
[0016] The device layer 20 typically includes at least a wiring layer, and more preferably includes an electronic element and a molded resin layer. The wiring layer may be in the form of a redistribution layer formed by a method such as the coreless build-up method described above. The redistribution layer preferably includes a wiring pattern with a line / space (L / S) of 10 μm or less / 10 μm or less, and more preferably includes a wiring pattern with a line / space (L / S) of 5 μm or less / 5 μm or less. The lower limit of the line / space (L / S) in the wiring pattern is not particularly limited, but is typically 1 μm or more / 1 μm or more. The electronic element may be a semiconductor chip, an integrated circuit, a sensor, or other device with functional capabilities. The molded resin layer may have a structure that embeds only the electronic element, or it may have a structure that embeds both the electronic element and the wiring layer. However, the device layer 20 may mainly consist of a wiring layer and may not include an electronic element and / or a molded resin layer.
[0017] Figures 3 and 4 show a preferred example of a method for forming the device layer 20. First, a carrier-attached metal foil is prepared, comprising an intermediate layer 14 (an optional layer), a release layer 16, and a metal layer 18 (an optional layer) in that order on a carrier 12 (Figure 3(i)). A wiring layer and an insulating layer are formed on the surface of the metal layer 18 of this carrier-attached metal foil by a coreless build-up method to obtain a first rewiring layer 20a (Figure 3(ii)). Specifically, a photoresist is laminated onto the metal layer 18, and exposure and development are performed to form a predetermined pattern to form a resist pattern. Then, electroplating (e.g., electroplating of copper) is applied between the resist patterns, and after peeling off the resist pattern, the unnecessary parts of the metal layer 18 exposed by the peeling off of the resist pattern (i.e., parts where a wiring pattern is not formed) are removed by etching to form a first wiring layer. Subsequently, an insulating layer and an n wiring layer (n is an integer of 2 or more) are alternately formed on the surface of the carrier-attached metal foil on which the first wiring layer is formed. Thus, a first redistribution layer 20a is obtained, which includes an insulating layer and a wiring layer formed inside and / or on the surface of the insulating layer.Optionally, pillars (columnar electrodes) P or electronic elements such as chips C may be formed on the first redistribution layer 20a (Figure 3(iii)).A molded resin layer 20b is formed by embedding the pillars P and chips C in insulating resin (Figure 4(iv)).Alternatively, the pillars P and other elements may be exposed from the molded resin layer 20b by surface polishing (Figure 4(v)).Preferred examples of surface polishing include grinding using a grinding wheel and chemical mechanical polishing (CMP).Then, a second redistribution layer 20c is formed on the surface of the molded resin layer 20b by the coreless build-up method described above (Figure 4(vi)).In this way, a laminate 10 having a device layer 20 including a wiring layer, electronic elements and a molded resin layer can be preferably manufactured.Other preferred embodiments of the laminate 10 will be described later.
[0018] (2) Trimming of the device layer (optional step) As shown in Figure 1(ii), the device layer 20 may be trimmed. Preferably, this trimming is performed by making cuts that pass inside the contour of the device layer 20 when the laminate 10 is viewed from above, and that penetrate the device layer 20 when the laminate 10 is viewed in cross-section. By making such cuts, a starting point for delamination can be formed, making it possible to separate the carrier 12 and the device layer 20 more easily and reliably in the process described later. The trimming is not particularly limited and any known method can be used. For example, cuts can be made in the device layer 20 using a cutting tool such as a cutter or a machine tool such as a cutting blade.
[0019] The above-mentioned cuts are preferably made so as to pass through a region 0.5 mm to 30.0 mm inward from the contour of the device layer 20 when the laminate 10 is viewed from above, more preferably 1.0 mm to 15.0 mm inward, and even more preferably 1.5 mm to 5.0 mm inward. This effectively suppresses damage to the device layer 20 (especially the wiring layer and electronic elements) when the carrier 12 is peeled off.
[0020] (3) As shown in the resin layer lamination diagram 1(iii), a resin layer 22 is laminated on the carrier 12 side surface of the laminate 10 (the surface opposite to the device layer 20) to obtain a resin-layered laminate 24. The resin layer 22 contains a curable resin. As will be described later, by performing a curing treatment on the resin layer 22 laminated on the surface of the carrier 12, the carrier 12 and the device layer 20 can be easily separated by utilizing the shrinkage force when the resin layer 22 hardens.
[0021] The resin layer 22 is preferably provided in the form of a resin film for ease of handling. The resin layer 22 preferably has a thickness of 0.01 μm to 1 mm, more preferably 0.1 μm to 800 μm, even more preferably 1 μm to 700 μm, particularly preferably 10 μm to 600 μm, and most preferably 100 μm to 400 μm. Within this range, it becomes easier to apply the desired stress to the carrier 12 during the curing process of the resin layer 22.
[0022] The curable resin contained in the resin layer 22 should have the property of shrinking during curing. Therefore, the curable resin preferably has a maximum curing shrinkage rate of 0.0010% or more, more preferably 0.010% or more, even more preferably 0.10% to 1.0%, and particularly preferably 0.50% to 0.90%. This maximum curing shrinkage rate refers to the volume reduction rate from the curing start point to the shrinkage end point, measured in accordance with JIS K 6941:2019.
[0023] Examples of curable resins include thermosetting resins, photocurable resins (e.g., UV-curable resins), or mixtures thereof. For example, a resin that allows for easy control of shrinkage rate by adjusting the curing speed can be appropriately selected.
[0024] The thermosetting resin preferably has a thermal expansion coefficient of 10 ppm / K or more, more preferably 30 ppm / K or more, even more preferably 50 ppm / K or more, and particularly preferably 100 ppm / K or more. A larger thermal expansion coefficient is preferable, and there is no particular upper limit, but it is typically 1000 ppm / K or less. By using a thermosetting resin having a thermal expansion coefficient within the above range, as will be described later, it becomes easier to control the deformation of the resin layer 22 by the curing treatment involving heating to a desired range.
[0025] Preferred examples of thermosetting resins include (meth)acrylic resins, vinyl resins, allyl resins, melamine resins, urethane resins, epoxy resins, silicone resins, polyester resins, polyamic acid resins, polyimide resins, styrene maleic acid resins, styrene maleic anhydride resins, maleimide resins, and cyanate resins.
[0026] The method of the present invention may further include a step of priming the carrier 12 before laminating the resin layer 22. For example, when using a curable resin with low adhesion to the carrier 12, the adhesion between the carrier 12 and the resin layer 22 can be improved by interposing a primer. Known methods can be used for priming, and it can preferably be carried out by applying a commercially available primer solution to the surface of the laminate 10 on the carrier 12 side (the surface opposite to the device layer 20) and drying it.
[0027] (4) Lamination of reinforcing sheet (optional step) As shown in Figure 5(i), a reinforcing sheet 26 may be laminated on the device layer 20. This effectively suppresses the bending of the device layer 20 supported by the reinforcing sheet 26. For example, for a device layer 20 where bending reduces the connection reliability of the wiring layer, etc., it is preferable to laminate the reinforcing sheet 26 in advance before curing the resin layer 22. Accordingly, according to a preferred embodiment of the present invention, as shown in Figures 5(ii) and (iii), when the shape of the carrier 12 is changed, the reinforcing sheet 26 and the device layer 20 supported by it are not bent, and the device layer 20 is peeled off from the resin layer laminate 24 by changing the shape of the part of the resin layer laminate 24 other than the device layer 20 (particularly the carrier 12). Note that the lamination of the reinforcing sheet 26 may be performed before the lamination of the resin layer 22 as described above, or it may be performed after the lamination of the resin layer 22.
[0028] The reinforcing sheet 26 is not particularly limited in material as long as it can prevent or suppress the bending of the device layer 20, but is preferably made of metal. Preferred examples of metals that make up the reinforcing sheet 26 include aluminum and aluminum alloys (e.g., duralumin (e.g., A2017, A2024, and A7075 in JIS standards)), stainless steel, copper and copper alloys (e.g., bronze, phosphorus copper, copper-nickel alloy, copper-titanium alloy, etc.), titanium and titanium alloys, and nickel and nickel alloys.
[0029] The form of the reinforcing sheet 26 is not limited to a sheet, but may be a film, plate, or foil, as long as it can prevent or suppress the bending of the device layer 20, and is preferably in the form of a sheet or plate. The reinforcing sheet 26 may also be a laminate of these sheets, films, plates, foils, etc. The thickness of the reinforcing sheet 26 is preferably 10 μm or more and 1 mm or less, more preferably 50 μm or more and 800 μm or less, and even more preferably 100 μm or more and 600 μm or less, from the viewpoint of maintaining the strength of the reinforcing sheet and ease of handling.
[0030] The reinforcing sheet 26 may be laminated onto the device layer 20 via an adhesive layer (not shown). Preferably, the adhesive layer is a layer that can adhere the reinforcing sheet 26 to the device layer 20 with desired adhesion and can be removed from the device layer 20 after use. The manner of adhesion between the reinforcing sheet 26 and the device layer 20 via the adhesive layer is not particularly limited and may be, for example, mechanical bonding (i.e., adhesion by anchoring effect), physical interaction (i.e., adhesion by van der Waals forces), chemical bonding, etc. Examples of adhesive materials included in the adhesive layer include phenolic resin, urea resin, melamine resin, epoxy resin, polyimide resin, ethylene-vinyl acetate copolymer resin (EVA), urethane resin, acrylic resin, synthetic rubber, and starch, preferably thermosetting epoxy resin, thermosetting polyimide resin, photosensitive polyimide resin, acrylic resin, phenolic resin, or a combination thereof, more preferably thermosetting epoxy resin, thermosetting polyimide resin, acrylic resin, phenolic resin, or a combination thereof. The adhesive layer preferably has a thickness of 1 μm to 2000 μm, more preferably 3 μm to 1000 μm, even more preferably 5 μm to 800 μm, and particularly preferably 10 μm to 500 μm. Such a thickness makes it easier to control the adhesion to the device layer 20 within a desired range, and allows for quick peeling and removal of the reinforcing sheet 26 after use.
[0031] If desired, other layers such as an intermediate layer, release layer, or metal layer may be interposed between the reinforcing sheet 26 and the adhesive layer. For example, the adhesive layer, metal layer, release layer, intermediate layer, and reinforcing sheet 26 may be laminated on the device layer 20 in this order. The configurations of the intermediate layer, release layer, and metal layer are not particularly limited, and may, for example, conform to the preferred configurations of the intermediate layer 14, release layer 16, and metal layer 18 described later with respect to the laminate 10.
[0032] (5) Curing treatment of the resin layer As shown in Figure 2(iv), the resin layer 22 is shrunk by curing treatment of the resin layer laminate 24 with a curable resin. As a result, the carrier 12 is pulled in the direction that follows the shrinkage of the resin layer 22, thereby changing the shape of the carrier 12 or the resin layer laminate 24. That is, the resin layer 22 shrinks toward its center due to the curing treatment (i.e., its volume decreases). At this time, a three-dimensional stress is generated in the resin layer 22 toward the center of the resin layer, and this stress pulls the carrier 12 that is in contact with the resin layer 22, resulting in a change in the shape of the carrier 12, etc. In this way, by utilizing the three-dimensional stress associated with the shrinkage of the resin layer 22, the stress applied to the carrier 12 is made uniform, and therefore, damage or defects to the carrier 12 and / or device layer 20 caused by locally applied stress can be effectively suppressed. When the reinforcing sheet 26 is pre-laminated on the device layer 20, as described above, changes in the shape of the device layer 20 (e.g., curvature) are suppressed, and typically, the shape of the carrier 12 changes primarily. On the other hand, when the reinforcing sheet 26 is not pre-laminated, the shape of not only the carrier 12 but also the device layer 20 may change.
[0033] The shape change of the carrier 12 or the laminated body 24 with the resin layer is preferably such that the outer surface of the carrier 12 becomes concave, as shown in Figure 2(v). However, it is also possible that, before the lamination of the resin layer 22, the laminated body 10 is warped such that the outer surface of the carrier 12 becomes convex due to the formation of the device layer 20 or the like. In such a case, the shape change may be such that the curvature of the carrier 12 or the laminated body 24 with the resin layer is corrected so that the outer surface of the carrier 12 becomes flat.
[0034] When the curable resin includes a thermosetting resin, the curing treatment preferably includes a heat treatment of the resin layer 22 and a subsequent heat dissipation treatment. In this way, the resin layer 22 undergoes not only curing shrinkage but also deformation corresponding to the temperature difference between the heat treatment and the heat dissipation treatment, as well as the coefficient of thermal expansion (CTE). By utilizing this deformation of the resin layer 22, it becomes easier to apply the desired stress to the carrier 12 or the laminated body 24 with the resin layer. The heat treatment and heat dissipation treatment can be carried out by known methods and are not particularly limited. For example, the heat treatment can preferably be carried out by using a commercially available oven or the like to heat the laminated body 24 with the resin layer to a desired temperature according to the curing conditions of the thermosetting resin. When the laminated body 24 with the resin layer (e.g., device layer 20) includes solder, the heat treatment can preferably be carried out at a temperature below the melting point of the solder. Furthermore, the heat dissipation treatment can preferably be carried out by cooling the laminated body 24 with the resin layer after heating until it reaches a desired ambient temperature (e.g., room temperature (25°C) or lower). From the viewpoint of promoting the deformation of the resin layer 22 described above, the maximum difference between the temperature of the heat treatment and the ambient temperature of the heat dissipation treatment is preferably 50°C or more, more preferably 70°C or more, even more preferably 100°C or more, and particularly preferably 130°C or more. The larger this maximum temperature difference, the better, and although there is no particular upper limit, it is typically 200°C or less.
[0035] (6) Separation of carrier and device layer As shown in Figure 2(vi), shear stress is generated between the carrier 12 and the device layer 20 by utilizing the shape change of the carrier 12. This causes the device layer 20 to be separated from the resin-coated laminate 24 at the location of the release layer 16. Note that the resin layer curing process described in (5) above and this process may be performed continuously. That is, separation of the carrier 12 and the device layer 20 during the curing shrinkage of the resin layer 22 is permissible.
[0036] The delamination mechanism of the carrier 12 and / or device layer 20 in the present invention is not entirely clear, but it is thought to be as follows. Here, Figure 6 shows a schematic diagram illustrating the stress applied to each layer when a shape change occurs in the laminate 10. First, as shown in Figures 6(i) and (ii), a force is applied to the laminate 10 in a direction that causes the outer surface of the carrier 12 to contract, and / or a force that causes the outer surface of the device layer 20 to stretch, causing the laminate 10 to bend or deform. At this time, as shown in Figure 6(ii), a compressive stress is applied to the carrier 12 in a direction toward the center of the carrier, and a tensile stress is applied to the device layer 20 in a direction toward the outer circumference of the device layer. In other words, stresses in opposite directions are applied to the carrier 12 and the device layer 20. For this reason, as shown in Figure 6(iii), shear stress is generated in the delamination layer 16 interposed between the carrier 12 and the device layer 20 due to the above compressive and tensile stresses. Then, the shear stress causes the delamination layer 16 to break at least partially, separating the carrier 12 and the device layer 20. It is also believed that even when the carrier 12 changes shape so that its outer surface changes from a convex surface to a flat surface, the separation of the carrier 12 and the device layer 20 proceeds by the same mechanism as described above.
[0037] Thus, according to the present invention, the carrier 12 and the device layer 20 can be easily separated by utilizing the shape change of the carrier 12, etc., due to the curing shrinkage of the resin layer 22, without requiring a dedicated device or complex process. Therefore, according to a preferred embodiment of the present invention, the peeling of the device layer 20 from the resin-coated laminate 24 is performed solely by utilizing the shape change of the carrier 12, without using mechanical peeling means. However, if the carrier 12 and / or the device layer 20 are only partially separated (i.e., only a part of the peeling layer 16 is destroyed), the carrier 12 and the device layer 20 may be completely separated by gripping the carrier 12 and / or the device layer 20 with your hands or a jig and pulling them apart.
[0038] The device layer 20 peeled off from the resin-layered laminate 24 may be used as a substrate for the final product as is, or it may be used as a substrate after further processing of various known treatments on the device layer 20. For example, if a reinforcing sheet 26 is laminated on the device layer 20, it is preferable to peel off the reinforcing sheet 26 from the device layer 20 after removing the carrier 12. In this regard, if the reinforcing sheet 26 is laminated via an adhesive layer, the reinforcing sheet 26 can be removed by dissolving or softening the adhesive layer by contacting it with a solution that can dissolve the adhesive layer. Furthermore, if necessary, a process such as mounting an electronic element such as a chip on the device layer 20 (e.g., second redistribution layer 20c) may be performed. By laminating multiple IC packages together with the chip C that can be embedded in the device layer 20 (e.g., molded resin layer 20b) described above and mounting them on the substrate, the integration density can be improved. Furthermore, a solder resist or mounting bumps may be formed on the outer surface of the device layer 20.
[0039] Laminate As described above, the laminate 10 used in the method of the present invention may comprise, in order, a carrier 12, an optional intermediate layer 14, a release layer 16, an optional metal layer 18, and a device layer 20. Each of the intermediate layer 14, the release layer 16, and the metal layer 18 may be a single layer or a multilayer consisting of two or more layers. Preferred embodiments of the carrier 12, intermediate layer 14, release layer 16, and metal layer 18 will be described below.
[0040] As described above, the carrier 12 is preferably composed of glass, silicon, metal, ceramics, or a combination thereof. When glass is used as the carrier 12, it has advantages such as being lightweight, having a low coefficient of thermal expansion, high insulating properties, being rigid and having a flat surface, which allows the surface of various layers laminated on the carrier 12 to be extremely smooth. Furthermore, when the carrier 12 is glass, it has advantages such as having surface flatness (coplanarity) that is advantageous for forming fine circuits, and having chemical resistance in desmear in the wiring manufacturing process and in various plating processes. Preferred examples of glass constituting the carrier 12 include quartz glass, borosilicate glass, alkali-free glass, soda-lime glass, aluminosilicate glass, and combinations thereof, more preferably alkali-free glass, soda-lime glass, and combinations thereof, and particularly preferably alkali-free glass. Alkali-free glass is a glass that is substantially free of alkali metals, with silicon dioxide, aluminum oxide, boron oxide, and alkaline earth metal oxides such as calcium oxide and barium oxide as its main components, and further containing boric acid. This alkali-free glass has the advantage of minimizing glass warping during heating processes because its thermal expansion coefficient is low and stable in the range of 3 ppm / K to 5 ppm / K over a wide temperature range from 0°C to 350°C.
[0041] The silicon-based carrier 12 can be any silicon containing the element Si, such as SiO 2Substrates such as SiN substrates, Si single-crystal substrates, and Si polycrystalline substrates can be used. Preferred examples of metals constituting the carrier 12 include copper, titanium, nickel, stainless steel, and aluminum. Preferred examples of ceramics constituting the carrier 12 include alumina, zirconia, silicon nitride, aluminum nitride, and various other fine ceramics. More preferably, from the viewpoint of preventing warping of the coreless support due to heating when mounting semiconductor elements, the material has a coefficient of thermal expansion (CTE) of less than 25 ppm / K (typically 1.0 ppm / K or more and 23 ppm / K or less), and examples of such materials include the glass, silicon, metal and ceramics mentioned above. Furthermore, from the viewpoint of handling and ensuring flatness when mounting chips, the carrier 12 preferably has a Vickers hardness of 100 HV or more, and more preferably 150 HV or more and 2500 HV or less. As a material that satisfies these characteristics, the carrier 12 is preferably composed of glass, silicon, metal or ceramics.
[0042] The carrier 12 may take the form of a sheet, film, or plate. Alternatively, the carrier 12 may be a laminate of these sheets, films, and plates. For example, the carrier 12 may function as a rigid support such as a glass plate, ceramic plate, silicon wafer, or metal plate, or it may be a non-rigid form such as a metal foil. According to a preferred embodiment of the present invention, the carrier 12 is disc-shaped with a diameter of 100 mm or more, and more preferably disc-shaped with a diameter of 200 mm or more and 450 mm or less. The carrier 12 (e.g., a Si single crystal substrate) may have a notch or orientation flat (also called an orientation flat) to indicate a reference point for the crystal orientation. Generally, an orientation flat is formed when the diameter of the carrier 12 is 200 mm or less, and a notch is formed when the diameter is 200 mm or more. According to another preferred embodiment of the present invention, the carrier 12 is rectangular with a short side of 100 mm or more, and more preferably with a short side of 150 mm or more and 650 mm or less. The rectangular carrier 12 may have a long side that is sufficiently longer than its short side, but preferably the long side is 200 mm or more and 650 mm or less.
[0043] The intermediate layer 14 is an optional layer that intervenes between the carrier 12 and the release layer 16 and contributes to ensuring the adhesion between the carrier 12 and the release layer 16. Examples of the metal constituting the intermediate layer 14 include Cu, Ti, Al, Nb, Zr, Cr, W, Ta, Co, Ag, Ni, In, Sn, Zn, Ga, Mo, and combinations thereof (hereinafter sometimes referred to as metal M), preferably Cu, Ti, Al, Nb, Zr, Cr, W, Ta, Co, Ag, Ni, Mo, and combinations thereof, more preferably Cu, Ti, Zr, Al, Cr, W, Ni, Mo, and combinations thereof, still more preferably Cu, Ti, Al, Cr, Ni, Mo, and combinations thereof, and particularly preferably Cu, Ti, Al, Ni, and combinations thereof. The intermediate layer 14 may be a pure metal or an alloy. The metal constituting the intermediate layer 14 may contain impurities resulting from raw material components, film formation processes, etc. Also, although not particularly limited, when the intermediate layer 14 is exposed to the atmosphere after film formation, the presence of oxygen mixed therein due to this is acceptable. The upper limit of the content of the above metal is not particularly limited and may be 100 atomic %. The intermediate layer 14 is preferably a layer formed by a physical vapor deposition (PVD) method, more preferably a layer formed by sputtering. The intermediate layer 14 is particularly preferably a layer formed by a magnetron sputtering method using a metal target from the viewpoint of the uniformity of the film thickness distribution. The thickness of the intermediate layer 14 is preferably 10 nm or more and 1000 nm or less, more preferably 30 nm or more and 800 nm or less, still more preferably 60 nm or more and 600 nm or less, and particularly preferably 100 nm or more and 400 nm or less. By setting the thickness in this way, it becomes possible to obtain an intermediate layer having the same roughness as the carrier. This thickness is a value measured by analyzing the cross-section of the layer with an energy dispersive X-ray spectrometer (TEM-EDX) of a transmission electron microscope.
[0044] The intermediate layer 14 may be a single layer or a layer of two or more layers. When the intermediate layer 14 is a single layer, it is preferable that the intermediate layer 14 consists of a layer containing a metal composed of Cu, Al, Ti, Ni, or a combination thereof (e.g., an alloy or an intermetallic compound), more preferably Al, Ti, or a combination thereof (e.g., an alloy or an intermetallic compound), and even more preferably a layer mainly containing Al or a layer mainly containing Ti. On the other hand, when using a metal or alloy that does not have sufficiently high adhesion to the carrier 12 for the intermediate layer 14, it is preferable to have a two-layer intermediate layer 14. That is, by providing a layer made of a metal (e.g., Ti) or alloy with excellent adhesion to the carrier 12 adjacent to the carrier 12, and providing a layer made of a metal (e.g., Cu) or alloy with poor adhesion to the carrier 12 adjacent to the release layer 16, the adhesion to the carrier 12 can be improved. Therefore, a preferred example of a two-layer configuration for the intermediate layer 14 is a laminated structure consisting of a Ti-containing layer adjacent to the carrier 12 and a Cu-containing layer adjacent to the release layer 16. Furthermore, since changing the balance of constituent elements and thickness of each layer in the two-layer configuration also changes the release strength, it is preferable to appropriately adjust the constituent elements and thickness of each layer. In this specification, the category of "metal M-containing layer" includes alloys containing elements other than metal M, as long as they do not impair the release properties of the carrier. Therefore, the intermediate layer 14 can also be said to be a layer mainly containing metal M. From the above, the metal M content in the intermediate layer 14 is preferably 50 atomic% to 100 atomic%, more preferably 60 atomic% to 100 atomic%, even more preferably 70 atomic% to 100 atomic%, particularly preferably 80 atomic% to 100 atomic%, and most preferably 90 atomic% to 100 atomic%.
[0045] When the intermediate layer 14 is made of an alloy, a preferred example of an alloy is a Ni alloy. The Ni alloy preferably has a Ni content of 45% to 98% by weight, more preferably 55% to 90% by weight, and even more preferably 65% to 85% by weight. A preferred Ni alloy is an alloy of Ni and at least one selected from the group consisting of Cr, W, Ta, Co, Cu, Ti, Zr, Si, C, Nd, Nb, and La, and more preferably an alloy of Ni and at least one selected from the group consisting of Cr, W, Cu, and Si. When the intermediate layer 14 is a Ni alloy layer, it is particularly preferable from the viewpoint of uniformity of film thickness distribution that the layer is formed by a magnetron sputtering method using a Ni alloy target.
[0046] The release layer 16 is a layer that enables or facilitates the release of the carrier 12 and, if present, the intermediate layer 14. The release layer 16 may be removable by a method that applies physical force, or it may be removable by a laser method (laser lift-off, LLO). If the release layer 16 is made of a material that can be removed by laser lift-off, the release layer 16 may be made of a resin whose interfacial adhesion strength decreases when irradiated with a laser beam after curing, or it may be a layer of silicon, silicon carbide, metal oxide, etc. that is modified by laser beam irradiation. Furthermore, the release layer 16 may be either an organic release layer or an inorganic release layer. Examples of organic components used in the organic release layer include nitrogen-containing organic compounds, sulfur-containing organic compounds, carboxylic acids, etc. Examples of nitrogen-containing organic compounds include triazole compounds, imidazole compounds, etc. On the other hand, examples of inorganic components used in the inorganic release layer include metal oxides or metal oxynitrides containing at least one of Ni, Mo, Co, Cr, Fe, Ti, W, P, Zn, Cu, Al, Nb, Zr, Ta, Ag, In, Sn, or Ga, or a carbon layer. Among these, the release layer 16 is particularly preferably a carbon-containing layer, i.e., a layer mainly containing carbon, from the viewpoint of ease of release and film formation, more preferably a layer mainly composed of carbon or hydrocarbons, and even more preferably a layer made of amorphous carbon, which is a hard carbon film. In this case, the carbon concentration of the release layer 16 (i.e., the carbon-containing layer) measured by XPS is preferably 60 atomic% or more, more preferably 70 atomic% or more, even more preferably 80 atomic% or more, and particularly preferably 85 atomic% or more. The upper limit of the carbon concentration is not particularly limited and may be 100 atomic%, but 98 atomic% or less is practical. The release layer 16 may contain impurities (for example, oxygen, hydrogen, etc., derived from the surrounding environment such as the atmosphere). Furthermore, due to the film formation method used for the metal layer 18 and other materials, metal atoms of types other than the metal contained in the release layer 16 may be mixed into the release layer 16.When a carbon-containing layer is used as the release layer 16, it exhibits low interdiffusivity and reactivity with carriers. Even when subjected to press working at temperatures exceeding 300°C, it prevents the formation of metallic bonds between the metal layer and the bonding interface due to high-temperature heating, thus maintaining a state where carrier peeling and removal is easy. It is preferable that this release layer 16 is also formed by a vapor phase method such as sputtering, in terms of suppressing excessive impurities in the release layer 16 and enabling continuous productivity with the deposition of an optional intermediate layer 14. When a carbon-containing layer is used as the release layer 16, its thickness is preferably 1 nm to 20 nm, and more preferably 1 nm to 10 nm. By setting the thickness to this extent, it is possible to create a release layer that has a roughness equivalent to that of the carriers and possesses a release function. This thickness is measured by analyzing the layer cross-section with an energy-dispersive X-ray spectrometer (TEM-EDX) on a transmission electron microscope.
[0047] The release layer 16 may be a layer containing each of the metal oxide layer and the carbon-containing layer, or a layer containing both the metal oxide and carbon. In particular, when the laminate 10 includes the intermediate layer 14, the carbon-containing layer contributes to stable peeling of the carrier 12, and the metal oxide layer can suppress diffusion accompanying heating of the metal elements derived from the intermediate layer 14 and the metal layer 18. As a result, stable peelability can be maintained even after heating at a high temperature of, for example, 350 °C or higher. The metal oxide layer is preferably a layer containing an oxide of a metal composed of Cu, Ti, Al, Nb, Zr, Cr, W, Ta, Co, Ag, Ni, In, Sn, Zn, Ga, Mo, or a combination thereof. The metal oxide layer is particularly preferably a layer formed by a reactive sputtering method in which sputtering is performed in an oxidizing atmosphere using a metal target, because the film thickness can be easily controlled by adjusting the film formation time. The thickness of the metal oxide layer is preferably 0.1 nm or more and 100 nm or less. The upper limit value of the thickness of the metal oxide layer is more preferably 60 nm or less, still more preferably 30 nm or less, and particularly preferably 10 nm or less. This thickness is a value measured by analyzing the layer cross section with an energy dispersive X-ray spectrometer (TEM-EDX) of a transmission electron microscope. At this time, the order in which the metal oxide layer and the carbon layer are laminated as the release layer 16 is not particularly limited. Further, the release layer 16 may exist in a mixed phase state (that is, a layer containing both the metal oxide and carbon) in which the boundary between the metal oxide layer and the carbon-containing layer is not clearly specified.
[0048] Similarly, from the viewpoint of maintaining stable peelability even after heat treatment at a high temperature, the release layer 16 may be a metal-containing layer in which the surface on the side adjacent to the metal layer 18 is a fluorinated surface and / or a nitrided surface. In the metal-containing layer, it is preferable that a region (hereinafter referred to as “(F + N) region”) in which the sum of the fluorine content and the nitrogen content is 1.0 atomic% or more exists over a thickness of 10 nm or more, and the (F + N) region is preferably present on the metal layer 18 side of the metal-containing layer. The thickness of the (F + N) region (SiO 2The (converted) value is determined by performing elemental analysis of the laminate 10 in the depth direction using XPS. The fluorinated or nitrided surface can preferably be formed by reactive ion etching (RIE) or reactive sputtering. On the other hand, the metal elements contained in the metal-containing layer preferably have a negative standard electrode potential. Preferred examples of metal elements contained in the metal-containing layer include Cu, Ag, Sn, Zn, Ti, Al, Nb, Zr, W, Ta, Mo, and combinations thereof (e.g., alloys and intermetallic compounds). The content of metal elements in the metal-containing layer is preferably 50 atomic% or more and 100 atomic% or less. The metal-containing layer may be a single layer consisting of one layer, or a multilayer consisting of two or more layers. The overall thickness of the metal-containing layer is preferably 10 nm to 1000 nm, more preferably 30 nm to 500 nm, even more preferably 50 nm to 400 nm, and particularly preferably 100 nm to 300 nm. The thickness of the metal-containing layer itself is determined by analyzing the cross-section of the layer with an energy-dispersive X-ray spectrometer (TEM-EDX) on a transmission electron microscope.
[0049] Alternatively, the release layer 16 may be a metal oxynitride-containing layer instead of a carbon layer or the like. The surface of the metal oxynitride-containing layer opposite to the carrier 12 (i.e., the metal layer 18 side) preferably contains at least one metal oxynitride selected from the group consisting of TaON, NiON, TiON, NiWON, and MoON. Furthermore, in order to ensure adhesion between the carrier 12 and the metal layer 18, the surface of the metal oxynitride-containing layer on the carrier 12 side preferably contains at least one selected from the group consisting of Cu, Ti, Ta, Cr, Ni, Al, Mo, Zn, W, TiN, and TaN. This suppresses the number of foreign particles on the surface of the metal layer 18, improves circuit formation, and makes it possible to maintain stable release strength even after heating at high temperatures for a long time. The thickness of the metal oxynitride-containing layer is preferably 5 nm to 500 nm, more preferably 10 nm to 400 nm, even more preferably 20 nm to 200 nm, and particularly preferably 30 nm to 100 nm. This thickness is determined by analyzing the cross-section of the layer with an energy-dispersive X-ray spectrometer (TEM-EDX) on a transmission electron microscope.
[0050] The metal layer 18 is a layer made of metal. The metal layer 18 may be a single layer or a layer of two or more. When the metal layer 18 is made up of two or more layers, the metal layer 18 can be configured such that each metal layer from the first metal layer to the mth metal layer (where m is an integer of 2 or more) is sequentially stacked on the side of the release layer 16 opposite to the carrier 12. The total thickness of the metal layer 18 is preferably 1 nm to 2000 nm, more preferably 100 nm to 1500 nm, more preferably 200 nm to 1000 nm, even more preferably 300 nm to 800 nm, and particularly preferably 350 nm to 500 nm. The thickness of the metal layer 18 is measured by analyzing the cross-section of the layer with an energy-dispersive X-ray spectrometer (TEM-EDX) on a transmission electron microscope. Below, an example in which the metal layer 18 is made up of two layers, a first metal layer and a second metal layer, will be described.
[0051] The first metal layer preferably provides the laminate 10 with desired functions such as an etching stopper function and an anti-reflective function. Preferred examples of metals constituting the first metal layer include Ti, Al, Nb, Zr, Cr, W, Ta, Co, Ag, Ni, Mo, and combinations thereof, more preferably Ti, Zr, Al, Cr, W, Ni, Mo, and combinations thereof, even more preferably Ti, Al, Cr, Ni, Mo, and combinations thereof, and particularly preferably Ti, Mo, and combinations thereof. These elements have the property of being poorly soluble in flash etching solutions (e.g., copper flash etching solutions), and as a result, can exhibit excellent chemical resistance to flash etching solutions. Therefore, the first metal layer is less susceptible to etching by flash etching solutions than the second metal layer described later, and thus can function as an etching stopper layer that can delay the progress of etching. Furthermore, since the metal constituting the first metal layer also has the function of preventing light reflection, the first metal layer can also function as an anti-reflective layer to improve visibility in image inspection (for example, automated image inspection (AOI)). The first metal layer may be a pure metal or an alloy. The metal constituting the first metal layer may contain impurities resulting from the raw material components or the film formation process. Also, there is no particular upper limit to the content of the above metal, and it may be 100 atomic percent. The first metal layer is preferably a layer formed by physical vapor deposition (PVD), and more preferably a layer formed by sputtering. The thickness of the first metal layer is preferably 1 nm to 500 nm, more preferably 10 nm to 400 nm, even more preferably 30 nm to 300 nm, and particularly preferably 50 nm to 200 nm.
[0052] Preferred examples of metals constituting the second metal layer include transition elements of Groups 4, 5, 6, 9, 10, and 11, Al, and combinations thereof (e.g., alloys and intermetallic compounds). More preferably, transition elements of Groups 4 and 11, Al, Nb, Co, Ni, Mo, and combinations thereof. Even more preferably, transition elements of Group 11, Ti, Al, Mo, and combinations thereof. Particularly preferred are Cu, Ti, Mo, and combinations thereof. Most preferably, Cu. The second metal layer may be manufactured by any method, for example, a metal foil formed by wet deposition methods such as electroless metal plating and electrolytic metal plating, physical vapor deposition (PVD) methods such as sputtering and vacuum deposition, chemical vapor deposition, or a combination thereof. A particularly preferred second metal layer is a metal layer formed by physical vapor deposition (PVD) methods such as sputtering or vacuum deposition, from the viewpoint of easily accommodating fine pitch reduction through ultrathinning, and most preferably a metal layer manufactured by sputtering. Furthermore, while an unroughened metal layer is preferred for the second metal layer, it may also be subjected to secondary roughening treatments such as preliminary roughening, soft etching, cleaning, or oxidation-reduction treatment, as long as it does not hinder wiring pattern formation. From the viewpoint of accommodating fine pitch reduction, the thickness of the second metal layer is preferably 10 nm to 1000 nm, more preferably 20 nm to 900 nm, even more preferably 30 nm to 700 nm, even more preferably 50 nm to 600 nm, particularly preferably 70 nm to 500 nm, and most preferably 100 nm to 400 nm. Metal layers with thicknesses within this range are preferably manufactured by sputtering from the viewpoint of in-plane uniformity of film thickness and productivity in sheet or roll form.
[0053] When the metal layer 18 has a single-layer structure, it is preferable to use the second metal layer described above as the metal layer 18. On the other hand, when the metal layer 18 has an n-layer structure (where n is an integer of 3 or more), it is preferable to have the first metal layer to the (n-1)th metal layer of the metal layer 18 have the configuration of the first metal layer described above, and the outermost layer of the metal layer 18, i.e., the nth metal layer, have the configuration of the second metal layer described above.
[0054] The intermediate layer 14 (if present), the release layer 16, and the metal layer 18 are preferably all physical vapor deposition (PVD) films, i.e., films formed by the physical vapor deposition (PVD) method, and more preferably sputtered films, i.e., films formed by the sputtering method.
[0055] It is preferable that the metal layer 18, an optional intermediate layer 14, and an optional release layer 16 (i.e., at least the metal layer 18, for example, the metal layer 18 and the intermediate layer 14) extend to the end face of the carrier 12 so that the end face is covered. In other words, it is preferable that not only the surface of the carrier 12 but also the end face is covered with at least the metal layer 18. By covering the end face as well, it is possible to prevent chemical solutions from penetrating the carrier 12 during the manufacturing process of the wiring board, and it is also possible to firmly prevent chipping due to peeling at the side edges when handling the laminate 10, i.e., chipping of the film on the release layer 16 (i.e., the metal layer 18). The covered area on the end face of the carrier 12 is preferably an area of 0.1 mm or more, more preferably an area of 0.2 mm or more, and even more preferably extends over the entire end face of the carrier 12, in the thickness direction (i.e., the direction perpendicular to the carrier surface) from the surface of the carrier 12.
[0056] The overall thickness of the laminate 10 is not particularly limited, but is preferably 500 μm to 3000 μm, more preferably 700 μm to 2500 μm, even more preferably 900 μm to 2000 μm, and especially preferably 1000 μm to 1700 μm. The size of the laminate 10 is not particularly limited, but is preferably 10 cm or larger in diameter or 10 cm square or larger, more preferably 20 cm or larger in diameter or 20 cm square or larger, and even more preferably 25 cm or larger in diameter or 25 cm square or larger. The upper limit of the size of the laminate 10 is not particularly limited, but a diameter of 1000 cm or 1000 cm square can be cited as one guideline for the upper limit. Furthermore, the laminate 10 is in a form that can be handled independently before and after the formation of the device layer 20.
[0057] The present invention will be further described in detail by the following examples. However, the present invention is not limited to the following examples.
[0058] Example 1: A laminate comprising a carrier, a release layer, and a device layer was prepared, and the carrier and device layer were separated according to the method of the present invention. Specifically, the procedure was as follows.
[0059] (1) Preparation of the laminate A glass sheet with a diameter of 300 mm and a thickness of 1.1 mm (material: soda-lime glass, coefficient of thermal expansion: 8.5 ppm / K) was prepared as the carrier 12. On this carrier 12, a titanium layer (thickness 50 nm) and a copper layer (thickness 200 nm) as a two-layer intermediate layer 14, an amorphous carbon layer (thickness 6 nm) as a release layer 16, and a titanium layer (thickness 100 nm) and a copper layer (thickness 300 nm) as a two-layer metal layer 18 were deposited in this order by sputtering to obtain a metal foil with a carrier. At this time, the metal layer 18 was deposited so as to extend to the end face of the carrier 12, thereby covering the end of the release layer 16.
[0060] On the metal layer 18 of the carrier-attached metal foil, an insulating layer (material: polyimide resin) with a diameter of 300 mm and a thickness of 30 μm, and a mold resin layer (material: epoxyphenol resin) with a diameter of 300 mm and a thickness of 350 μm were formed in this order as the device layer 20. In this way, a laminate 10 was obtained having the release layer 16 and the device layer 20 in order on the carrier 12.
[0061] (2) Trimming of the device layer The peripheral edge of the device layer 20 was trimmed from the obtained laminate 10 using a cutter. This trimming was performed by making an incision that passed through a position 10 mm inside the contour of the device layer 20 when the laminate 10 was viewed from above.
[0062] (3) Six thermosetting resin films with a diameter of 300 mm (ABF-GX92, manufactured by Ajinomoto Fine Techno Co., Ltd., thickness 35 μm, thermal expansion coefficient: 39 ppm / K) were laminated as a resin layer 22 on the carrier 12 side surface of the resin layer laminate 10 (the surface opposite to the device layer 20). Then, lamination was performed for 60 seconds using a vacuum laminator (MVLP-500 / 600, manufactured by Meiki Seisakusho Co., Ltd.) at a temperature of 100°C and a pressure of 0.55 MPa. In this way, a resin layer 22 with a thickness of 210 μm was formed, and a resin layer laminate 24 was obtained.
[0063] (4) Curing treatment of the resin layer The resin-coated laminate 24 obtained was placed in an oven and heated at a temperature of 130°C for 30 minutes. Subsequently, the oven temperature was raised to 170°C and heated for another 30 minutes. After the heating treatment, the resin-coated laminate 24 was allowed to cool at room temperature (25°C). In this way, the resin layer 22 was cured.
[0064] (5) Separation of carrier and device layer Due to the curing treatment described above, the carrier 12 was pulled in a direction that followed the shrinkage of the resin layer 22, causing the shape of the resin-coated laminate 24 to change so that the outer surface of the carrier 12 became concave. As a result, the carrier 12 and the device layer 20 separated at the location of the release layer 16. Upon observation of the carrier 12 and the device layer 20 after separation, it was confirmed that no damage had occurred to either the carrier 12 or the device layer 20.
[0065] 10 Laminate 12 Carrier 14 Interlayer 16 Release layer 18 Metal layer 20 Device layer 20a First redistribution layer 20b Molding resin layer 20c Second redistribution layer 22 Resin layer 24 Laminate with resin layer 26 Reinforcement sheet C Chip P Pillar
Claims
1. A method for manufacturing a substrate, comprising: a step of preparing a laminate having a release layer and a device layer in order on a carrier; a step of laminating a resin layer containing a curable resin on the carrier-side surface of the laminate to obtain a resin-layered laminate; a step of curing the resin-layered laminate with the resin-layered laminate to shrink the resin layer by curing the curable resin, thereby changing the shape of the carrier or the resin-layered laminate by pulling the carrier in a direction that follows the shrinkage of the resin layer; and a step of utilizing the change in the shape of the carrier to generate shear stress between the carrier and the device layer, thereby peeling the device layer from the resin-layered laminate at the position of the release layer.
2. The method for manufacturing a substrate according to claim 1, wherein the device layer is peeled from the resin-coated laminate without using mechanical peeling means, but solely by utilizing the change in the shape of the carrier.
3. The method for manufacturing a substrate according to claim 1 or 2, further comprising the step of performing a trimming process on the device layer before laminating the resin layer, wherein the trimming process is performed by making cuts that pass inside the contour of the device layer when the laminate is viewed from above, and penetrate the device layer when the laminate is viewed in cross-section.
4. The method for manufacturing a substrate according to claim 1 or 2, further comprising the step of laminating a reinforcing sheet on the device layer before performing the curing treatment of the curable resin.
5. The method for manufacturing a substrate according to claim 4, wherein when the shape of the carrier is changed, the reinforcing sheet and the device layer supported by it are not bent, and the device layer is peeled off from the resin-coated laminate by changing the shape of the portion of the resin-coated laminate other than the device layer.
6. The method for manufacturing a substrate according to claim 1 or 2, wherein the laminate further comprises a metal layer provided between the release layer and the device layer.
7. The method for manufacturing a substrate according to claim 1 or 2, further comprising the step of applying a primer treatment to the carrier before laminating the resin layer.
8. The method for manufacturing a substrate according to claim 1 or 2, wherein the curable resin includes a thermosetting resin.
9. The method for manufacturing a substrate according to claim 8, wherein the curing treatment includes a heat treatment of the resin layer and a subsequent heat dissipation treatment, and the maximum difference between the temperature of the heat treatment and the ambient temperature of the heat dissipation treatment is 50°C or more.
10. The method for manufacturing a substrate according to claim 8, wherein the thermosetting resin has a coefficient of thermal expansion of 10 ppm / K or more.
11. The method for manufacturing a substrate according to claim 8, wherein the thermosetting resin comprises at least one resin selected from the group consisting of (meth)acrylic resins, vinyl resins, allyl resins, melamine resins, urethane resins, epoxy resins, silicone resins, polyester resins, polyamic acid resins, polyimide resins, styrene maleic acid resins, styrene maleic anhydride resins, maleimide resins, and cyanate resins.
12. The method for manufacturing a substrate according to claim 1 or 2, wherein the curable resin has a maximum curing shrinkage rate of 0.0010% or more, as measured in accordance with JIS K 6941:2019.
13. The method for manufacturing a substrate according to claim 1 or 2, wherein the resin layer is provided in the form of a resin film.
14. The method for manufacturing a substrate according to claim 13, wherein the resin layer has a thickness of 0.01 μm or more and 1 mm or less.
15. The method for manufacturing a substrate according to claim 1 or 2, wherein the carrier is composed of glass, silicon, metal, or ceramics.
16. The method for manufacturing a substrate according to claim 1 or 2, wherein the carrier has a thickness of 3000 μm or less.
17. The method for manufacturing a substrate according to claim 1 or 2, wherein the device layer includes a wiring layer, an electronic element provided on the wiring layer, and a molded resin layer that embeds the electronic element.
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