Three-level power test circuit
By designing controllable switch and capacitor branch connections, the problem of traditional three-level power testing schemes being unable to switch connection modes is solved, achieving flexible bus connections and improving the flexibility and applicability of testing.
Patent Information
- Application Number
- CN202422841673.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-20
- Publication Date
- 2025-11-04
- Estimated Expiration
- 2034-11-20
AI Technical Summary
Traditional three-level power testing solutions cannot be switched to full bus connection or arbitrary positive and negative bus connection modes according to actual needs, resulting in insufficient flexibility and applicability of the testing platform.
Design a three-level power test circuit that connects a switching branch and a controllable capacitor branch to achieve flexible switching between positive, negative and intermediate potentials. The switching branch includes an insulated gate bipolar transistor and a diode, and the capacitor branch includes a parallel capacitor. Switching between different bus connection modes is achieved through switch control.
It enables flexible switching of test connection modes, meeting the requirements of full busbar connection and arbitrary positive and negative half busbar connection, significantly improving the flexibility and applicability of testing.
Smart Images
Figure CN223513270U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of power testing technology, and in particular to a three-level power testing circuit. Background Technology
[0002] Three-level power devices are widely used in photovoltaic power generation, wind power generation, and energy storage systems due to their high efficiency, low harmonic distortion, and good voltage balance capabilities. These applications place stringent demands on the performance of power devices, requiring not only high reliability and long lifespan, but also stable power output and excellent energy efficiency ratios under complex and variable operating conditions. Therefore, a comprehensive performance evaluation of three-level power devices is one of the key steps to ensure their stable operation in various systems.
[0003] Performance evaluation typically encompasses multiple test items, including static characteristic testing, dynamic response testing, and reliability testing. Static characteristic testing primarily focuses on the voltage, current characteristics, and temperature stability of a device under specific conditions; dynamic response testing emphasizes evaluating the device's response speed and control accuracy under rapidly changing load or input conditions; while reliability testing aims to simulate stress conditions in long-term operating environments to verify the device's durability and failure rate.
[0004] Traditional three-level power testing schemes, such as Figure 1 As shown, a high-voltage source is typically used to provide bus voltage, which is applied to the full bus or half-bus capacitors. After the bus capacitors are electrically connected to the power board, the entire test platform is completed. However, this test platform cannot be switched to a full bus connection or any positive or negative bus connection mode according to actual needs. Utility Model Content
[0005] To solve the above technical problems, this utility model provides a three-level power testing circuit.
[0006] The technical problem solved by this utility model can be achieved by the following technical solution:
[0007] A three-level power testing circuit includes:
[0008] The switch branch is connected between the positive and negative potentials;
[0009] A first capacitor branch, one end of which is controllably connected to the positive potential, and the other end of which is controllably connected to an intermediate potential;
[0010] The second capacitor branch has one end controllably connected to the intermediate potential and the other end controllably connected to the negative potential.
[0011] Preferably, the switch branch includes:
[0012] A first transistor, the drain of which is connected to the positive potential, and the source of which is connected to the first node;
[0013] The second transistor has its drain connected to the first node and its source connected to the voltage output terminal.
[0014] The third transistor has its drain connected to the voltage output terminal and its source connected to the second node.
[0015] A fourth transistor, the drain of which is connected to the second node, and the source of which is connected to the negative potential.
[0016] Preferably, the first transistor, the second transistor, the third transistor, and the fourth transistor are all insulated-gate bipolar transistors.
[0017] Preferably, the switch branch further includes:
[0018] A first diode, wherein the anode of the first diode is connected to the intermediate potential, and the cathode of the first diode is connected to the first node;
[0019] The second diode has its anode connected to the second node and its cathode connected to the intermediate potential.
[0020] Preferably, the switch branch further includes:
[0021] The first inductor is connected between the positive potential and the first node.
[0022] Preferably, the first capacitor branch includes:
[0023] The first capacitor and the second bus capacitor are connected in parallel.
[0024] Preferably, the second capacitor branch includes:
[0025] The third capacitor and the fourth bus capacitor are connected in parallel.
[0026] Preferably, it further includes:
[0027] The first switch is connected between the positive potential and the first capacitor branch;
[0028] The second switch is connected between the first capacitor branch and the intermediate potential;
[0029] The third switch is connected between the intermediate potential and the second capacitor branch;
[0030] The fourth switch is connected between the second capacitor branch and the negative electrode potential.
[0031] Preferably, it further includes:
[0032] A power board, wherein the switch branch is soldered to the power board, and a plurality of first power terminals are also soldered to the power board, and the plurality of first power terminals are connected one-to-one with each power element of the switch branch;
[0033] A capacitor board is provided, on which the first capacitor branch and the second capacitor branch are soldered. The capacitor board is also provided with a plurality of second power terminals, which are connected one-to-one with each capacitor element of the first capacitor branch and the second capacitor branch.
[0034] Preferably, the power board is further soldered with a plurality of combined terminals, which are electrically connected to the corresponding first power terminal and second power terminal.
[0035] The advantages or beneficial effects of this utility model's technical solution are as follows:
[0036] This invention achieves flexible switching of test connection modes by controllably connecting the first capacitor branch and the second capacitor branch between the positive potential, intermediate potential and negative potential. It can meet the connection requirements of the entire busbar and adapt to the connection requirements of any positive or negative half busbar, thereby greatly enhancing the flexibility and practicality of the test. Attached Figure Description
[0037] Figure 1 This is a schematic diagram of a three-level power testing circuit in the prior art;
[0038] Figure 2 This is a schematic diagram of a three-level power testing circuit in a preferred embodiment of the present invention.
[0039] Figure 3 In a preferred embodiment of this utility model, the PCB layout of the first to fourth transistors is shown. Detailed Implementation
[0040] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.
[0041] It should be noted that, unless otherwise specified, the embodiments and features described in these embodiments can be combined with each other.
[0042] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, but this is not intended to limit the present invention.
[0043] In a preferred embodiment of this utility model, based on the above-mentioned problems existing in the prior art, a three-level power testing circuit is provided, such as... Figure 2 As shown, it includes:
[0044] Switch branch 1 is connected between the positive potential DC+ and the negative potential DC-;
[0045] First capacitor branch 2, one end of the first capacitor branch 2 can be controlled to be connected to the positive potential DC+, and the other end of the first capacitor branch 2 can be controlled to be connected to the intermediate potential N.
[0046] The second capacitor branch 3 has one end controllably connected to the intermediate potential N and the other end controllably connected to the negative potential DC-.
[0047] Specifically, the three-level power test circuit of this utility model embodiment mainly includes a switch branch 1, a first capacitor branch 2, and a second capacitor branch 3 connecting the positive potential DC+ and the negative potential DC-. One end of the first capacitor branch 2 is connected to the positive potential DC+ in a controllable manner, and the other end is connected to the intermediate potential N in a controllable manner. It can flexibly connect or disconnect the first capacitor branch 2 from the positive potential DC+ and the intermediate potential N according to the test requirements.
[0048] The design of the second capacitor branch 3 is similar. One end of it is controllably connected to the intermediate potential N, and the other end is connected to the negative potential DC-. The connection state of the second capacitor branch 3 with the intermediate potential N and the negative potential DC- can be flexibly controlled according to the test requirements.
[0049] Different bus connection modes can be achieved by controlling the connection states of the first capacitor branch 2 and the second capacitor branch:
[0050] When the first capacitor branch 2 is connected to the positive potential DC+ and the intermediate potential N, while the second capacitor branch 3 is disconnected from the intermediate potential N and the negative potential DC-, the circuit is in the positive half-bus connection mode.
[0051] When the first capacitor branch 2 is disconnected from the positive potential DC+ and the intermediate potential N, while the second capacitor branch 3 is connected to the intermediate potential N and the negative potential DC-, the circuit is in the negative half-bus connection mode.
[0052] When the first capacitor branch 2 is connected to the positive potential DC+ and the intermediate potential N, and the second capacitor branch 3 is also connected to the intermediate potential N and the negative potential DC-, the circuit is in full bus connection mode.
[0053] The three-level power test circuit of this embodiment can quickly modify the positive and negative capacitors of the power board. It is mainly used in dynamic testing. Without changing the original test platform connection method, the controllable switching of the circuit bus capacitor can be quickly completed by simply switching the connection mode of the capacitor part. It can flexibly switch to the full bus connection or arbitrary positive and negative bus connection mode according to the actual test requirements, thereby significantly improving the flexibility and applicability of the test.
[0054] Compared to traditional circuits where the power board and bus capacitor are directly connected, the circuit in this embodiment has a smaller inductance, lower cost, and adjustable power circuit inductance to simulate different application scenarios and achieve different testing objectives.
[0055] In a preferred embodiment, the switch branch 1 includes:
[0056] The first transistor T1 has its drain connected to the positive potential DC+ and its source connected to the first node J1.
[0057] The drain of the second transistor T2 is connected to the first node J1, and the source of the second transistor T2 is connected to the voltage output terminal AC.
[0058] The third transistor T3 has its drain connected to the voltage output terminal AC and its source connected to the second node J2.
[0059] The fourth transistor T4 has its drain connected to the second node J2 and its source connected to the negative potential DC-.
[0060] Specifically, the gates of the first to fourth transistors are used to receive external drive signals, so as to control the conduction or cutoff of each transistor under the action of the drive signals, thereby realizing the switching of current on / off and direction.
[0061] In a preferred embodiment, the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 are all insulated gate bipolar transistors.
[0062] Specifically, an Insulated Gate Bipolar Transistor (IGBT) is a composite fully controllable voltage-driven power semiconductor device composed of a bipolar junction transistor (BJT) and an insulated gate field-effect transistor (MOSFET). It combines the advantages of high input impedance of MOSFET and low on-state voltage drop of GTR, making it suitable for high-voltage and high-current applications.
[0063] In a preferred embodiment, the switch branch 1 further includes:
[0064] The first diode D1 has its anode connected to the intermediate potential N and its cathode connected to the first node J1.
[0065] The anode of the second diode D2 is connected to the second node J2, and the cathode of the second diode D2 is connected to the intermediate potential N.
[0066] Specifically, in this embodiment, a first diode D1 and a second diode D2 are connected in series between the second node J2 and the first node J1 of the switch branch 1, and the connection point of the first diode D1 and the second diode D2 is connected to the intermediate potential N.
[0067] In this embodiment, the intermediate potential N is zero potential.
[0068] In a preferred embodiment, the switch branch 1 further includes:
[0069] The first inductor L1 is connected between the positive potential DC+ and the first node J1.
[0070] Specifically, the first inductor L1 is charged through the first capacitor branch 2, or the second capacitor branch 3, or the first capacitor branch 2 and the second capacitor branch 3.
[0071] In a preferred embodiment, the first capacitor branch 2 includes:
[0072] The first capacitor C5 and the second bus capacitor C6 are connected in parallel.
[0073] In this embodiment, the second bus capacitor C6 can be a single capacitor or multiple capacitors connected in parallel.
[0074] Preferably, the second bus capacitor C6 is a polarized capacitor.
[0075] In a preferred embodiment, the second capacitor branch 3 includes:
[0076] The third capacitor C7 and the fourth bus capacitor C8 are connected in parallel.
[0077] In this embodiment, the fourth bus capacitor C8 can be a single capacitor or multiple capacitors connected in parallel.
[0078] Preferably, the fourth bus capacitor C8 is a polarized capacitor.
[0079] In a preferred embodiment, it further includes:
[0080] The first switch SW1 is connected between the positive potential DC+ and the first capacitor branch 2;
[0081] The second switch SW2 is connected between the first capacitor branch 2 and the intermediate potential N;
[0082] The third switch SW3 is connected between the intermediate potential N and the second capacitor branch 3;
[0083] The fourth switch SW4 is connected between the second capacitor branch 3 and the negative potential DC-.
[0084] Specifically, in this embodiment, the bus connection mode is switched by the working states of the four switches SW1-4.
[0085] Busbar connection modes include the following three types: full busbar, positive half busbar, and negative half busbar.
[0086] The on / off states of the first to fourth switches under each connection mode are shown in Table 1 below.
[0087] Table 1. On / off states of the first to fourth switches under each connection mode.
[0088] Switch on / off state Connection mode 1 SW1, SW2, SW3, and SW4 are all closed. All busbars 2 SW1 and SW2 are closed, SW3 and SW4 are open; Positive half busbar 3 SW1 and SW2 are disconnected, while SW3 and SW4 are closed. negative half busbar
[0089] When the first switch SW1, the second switch SW2, the third switch SW3, and the fourth switch SW4 are all closed, the circuit is in full busbar connection mode.
[0090] When the first switch SW1 and the second switch SW2 are closed, and the third switch SW3 and the fourth switch SW4 are open, the circuit is in the positive half-bus connection mode.
[0091] When the first switch SW1 and the second switch SW2 are open, and the third switch SW3 and the fourth switch SW4 are closed, the circuit is in the negative half bus connection mode.
[0092] In a preferred embodiment, such as Figure 3 As shown, it also includes:
[0093] Power board 4, switch branch 1 is soldered on power board 1, and several first power terminals 5 are also soldered on power board 4. The several first power terminals 5 are connected to each power element of switch branch 1 in a corresponding manner.
[0094] A capacitor board (not shown in the figure) is provided. The first capacitor branch 2 and the second capacitor branch 3 are soldered onto the capacitor board. Several second power terminals are also soldered onto the capacitor board. The several second power terminals are connected to each capacitor element of the first capacitor branch 2 and the second capacitor branch 3 in a corresponding manner.
[0095] Furthermore, it may also include: a driver board, on which a driver circuit is soldered, the driver circuit being used to output a driver signal to the gates of the first transistor T1, the second transistor T2, the third transistor T3 and the fourth transistor T4 to control the on / off state of the four transistors.
[0096] In a preferred embodiment, a plurality of combined terminals 6 are also welded onto the power board 4, and the plurality of combined terminals 6 are electrically connected to the corresponding first power terminal 5 and second power terminal.
[0097] Specifically, by adding combination terminals at the power terminals and changing the material and length of the connection, the noise inductance of the module circuit can be adjusted, and it can be connected to the full bus or any positive and negative half bus as needed.
[0098] Specifically, the biggest difference from the traditional solution lies in the modification of the power board. The other connections of the platform are the same, that is, except that the inductors of the power board platform are fixed, the test level of the entire platform can be changed directly by switching the bus capacitors of the corresponding electrical connections of the power board.
[0099] The advantages or beneficial effects of adopting the above technical solution are as follows: This utility model realizes flexible switching of test connection mode by controllably connecting the first capacitor branch and the second capacitor branch between the positive potential, the intermediate potential and the negative potential. It can not only meet the full busbar connection requirements, but also adapt to the connection requirements of any positive or negative half busbar, thereby greatly enhancing the flexibility and practicality of the test.
[0100] The above are merely preferred embodiments of the present utility model and are not intended to limit the implementation methods and protection scope of the present utility model. Those skilled in the art should realize that any equivalent substitutions and obvious changes made using the content of this specification and illustrations should be included within the protection scope of the present utility model.
Claims
1. A three-level power testing circuit, characterized in that, include: The switch branch is connected between the positive and negative potentials; A first capacitor branch, one end of which is controllably connected to the positive potential, and the other end of which is controllably connected to an intermediate potential; The second capacitor branch has one end controllably connected to the intermediate potential and the other end controllably connected to the negative potential.
2. The three-level power testing circuit according to claim 1, characterized in that, The switch branch includes: A first transistor, the drain of which is connected to the positive potential, and the source of which is connected to the first node; The second transistor has its drain connected to the first node and its source connected to the voltage output terminal. The third transistor has its drain connected to the voltage output terminal and its source connected to the second node. A fourth transistor, the drain of which is connected to the second node, and the source of which is connected to the negative potential.
3. The three-level power testing circuit according to claim 2, characterized in that, The first transistor, the second transistor, the third transistor, and the fourth transistor are all insulated-gate bipolar transistors.
4. The three-level power testing circuit according to claim 2, characterized in that, The switch branch also includes: A first diode, wherein the anode of the first diode is connected to the intermediate potential, and the cathode of the first diode is connected to the first node; The second diode has its anode connected to the second node and its cathode connected to the intermediate potential.
5. The three-level power testing circuit according to claim 2, characterized in that, The switch branch also includes: The first inductor is connected between the positive potential and the first node.
6. The three-level power testing circuit according to claim 1, characterized in that, The first capacitor branch includes: The first capacitor and the second bus capacitor are connected in parallel.
7. The three-level power testing circuit according to claim 1, characterized in that, The second capacitor branch includes: The third capacitor and the fourth bus capacitor are connected in parallel.
8. The three-level power testing circuit according to claim 1, characterized in that, Also includes: The first switch is connected between the positive potential and the first capacitor branch; The second switch is connected between the first capacitor branch and the intermediate potential; The third switch is connected between the intermediate potential and the second capacitor branch; The fourth switch is connected between the second capacitor branch and the negative electrode potential.
9. The three-level power testing circuit according to claim 1, characterized in that, Also includes: A power board, wherein the switch branch is soldered to the power board, and a plurality of first power terminals are also soldered to the power board, and the plurality of first power terminals are connected one-to-one with each power element of the switch branch; A capacitor board is provided, on which the first capacitor branch and the second capacitor branch are soldered. The capacitor board is also provided with a plurality of second power terminals, which are connected one-to-one with each capacitor element of the first capacitor branch and the second capacitor branch.
10. The three-level power testing circuit according to claim 9, characterized in that, The power board is also welded with a number of combined terminals, which are electrically connected to the corresponding first power terminal and second power terminal.