Special test tool based on FPGA multi-interface data conversion

Abstract

The utility model belongs to the technical field of electronic information and communication, and particularly relates to a special test tool based on FPGA multi-interface data conversion, which comprises an FPGA, a high-speed interface module and a universal interface module, a protocol processing module is arranged in the FPGA, the high-speed interface module comprises two SRIO interfaces, the universal interface module comprises an SGMII interface, an Ethernet interface, an SPI interface and a UART interface, and the protocol processing module is arranged in the FPGA. Each interface is matched with a cache, the FPGA is connected with the two SRIO interfaces, and the FPGA is also connected with each cache in the universal interface module. The tool is based on the FPGA, communication between the SRIO interface and general interfaces such as the SGMII interface, the 100M Ethernet interface, the SPI interface and the UART interface can be achieved, and then communication between the SRIO interface special equipment and the special equipment with the multiple general interfaces is achieved.

Description

Technical Field

[0001] This utility model belongs to the field of electronic information and communication technology, specifically a special test fixture based on FPGA multi-interface data conversion. Background Technology

[0002] Special equipment refers to eight categories of equipment involving life safety and high risk, including boilers, pressure vessels (including gas cylinders), pressure pipelines, elevators, lifting machinery, passenger ropeways, large amusement facilities, and special-purpose motor vehicles for on-site use. To ensure the safe operation of special equipment, the state has strict regulations for all types of special equipment in three stages: production, use, and inspection and testing, implementing full-process supervision. Therefore, special equipment needs to be inspected before use. Special equipment inspection and testing devices are designed and manufactured to meet the relevant regulations and standards for special equipment, conducting performance and safety inspections and tests. When testing special equipment, the interfaces to be tested are converted into dedicated test interfaces to facilitate equipment interconnection and testing. However, current inspection and testing devices are only designed for single interfaces, resulting in poor versatility. Summary of the Invention

[0003] This invention addresses the problem that current testing and inspection devices only perform single-interface conversion by providing a dedicated testing fixture based on FPGA multi-interface data conversion.

[0004] This utility model is achieved using the following technical solution: a dedicated test fixture for multi-interface data conversion based on FPGA, comprising an FPGA, wherein the FPGA has a built-in high-speed interface module, a general interface module and a protocol processing module, the high-speed interface module includes an SRIO interface, the general interface module includes an SGMII interface, an Ethernet interface, an SPI interface and a UART interface, the SRIO interface inside the FPGA is connected to the protocol processing module, and the protocol processing module is also connected to each interface in the general interface module.

[0005] The SRIO interface of the test fixture is connected to the SRIO interface special equipment, and the SGMII interface, Ethernet interface, SPI interface and UART interface are connected to the corresponding general interface special equipment. The SRIO interface receives data from the SRIO interface special equipment. The protocol processing module determines the general interface type based on the data type and sends it to the corresponding general interface, which then sends it to the general interface special equipment. After receiving the data from the general interface special equipment, the general interface sends it to the SRIO interface, which then sends it to the SRIO interface special equipment.

[0006] This utility model has the following advantages: small size: designed as a compact structural component, easy to carry; flexible interface conversion to meet various testing needs; enhanced system scalability, allowing for the addition of more interfaces as needed; and improved hardware resource utilization. Attached Figure Description

[0007] Figure 1 This is a schematic diagram of the main structure of an FPGA.

[0008] Figure 2 This is a schematic diagram of the internal connection relationships of a general interface.

[0009] Figure 3 FPGA interface diagram Figure 1 .

[0010] Figure 4 FPGA interface diagram Figure 2 .

[0011] Figure 5 This is a schematic diagram of the SRIO interface.

[0012] Figure 6 This is a schematic diagram of the SGMII interface.

[0013] Figure 7 This is a schematic diagram of the SPI interface.

[0014] Figure 8 This is a schematic diagram of an Ethernet interface.

[0015] Figure 9 This is a schematic diagram of the UART interface. Detailed Implementation

[0016] A dedicated test fixture based on FPGA multi-interface data conversion. This fixture is based on FPGA and can realize communication between SRIO interface and general interfaces such as SGMII interface, 100M Ethernet interface, SPI interface, and UART interface, thereby realizing communication between SRIO interface special equipment and general interface special equipment.

[0017] This dedicated test fixture for FPGA-based multi-interface data conversion includes an FPGA, which integrates a high-speed interface module, a general-purpose interface module, and a protocol processing module. The FPGA allocates buffers for each interface in the general-purpose interface module. The high-speed interface module uses two SRIO interfaces, capable of receiving data from SRIO-specific devices or sending data to them. The protocol processing module processes the data from both the high-speed and general-purpose interface modules, parsing the data type from the SRIO's HELLO header to determine the general-purpose interface type. The general-purpose interface module consists of SGMII, 100Mbps Ethernet, SPI, and UART interfaces. Inside the FPGA, the SRIO interfaces connect to the protocol processing module, which in turn connects to the various buffers within the general-purpose interface module.

[0018] Figure 1 This is a schematic diagram of the composition structure of this utility model. In the uplink, the protocol processing module generates an address that is included with the frame according to the general interface type, and replaces it with the corresponding HELLO header in the high-speed interface module. In the downlink, the high-speed interface module receives data, strips off the HELLO header information, and sends it to the protocol processing module. The protocol processing module parses the data according to the address and sends it to the corresponding general interface buffer.

[0019] The functions of each module are as follows:

[0020] High-speed interface module

[0021] The high-speed interface is an SRIO interface, which connects directly to SRIO interface-specific devices via a high-speed connector to achieve communication with them. When the SRIO interface sends data to a general interface-specific device, it encapsulates the data and adds the corresponding HELLO header address parameter and packet type according to the different general interface types before sending it. After receiving data from the SRIO interface-specific device, the SRIO interface fills in the channel identifier into the relevant position in the data packet according to the address in the HELLO header. The protocol processing module then sends the data out from the corresponding channel based on the channel identifier in the data packet.

[0022] Protocol processing module

[0023] The protocol primarily defines information such as the fixed identifier in the frame header, data frame length, frame type, and address. After the high-speed interface receives data, the protocol processing module parses and processes the valid fields after removing the HELLO header from the high-speed interface, finally polls the status of each channel, and sends it to the corresponding buffer in the general interface module according to the interface address. After the general interface receives data, the protocol processing module adds the corresponding identifier field according to the protocol definition and sends it to the high-speed interface module.

[0024] General interface module

[0025] This module consists of SGMII, 100Mbps Ethernet, SPI, and UART interfaces, each with its own buffer. To facilitate interface integration, the module uses an 8-bit data width for external communication. Each interface is isolated within the module using its own buffer, ensuring timing stability between different interfaces. Figure 2 This is a schematic diagram of the internal connection relationships of the general interface module.

[0026] like Figure 3 and Figure 4 As shown, the FPGA model is XC7A100T-2FGG676I; Figure 5 As shown, the SRIO interface model is LRMS5-A288-Z1-MZ; Figure 6 As shown, the SGMII interface is a dual-row pin connector, a universal interface; as Figure 7 As shown, the SPI interface is a dual-pin header interface, which is a general-purpose interface; as Figure 8 As shown, the Ethernet interface is an RJ45 type. Figure 9 As shown, the UART interface includes a MAX3232EUE+ chip and a DB9 connector. The chip is connected to the FPGA, and then the chip is connected to external special equipment through the connector.

Claims

1. A dedicated test fixture for FPGA-based multi-interface data conversion, characterized in that: This includes an FPGA, which has built-in high-speed interface modules, general-purpose interface modules, and protocol processing modules. The high-speed interface modules include SRIO interfaces, and the general-purpose interface modules include SGMII interfaces, Ethernet interfaces, SPI interfaces, and UART interfaces. Inside the FPGA, the SRIO interface is connected to the protocol processing module, and the protocol processing module is also connected to various interfaces in the general-purpose interface modules.

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