High-voltage step-down voltage stabilizing circuit suitable for high-power synchronous rectifier

Abstract

The utility model relates to a high-voltage step-down voltage stabilizing circuit suitable for a high-power synchronous rectifier. The high-voltage step-down voltage stabilizing circuit comprises a sinusoidal voltage waveform, a rectifier bridge circuit, a high-voltage charging module, a front reference module Pre-BAG and a linear voltage stabilizing module, the sine voltage waveform is connected with the rectifier bridge circuit; the rectifier bridge circuit is connected with the high-voltage charging module; the high-voltage charging module is respectively connected with the front reference module Pre-BAG and the linear voltage stabilizing module; and the front reference module (Pre-BAG) is connected with the linear voltage stabilization module. According to the utility model, the technical problems of unstable output of the synchronous rectifier, limited conversion efficiency, poor load regulation rate and the like caused by unstable working voltage of a control circuit in the prior art are solved.

Description

Technical Field

[0001] This utility model relates to a high-voltage step-down voltage regulator circuit suitable for high-power synchronous rectifiers. Background Technology

[0002] Synchronous rectifiers, also known as AC / DC power converters, essentially use power electronic devices to convert alternating current (AC) into direct current (DC). Synchronous rectifiers offer advantages such as low power consumption, high efficiency, high reliability, and high integration. The performance of the rectifier has a crucial impact on the overall reliability of the system. Maintaining the phase of the MOSFET gate control signal synchronized with the phase of the rectified voltage, improving the conversion efficiency of the synchronous rectifier, and implementing intelligent control are key to achieving high-performance synchronous rectifiers. In a synchronous rectifier chip, the control circuit is the core of a high-power synchronous rectifier, significantly influencing the circuit's signal processing performance. Therefore, providing a stable operating voltage for the control circuit is extremely important.

[0003] Therefore, a high-voltage step-down regulator circuit suitable for high-power synchronous rectifiers is provided. Utility Model Content

[0004] The purpose of this utility model is to overcome the existing defects and provide a high-voltage step-down voltage regulator circuit suitable for high-power synchronous rectifiers, so as to solve the technical problems such as unstable output of synchronous rectifiers, limited conversion efficiency and poor load regulation caused by the unstable operating voltage of the control circuit under the existing technology.

[0005] The technical solution to achieve the above objectives is:

[0006] A high-voltage step-down regulator circuit suitable for high-power synchronous rectifiers includes: a sinusoidal voltage waveform, a rectifier bridge circuit, a high-voltage charging module, a pre-BAG reference module, and a linear regulator module;

[0007] The sinusoidal voltage waveform is connected to the rectifier bridge circuit;

[0008] The rectifier bridge circuit is connected to the high-voltage charging module;

[0009] The high-voltage charging module is connected to the pre-BAG reference module and the linear voltage regulator module respectively;

[0010] The pre-BAG module is connected to the linear voltage regulator module.

[0011] Preferably, the rectifier bridge circuit includes: a second LDMOS transistor, a third LDMOS transistor, a fourth LDMOS transistor, and a fifth LDMOS transistor.

[0012] The sinusoidal voltage waveform is connected to the two ends of the third LDMOS transistor and the fourth LDMOS transistor, respectively;

[0013] The second LDMOS transistor is connected to the high-voltage charging module;

[0014] The fifth LDMOS transistor is grounded.

[0015] Preferably, the high-voltage charging module includes: a zero-resistor and a high-voltage transistor.

[0016] The second LDMOS transistor is connected to the drain of the first resistor and the high-voltage transistor, respectively;

[0017] The zero-resistance is connected to the gate of the high-voltage tube;

[0018] The source of the high-voltage tube is connected to the first resistor;

[0019] The first resistor is connected to the first capacitor, the sixth resistor, and the linear voltage regulator module, respectively.

[0020] The sixth resistor is connected to the Pre-BAG pre-base module, the linear regulator module, and the cathode of the Zener diode, respectively.

[0021] The other end of the first capacitor and the anode of the Zener diode are grounded.

[0022] Preferably, the pre-BAG module includes: a startup circuit, a current source circuit, a temperature compensation circuit, and a high-gain operational amplifier circuit.

[0023] The startup circuit includes: a thirteenth PMOS transistor, a fourteenth NMOS transistor, and a fifteenth NMOS transistor.

[0024] The sixth resistor is connected to the drain of the thirteenth PMOS transistor;

[0025] The source and gate of the thirteenth PMOS transistor are respectively connected to the gate of the fourteenth NMOS transistor and the drain of the fifteenth NMOS transistor.

[0026] The drain of the fourteenth NMOS transistor is connected to the high-gain operational amplifier circuit;

[0027] The source of the fourteenth NMOS transistor is connected to the gate of the fifteenth NMOS transistor;

[0028] The source of the fifteenth NMOS transistor is grounded;

[0029] The current source circuit includes: a first transistor, a second transistor, a third resistor, a tenth PMOS transistor, an eleventh PMOS transistor, and a twelfth PMOS transistor.

[0030] The sixth resistor is connected to the drain of the tenth, eleventh, and twelfth PMOS transistors.

[0031] The gates of the tenth, eleventh, and twelfth PMOS transistors are all connected to the high-gain operational amplifier circuit.

[0032] The source of the twelfth PMOS transistor is connected to the third resistor and the high-gain operational amplifier circuit, respectively.

[0033] The source of the eleventh PMOS transistor is connected to the emitter of the second transistor and the high-gain operational amplifier circuit, respectively.

[0034] The source of the tenth PMOS transistor is connected to the temperature compensation circuit and the linear voltage regulator module, respectively.

[0035] The other end of the third resistor is connected to the emitter of the first transistor;

[0036] The base and collector of the first transistor and the base and collector of the second transistor are both grounded;

[0037] The temperature compensation circuit includes: a third transistor and a second resistor.

[0038] The source of the tenth PMOS transistor is connected to the second resistor;

[0039] The other end of the second resistor is connected to the emitter of the third transistor;

[0040] The base and collector of the third transistor are both grounded;

[0041] The high-gain operational amplifier circuit includes: a first PMOS transistor, a second PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, and a ninth PMOS transistor.

[0042] The gates of the tenth, eleventh, and twelfth PMOS transistors, and the drain of the fourteenth NMOS transistor are all connected to the gate of the ninth PMOS transistor.

[0043] The source of the eleventh PMOS transistor is connected to the gate of the first PMOS transistor.

[0044] The source of the twelfth PMOS transistor is connected to the gate of the second PMOS transistor;

[0045] The sixth resistor is connected to the drain of the fifth PMOS transistor, the sixth PMOS transistor, and the ninth PMOS transistor;

[0046] The source of the fifth PMOS transistor is connected to the drain of the first PMOS transistor and the second PMOS transistor, respectively.

[0047] The gate of the fifth PMOS transistor, the source and gate of the sixth PMOS transistor are all connected to the drain of the seventh NMOS transistor.

[0048] The source of the ninth PMOS transistor is connected to the gate of the seventh NMOS transistor and the drain and gate of the eighth NMOS transistor, respectively.

[0049] The sources of the seventh and eighth NMOS transistors are grounded;

[0050] The sources of both the first and second PMOS transistors are connected to the linear voltage regulator module.

[0051] Preferably, the linear voltage regulator module includes an operational amplifier and a MOSFET.

[0052] The first resistor is connected to the drain of the MOS transistor;

[0053] The sixth resistor is connected to the power supply terminal of the operational amplifier;

[0054] The sources of the tenth PMOS transistor, the first PMOS transistor, and the second PMOS transistor are all connected to the non-inverting input terminal of the operational amplifier.

[0055] The negative inverting input terminal of the operational amplifier is connected to a fifth resistor;

[0056] The output terminal of the operational amplifier is connected to the gate of the MOS transistor;

[0057] The operational amplifier's ground terminal is grounded;

[0058] The source of the MOS transistor is connected to a fourth resistor;

[0059] The other end of the fourth resistor is connected to the fifth resistor;

[0060] The other end of the fifth resistor is grounded.

[0061] The beneficial effects of this invention are: the invention provides a stable operating voltage to the control circuit through a rectifier bridge circuit, a high-voltage charging module, a pre-BAG reference module, and a linear voltage regulator module, thereby reducing the change in output voltage with temperature and improving power conversion efficiency and power energy utilization. It also solves the technical problems of unstable output, limited conversion efficiency, and poor load regulation of existing high-power rectifiers. Attached Figure Description

[0062] Figure 1 This is a circuit diagram of a high-voltage step-down voltage regulator circuit suitable for high-power synchronous rectifiers according to this utility model;

[0063] Figure 2This is a detailed circuit diagram of the rectifier bridge circuit, high-voltage charging module, pre-BAG reference module, and linear regulator module in this utility model. Detailed Implementation

[0064] The technical solution of this utility model will now be clearly and completely described in conjunction with the accompanying drawings. In the description of this utility model, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the accompanying drawings and are only for the convenience of describing this utility model and simplifying the description. They do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this utility model. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0065] The present invention will be further described below with reference to the accompanying drawings.

[0066] like Figure 1 , 2 As shown, a high-voltage buck regulator circuit suitable for high-power synchronous rectifiers is characterized by comprising: a sinusoidal voltage waveform AC, a rectifier bridge circuit, a high-voltage charging module, a pre-BAG reference module, and a linear regulator module; the sinusoidal voltage waveform AC is connected to the rectifier bridge circuit; the rectifier bridge circuit is connected to the high-voltage charging module; the high-voltage charging module is connected to both the pre-BAG reference module and the linear regulator module; and the pre-BAG reference module is connected to the linear regulator module.

[0067] In this embodiment, the rectifier bridge circuit includes: a second LDMOS transistor LDMOS2, a third LDMOS transistor LDMOS3, a fourth LDMOS transistor LDMOS4, and a fifth LDMOS transistor LDMOS5. The sinusoidal voltage waveform AC is connected to the two ends of the third LDMOS transistor LDMOS3 and the fourth LDMOS transistor LDMOS4, respectively. The second LDMOS transistor LDMOS2 is connected to the high-voltage charging module. The fifth LDMOS transistor LDMOS5 is grounded. The four LDMOS transistors replace the diodes and are connected to form a bridge rectifier circuit to fully rectify the 220V / 50Hz sinusoidal voltage waveform AC, thereby forming the power supply voltage ACC.

[0068] In this embodiment, the high-voltage charging module includes: a first zero resistor R0 and a high-voltage transistor LDMOS1; a second LDMOS transistor LDMOS2 is connected to the drain of the first resistor R0 and the high-voltage transistor LDMOS1, respectively; the first zero resistor R0 is connected to the gate of the high-voltage transistor LDMOS1; the source of the high-voltage transistor LDMOS1 is connected to the first resistor R1; the first resistor R1 is connected to the first capacitor C1, the sixth resistor R6, and the linear regulator module, respectively; the sixth resistor R6 is connected to the pre-BAG reference module, the linear regulator module, and the cathode of the Zener diode Z1, respectively; the other end of the first capacitor C1 and the anode of the Zener diode Z1 are grounded; the high-voltage transistor LDMOS1 can provide a current source to charge the first capacitor C1, so the voltage across the first capacitor C1 is VCC; the sixth resistor R6 and the Zener diode Z1 form a voltage regulator circuit, and the regulated voltage value of the Zener diode Z1 is provided to the pre-BAG reference module and the linear regulator module as the working voltage.

[0069] In this embodiment, the Pre-BAG module includes: a startup circuit, a current source circuit, a temperature compensation circuit, and a high-gain operational amplifier circuit.

[0070] The startup circuit includes: a thirteenth PMOS transistor M13, a fourteenth NMOS transistor M14, and a fifteenth NMOS transistor M15. Resistor R6 is connected to the drain of the thirteenth PMOS transistor M13. The source and gate of the thirteenth PMOS transistor M13 are connected to the gate of the fourteenth NMOS transistor M14 and the drain of the fifteenth NMOS transistor M15, respectively. The drain of the fourteenth NMOS transistor M14 is connected to a high-gain operational amplifier circuit. The source of the fourteenth NMOS transistor M14 is connected to the gate of the fifteenth NMOS transistor M15. The source of the fifteenth NMOS transistor M15 is grounded. The startup circuit is mainly added because the bandgap reference circuit has a degeneracy point. To avoid the occurrence of the degeneracy point, a startup circuit is added to the circuit.

[0071] The current source circuit includes: a first transistor Q1, a second transistor Q2, a third resistor R3, a tenth PMOS transistor M10, an eleventh PMOS transistor M11, and a twelfth PMOS transistor M12. A sixth resistor R6 is connected to the drains of the tenth PMOS transistors M10, M11, and M12. The gates of the tenth PMOS transistors M10, M11, and M12 are all connected to a high-gain operational amplifier circuit. The source of the twelfth PMOS transistor M12 is connected to the third resistor R3 and the high-gain operational amplifier circuit. The temperature-proportional current source circuit generates a temperature-proportional voltage, which is converted into a temperature-proportional current through the third resistor R3.

[0072] The source of the eleventh PMOS transistor M11 is connected to the emitter of the second transistor Q2 and the high-gain operational amplifier circuit, respectively; the source of the tenth PMOS transistor M10 is connected to the temperature compensation circuit and the linear voltage regulator module, respectively; the other end of the third resistor R3 is connected to the emitter of the first transistor Q1; the base and collector of the first transistor Q1 and the base and collector of the second transistor Q2 are both grounded; the temperature compensation circuit includes: the third transistor Q3 and the second resistor R2, the source of the tenth PMOS transistor M10 is connected to the second resistor R2; the other end of the second resistor R2 is connected to the emitter of the third transistor Q3; the base and collector of the third transistor Q3 are both grounded; the temperature compensation circuit uses the negative temperature characteristic of the emitter junction voltage and the positive temperature characteristic generated by the current source circuit that is proportional to the temperature to compensate, and finally obtains a reference voltage that is independent of temperature.

[0073] The high-gain operational amplifier circuit includes: a first PMOS transistor M1, a second PMOS transistor M2, a fifth PMOS transistor M5, a sixth PMOS transistor M6, a seventh NMOS transistor M7, an eighth NMOS transistor M8, and a ninth PMOS transistor M9; the gates of the tenth PMOS transistor M10, the eleventh PMOS transistor M11, and the twelfth PMOS transistor M12, and the drain of the fourteenth NMOS transistor M14 are all connected to the gate of the ninth PMOS transistor M9; the source of the eleventh PMOS transistor M11 is connected to the gate of the first PMOS transistor M1; the source of the twelfth PMOS transistor M12 is connected to the gate of the second PMOS transistor M2; and a sixth resistor R6 is connected to the gate of the fifth PMOS transistor M9. The drains of PMOS transistors M5, M6, and M9; the source of PMOS transistor M5 is connected to the drains of PMOS transistors M1 and M2; the gate of PMOS transistor M5, the source and gate of PMOS transistor M6 are all connected to the drain of NMOS transistor M7; the source of PMOS transistor M9 is connected to the gate of NMOS transistor M7 and the drain and gate of NMOS transistor M8; the sources of NMOS transistors M7 and M8 are grounded; the sources of PMOS transistors M1 and M2 are all connected to the linear regulator module.

[0074] In this embodiment, the linear voltage regulator module includes an operational amplifier OPA1 and a MOSFET M. A first resistor R1 is connected to the drain of the MOSFET M; a sixth resistor R6 is connected to the power supply terminal of the operational amplifier OPA1; the sources of the tenth PMOS transistor M10, the first PMOS transistor M1, and the second PMOS transistor M2 are all connected to the positive input terminal of the operational amplifier OPA1; the negative input terminal of the operational amplifier OPA1 is connected to the fifth resistor R5; the output terminal of the operational amplifier OPA1 is connected to the gate of the MOSFET M; the ground terminal of the operational amplifier OPA1 is grounded; the source of the MOSFET M is connected to the fourth resistor R4; the other end of the fourth resistor R4 is connected to the fifth resistor R5; the other end of the fifth resistor R5 is grounded.

[0075] Among them, such as Figure 2 As shown, the internal circuit of operational amplifier OPA1 consists of the third NMOS transistor M3, the fourth NMOS transistor M4, the sixteenth PMOS transistor M16, the seventeenth PMOS transistor M17, the eighteenth NMOS transistor M18, the nineteenth NMOS transistor M19, the twentieth PMOS transistor M20, the twenty-first PMOS transistor M21, the twenty-second PMOS transistor M22, the twenty-third PMOS transistor M23, the twenty-fourth PMOS transistor M24, the twenty-fifth PMOS transistor M25, the twenty-sixth PMOS transistor M26, the twenty-seventh NMOS transistor M27, the twenty-eighth PMOS transistor M28, and the twenty-ninth PMOS transistor M29, as well as resistors R, RB, and capacitor C. This is an existing circuit configuration and will not be described in detail.

[0076] The Pre-BAG module provides a reference voltage for the operational amplifier OPA1. The capacitor voltage VCC serves as the input voltage of the power transistor. The fourth resistor R4 and the fifth resistor R5 form a resistor feedback network. The voltage across resistor R5 is used as the feedback voltage and is compared with the reference voltage at the input of the op-amp. The output signal is adjusted according to the change in the input voltage, thereby controlling the conduction state of the regulating transistor and stabilizing the output voltage.

[0077] The above embodiments are only used to illustrate the technical solutions of this utility model, and are not intended to limit it. Although the utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this utility model.

Claims

1. A high-voltage step-down regulator circuit suitable for high-power synchronous rectifiers, characterized in that, include: Sinusoidal voltage waveform (AC), rectifier bridge circuit, high voltage charging module, pre-BAG reference module and linear regulator module; The sinusoidal voltage waveform (AC) is connected to the rectifier bridge circuit; The rectifier bridge circuit is connected to the high-voltage charging module; The high-voltage charging module is connected to the pre-BAG reference module and the linear voltage regulator module respectively; The pre-BAG module is connected to the linear voltage regulator module.

2. The high-voltage step-down regulator circuit suitable for high-power synchronous rectifiers according to claim 1, characterized in that, The rectifier bridge circuit includes: a second LDMOS transistor (LDMOS2), a third LDMOS transistor (LDMOS3), a fourth LDMOS transistor (LDMOS4), and a fifth LDMOS transistor (LDMOS5). The sinusoidal voltage waveform (AC) is connected to the two ends of the third LDMOS transistor (LDMOS3) and the fourth LDMOS transistor (LDMOS4), respectively; The second LDMOS transistor (LDMOS2) is connected to the high-voltage charging module; The fifth LDMOS transistor (LDMOS5) is grounded.

3. The high-voltage step-down regulator circuit suitable for high-power synchronous rectifiers according to claim 2, characterized in that, The high-voltage charging module includes: a zero-resistor (R0) and a high-voltage transistor (LDMOS1). The second LDMOS transistor (LDMOS2) is connected to the drain of the zero-resistance transistor (R0) and the high-voltage transistor (LDMOS1), respectively; The zero-resistance (R0) is connected to the gate of the high-voltage transistor (LDMOS1); The source of the high-voltage transistor (LDMOS1) is connected to the first resistor (R1). The first resistor (R1) is connected to the first capacitor (C1), the sixth resistor (R6), and the linear voltage regulator module, respectively; The sixth resistor (R6) is connected to the cathode of the pre-BAG reference module, the linear regulator module, and the Zener diode (Z1), respectively. The other end of the first capacitor (C1) and the anode of the Zener diode (Z1) are grounded.

4. The high-voltage step-down regulator circuit suitable for high-power synchronous rectifiers according to claim 3, characterized in that, The Pre-BAG module includes: a startup circuit, a current source circuit, a temperature compensation circuit, and a high-gain operational amplifier circuit. The startup circuit includes: a thirteenth PMOS transistor (M13), a fourteenth NMOS transistor (M14), and a fifteenth NMOS transistor (M15). The sixth resistor (R6) is connected to the drain of the thirteenth PMOS transistor (M13); The source and gate of the thirteenth PMOS transistor (M13) are respectively connected to the gate of the fourteenth NMOS transistor (M14) and the drain of the fifteenth NMOS transistor (M15); The drain of the fourteenth NMOS transistor (M14) is connected to the high-gain operational amplifier circuit; The source of the fourteenth NMOS transistor (M14) is connected to the gate of the fifteenth NMOS transistor (M15); The source of the fifteenth NMOS transistor (M15) is grounded; The current source circuit includes: a first transistor (Q1), a second transistor (Q2), a third resistor (R3), a tenth PMOS transistor (M10), an eleventh PMOS transistor (M11), and a twelfth PMOS transistor (M12). The sixth resistor (R6) is connected to the drain of the tenth PMOS transistor (M10), the eleventh PMOS transistor (M11), and the twelfth PMOS transistor (M12); The gates of the tenth PMOS transistor (M10), the eleventh PMOS transistor (M11), and the twelfth PMOS transistor (M12) are all connected to the high-gain operational amplifier circuit. The source of the twelfth PMOS transistor (M12) is connected to the third resistor (R3) and the high-gain operational amplifier circuit, respectively. The source of the eleventh PMOS transistor (M11) is connected to the emitter of the second transistor (Q2) and the high-gain operational amplifier circuit, respectively. The source of the tenth PMOS transistor (M10) is connected to the temperature compensation circuit and the linear voltage regulator module, respectively. The other end of the third resistor (R3) is connected to the emitter of the first transistor (Q1); The base and collector of the first transistor (Q1) and the base and collector of the second transistor (Q2) are both grounded; The temperature compensation circuit includes: a third transistor (Q3) and a second resistor (R2). The source of the tenth PMOS transistor (M10) is connected to the second resistor (R2). The other end of the second resistor (R2) is connected to the emitter of the third transistor (Q3); The base and collector of the third transistor (Q3) are both grounded; The high-gain operational amplifier circuit includes: a first PMOS transistor (M1), a second PMOS transistor (M2), a fifth PMOS transistor (M5), a sixth PMOS transistor (M6), a seventh NMOS transistor (M7), an eighth NMOS transistor (M8), and a ninth PMOS transistor (M9). The gates of the tenth PMOS transistor (M10), the eleventh PMOS transistor (M11), and the twelfth PMOS transistor (M12), and the drain of the fourteenth NMOS transistor (M14) are all connected to the gate of the ninth PMOS transistor (M9). The source of the eleventh PMOS transistor (M11) is connected to the gate of the first PMOS transistor (M1); The source of the twelfth PMOS transistor (M12) is connected to the gate of the second PMOS transistor (M2); The sixth resistor (R6) is connected to the drain of the fifth PMOS transistor (M5), the sixth PMOS transistor (M6), and the ninth PMOS transistor (M9); The source of the fifth PMOS transistor (M5) is connected to the drain of the first PMOS transistor (M1) and the second PMOS transistor (M2), respectively. The gate of the fifth PMOS transistor (M5), the source and gate of the sixth PMOS transistor (M6) are all connected to the drain of the seventh NMOS transistor (M7); The source of the ninth PMOS transistor (M9) is connected to the gate of the seventh NMOS transistor (M7) and the drain and gate of the eighth NMOS transistor (M8), respectively. The sources of the seventh NMOS transistor (M7) and the eighth NMOS transistor (M8) are grounded; The sources of both the first PMOS transistor (M1) and the second PMOS transistor (M2) are connected to the linear voltage regulator module.

5. A high-voltage step-down regulator circuit suitable for high-power synchronous rectifiers according to claim 4, characterized in that, The linear voltage regulator module includes an operational amplifier (OPA1) and a MOSFET (M). The first resistor (R1) is connected to the drain of the MOS transistor (M); The sixth resistor (R6) is connected to the power supply terminal of the operational amplifier (OPA1); The sources of the tenth PMOS transistor (M10), the first PMOS transistor (M1), and the second PMOS transistor (M2) are all connected to the non-inverting input terminal of the operational amplifier (OPA1). The negative input terminal of the operational amplifier (OPA1) is connected to the fifth resistor (R5). The output of the operational amplifier (OPA1) is connected to the gate of the MOS transistor (M); The ground terminal of the operational amplifier (OPA1) is grounded; The source of the MOS transistor (M) is connected to a fourth resistor (R4). The other end of the fourth resistor (R4) is connected to the fifth resistor (R5); The other end of the fifth resistor (R5) is grounded.

Images