Overcurrent protection circuit

Abstract

The utility model provides an overcurrent protection circuit, which comprises an operational amplifier U2 and a second MOS tube Q2, and is characterized in that the reverse input end of the operational amplifier U2 is electrically connected with a COMP pin of a chip; the output end of the operational amplifier U2 is electrically connected with the G end of the second MOS tube Q2; the D end of the second MOS tube Q2 is electrically connected with the first end of a first resistor R1, and the second end of the first resistor R1 is electrically connected with a voltage input end VCC; a first end of the first resistor R1 is electrically connected with a first capacitor plate of the first capacitor C1, and a second capacitor plate of the first capacitor C1 is grounded; and the S end of the second MOS tube Q2 is grounded. According to the technical scheme, the operational amplifier U2 and the second MOS tube Q2 are arranged, so that an overcurrent protection function is realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of GF core components, and particularly relates to an overcurrent protection circuit. BACKGROUND

[0002] Due to different temperature characteristics of electronic components, design of loop parameters, and the like, the output overcurrent protection point is higher or lower than the normal temperature output overcurrent protection point in a three-temperature working environment. In order to realize the consistency of the output overcurrent points of various input voltages under the three-temperature condition, an overcurrent protection circuit is urgently needed. CONTENT OF THE INVENTION

[0003] The present application provides an overcurrent protection circuit to realize the overcurrent protection function.

[0004] The present application provides an overcurrent protection circuit, comprising: an operational amplifier U2 and a second MOS tube Q2, wherein,

[0005] The reverse input end of the operational amplifier U2 is electrically connected with the COMP pin of a chip.

[0006] The output end of the operational amplifier U2 is electrically connected with the G end of the second MOS tube Q2.

[0007] The D end of the second MOS tube Q2 is electrically connected with the first end of a first resistor R1, the second end of the first resistor R1 is electrically connected with a voltage input end VCC; the first end of the first resistor R1 is electrically connected with the first capacitor plate of a first capacitor C1, and the second capacitor plate of the first capacitor C1 is grounded.

[0008] The S end of the second MOS tube Q2 is grounded.

[0009] In the above technical solution, by setting the operational amplifier U2 and the second MOS tube Q2, the reverse input end of the operational amplifier U2 is electrically connected with the COMP pin of the chip; the output end of the operational amplifier U2 is electrically connected with the G end of the second MOS tube Q2; the D end of the second MOS tube Q2 is electrically connected with the first end of the first resistor R1, the second end of the first resistor R1 is electrically connected with the voltage input end VCC; the first end of the first resistor R1 is electrically connected with the first capacitor plate of the first capacitor C1, and the second capacitor plate of the first capacitor C1 is grounded; the overcurrent protection function is realized.

[0010] In one specific embodiment, a second diode D2 is further included, wherein,

[0011] The conducting end of the second diode D2 is electrically connected with the COMP pin of the chip.

[0012] The cutoff end of the second diode D2 is electrically connected with the reverse input end of the operational amplifier U2.

[0013] In one specific embodiment, further comprising a negative temperature coefficient resistance RT, an eighth resistance R8 and a ninth resistance R9, wherein,

[0014] The first end of the ninth resistance R9 is electrically connected with the conducting end of the second diode D2, and the second end of the ninth resistance R9 is electrically connected with the COMP pin of the chip;

[0015] The first end of the eighth resistance R8 is electrically connected with the cutoff end of the second diode D2, the second end of the eighth resistance R8 is electrically connected with the first end of the negative temperature coefficient resistance RT, and the second end of the negative temperature coefficient resistance RT is grounded.

[0016] In one specific embodiment, further comprising a tenth resistance R10, an eleventh resistance R11 and a sixth capacitor C6, wherein,

[0017] The first end of the eleventh resistance R11 is electrically connected with the second end of the ninth resistance R9, and the second end of the eleventh resistance R11 is electrically connected with the COMP pin of the chip;

[0018] The first end of the tenth resistance R10 is electrically connected with the second end of the ninth resistance R9, and the second end of the tenth resistance R10 is grounded.

[0019] The sixth capacitor C6 is connected in parallel with the tenth resistance R10.

[0020] In one specific embodiment, further comprising a first MOS tube Q1, wherein,

[0021] The D end of the first MOS tube Q1 is electrically connected with the COMP pin of the chip;

[0022] The G end of the first MOS tube Q1 is electrically connected with the first capacitor plate of the first capacitor C1;

[0023] The S end of the first MOS tube Q1 is grounded.

[0024] In one specific embodiment, further comprising a first diode D1, wherein,

[0025] The conducting end of the first diode D1 is electrically connected with the first end of the fourth resistance R4, and the second end of the fourth resistance R4 is electrically connected with the positive input end of the operational amplifier U2;

[0026] The cutoff end of the first diode D1 is electrically connected with the first end of the third resistance R3, and the second end of the third resistance R3 is electrically connected with the voltage input end VCC;

[0027] The cutoff end of the first diode D1 is electrically connected with the output end of the operational amplifier U2.

[0028] In one specific embodiment, further comprising a second resistor R2, wherein,

[0029] The first end of the second resistor R2 is electrically connected with the output end of the operational amplifier U2, and the second end of the second resistor R2 is grounded.

[0030] In one specific embodiment, further comprising a voltage stabilizing tube U1, wherein,

[0031] The conducting end of the voltage stabilizing tube U1 is grounded, the cutoff end of the voltage stabilizing tube U1 is electrically connected with the first end of the seventh resistor, and the second end of the seventh resistor is electrically connected with the voltage input end VCC.

[0032] The cutoff end of the voltage stabilizing tube U1 is electrically connected with the positive input end of the operational amplifier U2.

[0033] In one specific embodiment, further comprising a fifth resistor R5, wherein,

[0034] The first end of the fifth resistor R5 is electrically connected with the positive input end of the operational amplifier U2, and the second end of the fifth resistor R5 is electrically connected with the cutoff end of the voltage stabilizing tube U1.

[0035] In one specific embodiment, further comprising a third capacitor C3, a fourth capacitor C4 and a fifth capacitor C5, wherein,

[0036] The first capacitor plate of the third capacitor C3 is electrically connected with the positive input end of the operational amplifier U2, and the second capacitor plate of the third capacitor C3 is grounded.

[0037] The first capacitor plate of the fourth capacitor C4 is electrically connected with the voltage input end VCC, and the second capacitor plate of the fourth capacitor C4 is grounded.

[0038] The first capacitor plate of the fifth capacitor C5 is electrically connected with the negative input end of the operational amplifier U2, and the second capacitor plate of the fifth capacitor C5 is grounded. BRIEF DESCRIPTION OF DRAWINGS

[0039] Figure 1 Another circuit diagram of the overcurrent protection circuit provided by the embodiment of the present application. DETAILED DESCRIPTION

[0040] The present application will be further described in details by the accompanying drawings and embodiments. Through these descriptions, the features and advantages of the present application will become more apparent.

[0041] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any implementation described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other implementations. Unless specifically indicated otherwise, the drawings are not necessarily to scale.

[0042] In addition, the technical features involved in different embodiments of the present application described below can be combined with each other as long as there is no conflict.

[0043] In order to facilitate the understanding of the overcurrent protection circuit provided by the embodiments of the present application, the application scenario thereof is first described. The overcurrent protection circuit provided by the embodiments of the present application is used to realize the overcurrent protection function. Due to different temperature characteristics of electronic components, design of loop parameters, and other reasons, the phenomenon that the output overcurrent protection point is higher or lower than the normal temperature output overcurrent protection point in a three-temperature working environment, in order to realize the consistency of the output overcurrent points of various input voltages under the three-temperature condition, an overcurrent protection circuit is urgently needed. Therefore, the embodiments of the present application provide an overcurrent protection circuit to realize the overcurrent protection function. The embodiments will be described in detail below in combination with specific drawings.

[0044] Reference Figure 1 , Figure 1 The circuit diagram of another overcurrent protection circuit provided by the embodiments of the present application is shown in FIG. 2.

[0045] In Figure 1 the embodiments of the present application, an overcurrent protection circuit is provided, which comprises an operational amplifier U2 and a second MOS tube Q2, wherein,

[0046] The reverse input end of the operational amplifier U2 is electrically connected with the COMP pin of the chip;

[0047] The output end of the operational amplifier U2 is electrically connected with the G end of the second MOS tube Q2;

[0048] The D end of the second MOS tube Q2 is electrically connected with the first end of the first resistor R1, and the second end of the first resistor R1 is electrically connected with the voltage input end VCC; the first end of the first resistor R1 is electrically connected with the first capacitor plate of the first capacitor C1, and the second capacitor plate of the first capacitor C1 is grounded;

[0049] The S end of the second MOS tube Q2 is grounded.

[0050] In the above technical scheme, by setting the operational amplifier U2 and the second MOS tube Q2, the reverse input end of the operational amplifier U2 is electrically connected with the COMP pin of the chip; the output end of the operational amplifier U2 is electrically connected with the G end of the second MOS tube Q2; the D end of the second MOS tube Q2 is electrically connected with the first end of the first resistor R1, and the second end of the first resistor R1 is electrically connected with the voltage input end VCC; the first end of the first resistor R1 is electrically connected with the first capacitor plate of the first capacitor C1, and the second capacitor plate of the first capacitor C1 is grounded; and the overcurrent protection function is realized.

[0051] In a specific embodiment, a second diode D2 is further included, wherein,

[0052] The conducting end of the second diode D2 is electrically connected with the COMP pin of the chip;

[0053] The cut-off end of the second diode D2 is electrically connected with the reverse input end of the operational amplifier U2.

[0054] In a specific embodiment, a negative temperature coefficient resistor RT, an eighth resistor R8 and a ninth resistor R9 are further included, wherein,

[0055] The first end of the ninth resistor R9 is electrically connected with the conducting end of the second diode D2, and the second end of the ninth resistor R9 is electrically connected with the COMP pin of the chip;

[0056] The first end of the eighth resistor R8 is electrically connected with the cut-off end of the second diode D2, the second end of the eighth resistor R8 is electrically connected with the first end of the negative temperature coefficient resistor RT, and the second end of the negative temperature coefficient resistor RT is grounded.

[0057] In a specific embodiment, a tenth resistor R10, an eleventh resistor R11 and a sixth capacitor C6 are further included, wherein,

[0058] The first end of the eleventh resistor R11 is electrically connected with the second end of the ninth resistor R9, and the second end of the eleventh resistor R11 is electrically connected with the COMP pin of the chip;

[0059] The first end of the tenth resistor R10 is electrically connected with the second end of the ninth resistor R9, and the second end of the tenth resistor R10 is grounded;

[0060] The sixth capacitor C6 is connected in parallel with the tenth resistor R10.

[0061] In a specific embodiment, a first MOS tube Q1 is further included, wherein,

[0062] The D end of the first MOS tube Q1 is electrically connected with the COMP pin of the chip;

[0063] the G end of the first MOS tube Q1 is electrically connected with the first capacitor plate of the first capacitor C1;

[0064] the S end of the first MOS tube Q1 is grounded.

[0065] In one specific embodiment, further comprising a first diode D1, wherein,

[0066] the conducting end of the first diode D1 is electrically connected with the first end of the fourth resistor R4, and the second end of the fourth resistor R4 is electrically connected with the positive input end of the operational amplifier U2;

[0067] the non-conducting end of the first diode D1 is electrically connected with the first end of the third resistor R3, and the second end of the third resistor R3 is electrically connected with the voltage input end VCC;

[0068] the non-conducting end of the first diode D1 is electrically connected with the output end of the operational amplifier U2.

[0069] In one specific embodiment, further comprising a second resistor R2, wherein,

[0070] the first end of the second resistor R2 is electrically connected with the output end of the operational amplifier U2, and the second end of the second resistor R2 is grounded.

[0071] In one specific embodiment, further comprising a voltage stabilizing tube U1, wherein,

[0072] the conducting end of the voltage stabilizing tube U1 is grounded, the non-conducting end of the voltage stabilizing tube U1 is electrically connected with the first end of the seventh resistor, and the second end of the seventh resistor is electrically connected with the voltage input end VCC;

[0073] the non-conducting end of the voltage stabilizing tube U1 is electrically connected with the positive input end of the operational amplifier U2.

[0074] In one specific embodiment, further comprising a fifth resistor R5, wherein,

[0075] the first end of the fifth resistor R5 is electrically connected with the positive input end of the operational amplifier U2, and the second end of the fifth resistor R5 is electrically connected with the non-conducting end of the voltage stabilizing tube U1.

[0076] In one specific embodiment, further comprising a third capacitor C3, a fourth capacitor C4 and a fifth capacitor C5, wherein,

[0077] the first capacitor plate of the third capacitor C3 is electrically connected with the positive input end of the operational amplifier U2, and the second capacitor plate of the third capacitor C3 is grounded;

[0078] The first capacitor plate of the fourth capacitor C4 is electrically connected with the voltage input terminal VCC, and the second capacitor plate of the fourth capacitor C4 is grounded.

[0079] The first capacitor plate of the fifth capacitor C5 is electrically connected with the inverting input terminal of the operational amplifier U2, and the second capacitor plate of the fifth capacitor C5 is grounded.

[0080] Specifically, the working principle of the overcurrent protection circuit is as follows: when the load current rises to a set overcurrent point, the voltage of the COMP pin of the chip is sampled by the sampling resistor and input to the inverting input terminal of the operational amplifier U2, and the voltage of the noninverting input terminal of the operational amplifier U2 is compared with the voltage of the inverting input terminal; if the sampling voltage of the inverting input terminal is higher than the voltage of the noninverting input terminal, the operational amplifier U2 outputs a low level, the second MOS tube Q2 is turned off, and the first resistor R1 and the first capacitor C1 perform RC oscillation at the VCC level, so that the first MOS tube Q1 is periodically turned on and turned off, thereby forcing the COMP pin of the control chip to be grounded, reducing the duty cycle of the output of the control chip to 0, and turning off the main switch tube of the power circuit, thereby realizing the overcurrent protection function.

[0081] In the embodiment, due to the temperature characteristics of the second diode D2, the conduction voltage drop of the second diode D2 changes obviously under three temperature conditions, and has a great influence on the sampling voltage of the inverting input terminal of the operational amplifier U2, so that the negative temperature coefficient thermistor RT is used to adjust the sampling voltage of the inverting input terminal of the operational amplifier U2 under high-temperature and low-temperature conditions, and to realize the adjustment and control of the overcurrent protection point. The adjustment formula is as follows: VU2-=(Vcomp*R10 / (R10+R11)-VD)*(R8+RT) / (R8+R9+RT), VD is the forward conduction voltage drop of the diode D2, RT is the negative temperature coefficient resistor, the resistance value decreases at high temperature and increases at low temperature; by adjusting the negative temperature coefficient resistor RT, the overcurrent protection point under three temperature conditions can be adjusted, and the consistency of the overcurrent protection point under the same input condition can be maintained.

[0082] In the above technical solution, the output overcurrent protection point under three temperature conditions is realized with high precision; the overcurrent protection point under three temperature conditions changes little, the circuit is simple, and the debugging is convenient.

[0083] Those skilled in the art know that the present application can be implemented as a system, a method or a computer program product.

[0084] Therefore, the present disclosure can be embodied in the form of hardware only, software only (including firmware, resident software, micro-code, etc.), or a combination of hardware and software that can all generally be referred to herein as a "circuit", "module" or "system". Furthermore, in some embodiments, the present disclosure can also be implemented in the form of a computer program product that includes computer readable program code.

[0085] Any combination of one or more computer readable medium can be employed. The computer readable medium can be a computer readable signal medium or a computer readable storage medium. A computer readable storage medium can be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer readable storage medium include: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In this document, the computer readable storage medium can be any tangible medium that contains, or stores a program that can be used by an instruction execution system, apparatus, or device.

[0086] Although the embodiments of the present disclosure have been shown and described above, it should be understood that the above-described embodiments are exemplary, and should not be construed as limiting the present disclosure, and those of ordinary skill in the art can make changes, modifications, replacements and variations to the above-described embodiments within the scope of the present disclosure. On this basis, various replacements and improvements can be made to the present disclosure, and these all fall within the protection scope of the present disclosure.

Claims

1. An overcurrent protection circuit, characterized by comprising: The utility model relates to a chip voltage regulator, including: operational amplifier U2 and second MOS tube Q2, wherein, the reverse input end of the operational amplifier U2 is electrically connected with the COMP foot of the chip; the output end of the operational amplifier U2 is electrically connected with the G end of the second MOS tube Q2; the D end of the second MOS tube Q2 is electrically connected with the first end of the first resistance R1, and the second end of the first resistance R1 is electrically connected with the voltage input end VCC;The first end of the first resistance R1 is electrically connected with the first capacitor plate of the first capacitor C1, and the second capacitor plate of the first capacitor C1 is grounded; the S end of the second MOS tube Q2 is grounded.

2. The overcurrent protection circuit of claim 1, wherein, Further including the second diode D2, wherein, the conducting end of the second diode D2 is electrically connected with the COMP foot of the chip; the cutoff end of the second diode D2 is electrically connected with the reverse input end of the operational amplifier U2.

3. The overcurrent protection circuit of claim 2, wherein, Further including negative temperature coefficient resistance RT, eighth resistance R8 and ninth resistance R9, wherein, the first end of the ninth resistance R9 is electrically connected with the conducting end of the second diode D2, and the second end of the ninth resistance R9 is electrically connected with the COMP foot of the chip; the first end of the eighth resistance R8 is electrically connected with the cutoff end of the second diode D2, the second end of the eighth resistance R8 is electrically connected with the first end of the negative temperature coefficient resistance RT, and the second end of the negative temperature coefficient resistance RT is grounded.

4. The overcurrent protection circuit of claim 3, wherein, Further including tenth resistance R10, eleventh resistance R11 and sixth capacitor C6, wherein, the first end of the eleventh resistance R11 is electrically connected with the second end of the ninth resistance R9, and the second end of the eleventh resistance R11 is electrically connected with the COMP foot of the chip; the first end of the tenth resistance R10 is electrically connected with the second end of the ninth resistance R9, and the second end of the tenth resistance R10 is grounded; the sixth capacitor C6 is connected with the tenth resistance R10 in parallel.

5. The overcurrent protection circuit of claim 4, wherein, Further including the first MOS tube Q1, wherein, the D end of the first MOS tube Q1 is electrically connected with the COMP foot of the chip; the G end of the first MOS tube Q1 is electrically connected with the first capacitor plate of the first capacitor C1; the S end of the first MOS tube Q1 is grounded.

6. The overcurrent protection circuit of claim 5, wherein, Further including the first diode D1, wherein, the conducting end of the first diode D1 is electrically connected with the first end of the fourth resistance R4, and the second end of the fourth resistance R4 is electrically connected with the positive input end of the operational amplifier U2; the cutoff end of the first diode D1 is electrically connected with the first end of the third resistance R3, and the second end of the third resistance R3 is electrically connected with the voltage input end VCC; the cutoff end of the first diode D1 is electrically connected with the output end of the operational amplifier U2.

7. The overcurrent protection circuit of claim 6, wherein, Further including the second resistance R2, wherein, the first end of the second resistance R2 is electrically connected with the output end of the operational amplifier U2, and the second end of the second resistance R2 is grounded.

8. The overcurrent protection circuit of claim 7, wherein, Further including the stabilizing tube U1, wherein, the conducting end of the stabilizing tube U1 is grounded, the cutoff end of the stabilizing tube U1 is electrically connected with the first end of the seventh resistance, and the second end of the seventh resistance is electrically connected with the voltage input end VCC; The cutoff end of the voltage stabilizing tube U1 is electrically connected with the positive input end of the operational amplifier U2.

9. The overcurrent protection circuit of claim 8, wherein, Further comprising a fifth resistor R5, wherein, The first end of the fifth resistor R5 is electrically connected with the positive input end of the operational amplifier U2, and the second end of the fifth resistor R5 is electrically connected with the cutoff end of the voltage stabilizing tube U1.

10. The overcurrent protection circuit of claim 9, wherein, Further comprising a third capacitor C3, a fourth capacitor C4 and a fifth capacitor C5, wherein, The first capacitor plate of the third capacitor C3 is electrically connected with the positive input end of the operational amplifier U2, and the second capacitor plate of the third capacitor C3 is grounded; The first capacitor plate of the fourth capacitor C4 is electrically connected with the voltage input end VCC, and the second capacitor plate of the fourth capacitor C4 is grounded; The first capacitor plate of the fifth capacitor C5 is electrically connected with the negative input end of the operational amplifier U2, and the second capacitor plate of the fifth capacitor C5 is grounded.

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