Low power consumption LDO chip output boost circuit

Abstract

A low-power-consumption LDO chip output booster circuit comprises an LDO chip, a voltage-regulator tube, a first switch circuit, a second switch circuit, a third switch circuit, a switch control circuit and a main control circuit. A voltage input pin of the LDO chip, an input end of the main control circuit, a first conduction end of the first switch circuit and a first input end of the switch control circuit are respectively connected with an input power supply; a common end pin of the LDO chip is respectively connected with the cathode of the voltage-regulator tube, the second conduction end of the first switching circuit and the first conduction end of the third switching circuit, the anode of the voltage-regulator tube is connected with the first conduction end of the second switching circuit, and the second conduction ends of the second switching circuit and the third switching circuit are grounded. The output end of the main control circuit is connected with the controlled end of the third switching circuit and the second input end of the switching control circuit. The first output end and the second output end of the switching control circuit are connected with the controlled end of the first switching circuit and the controlled end of the second switching circuit respectively. According to the LDO circuit, the influence on the power consumption of a post-stage circuit of the LDO chip is reduced.

Description

Technical Field

[0001] This utility model relates to power supply circuits, and more particularly to an output boosting circuit for an LDO chip. Background Technology

[0002] An LDO (Low Dropout Regulator) chip is a voltage conversion chip whose output voltage powers subsequent circuits. The power consumption of an LDO chip is related to the output load current and the voltage difference between its input and output. High power consumption in an LDO chip can lead to severe heat generation, and prolonged operation at high temperatures may even burn it out. With a fixed output load current, reducing the voltage difference between the LDO chip's input and output voltage can alleviate heat generation and reduce the risk of damage.

[0003] Current solutions such as Figure 1 As shown, the GND pin of LDO chip U1 is the common terminal. Existing solutions use Zener diode D1 to raise the level of the GND pin of LDO chip U1, thereby increasing the output voltage of LDO chip U1 and reducing the voltage difference between the input and output voltages. However, these existing solutions lack control logic; as long as there is input at the input terminal of LDO chip U1, the output voltage of LDO chip U1 will be raised, which will negatively impact the power consumption of subsequent circuits. Summary of the Invention

[0004] The technical problem to be solved by this utility model is to provide an LDO chip output boost circuit, which reduces the adverse effects on the power consumption of the subsequent circuits of the LDO chip.

[0005] This utility model discloses a low-power LDO chip output boosting circuit, comprising an LDO chip U1, a Zener diode D1, a first switching circuit, a second switching circuit, a third switching circuit, a switch control circuit, and a main control circuit. The voltage input pin Vin of the LDO chip U1, the input terminal of the main control circuit, the first conducting terminal of the first switching circuit, and the first input terminal of the switch control circuit are respectively connected to the input power supply VIN. The common terminal pin GND of the LDO chip U1 is connected to the cathode of the Zener diode D1, the second conducting terminal of the first switching circuit, and the first conducting terminal of the third switching circuit. The anode of the Zener diode D1 is connected to the first conducting terminal of the second switching circuit. The second conducting terminal of the second switching circuit and the third... The second conducting terminal of the switching circuit is grounded; the output terminal of the main control circuit is connected to the controlled terminal of the third switching circuit and the second input terminal of the switch control circuit, respectively; the first output terminal of the switch control circuit is connected to the controlled terminal of the first switching circuit; and the second output terminal of the switch control circuit is connected to the controlled terminal of the second switching circuit. The main control circuit is used to control the third switching circuit to conduct when the input voltage of the LDO chip U1 is less than the preset voltage threshold V1, and to control the first and second switching circuits to turn off when the input voltage of the LDO chip U1 is greater than or equal to the preset voltage threshold V1. The main control circuit is used to control the third switching circuit to turn off when the input voltage of the LDO chip U1 is greater than or equal to the preset voltage threshold V1, and to control the first and second switching circuits to conduct when the input voltage of the LDO chip U1 is greater than or equal to the preset voltage threshold V1.

[0006] This utility model has at least the following technical effects:

[0007] 1. The low-power LDO chip output boosting circuit according to the embodiment of this utility model controls whether the output voltage of the LDO chip is boosted according to the magnitude of the input voltage value of the LDO chip. When the input voltage of the LDO chip is small, the output voltage of the LDO chip is not boosted, thereby reducing the adverse effect on the power consumption of the subsequent circuit of the LDO chip and reducing the power consumption of the subsequent circuit.

[0008] 2. The low-power LDO chip output boosting circuit according to the present invention can reduce the voltage difference between the input voltage and the output voltage of the LDO chip, thereby reducing the power consumption of the LDO chip and alleviating the problem of severe self-heating of the LDO. Attached Figure Description

[0009] Figure 1 The circuit schematic of an existing low-power LDO chip output boost circuit is shown.

[0010] Figure 2 A circuit diagram of a low-power LDO chip output boost circuit according to a first embodiment of the present invention is shown.

[0011] Figure 3A circuit diagram of a low-power LDO chip output boost circuit according to a second embodiment of the present invention is shown. Detailed Implementation

[0012] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments.

[0013] Please refer to Figure 2 The low-power LDO chip output boost circuit according to the first embodiment of this utility model includes an LDO chip U1, a Zener diode D1, a first switching circuit 11, a second switching circuit 12, a third switching circuit 13, a switching control circuit 2, and a main control circuit 3.

[0014] The voltage input pin Vin of LDO chip U1, the input terminal of main control circuit 3, the first conducting terminal of first switching circuit 11, and the first input terminal of switch control circuit 2 are respectively connected to the input power supply VIN.

[0015] The common terminal pin GND of the LDO chip U1 is connected to the cathode of the Zener diode D1, the second conducting terminal of the first switching circuit 11, and the first conducting terminal of the third switching circuit 13, respectively. The anode of the Zener diode D1 is connected to the first conducting terminal of the second switching circuit 12. The second conducting terminals of the second switching circuit 12 and the second conducting terminals of the third switching circuit 13 are grounded, respectively.

[0016] The output terminal of the main control circuit 3 is connected to the controlled terminal of the third switching circuit 13 and the second input terminal of the switch control circuit 2, respectively. The first output terminal of the switch control circuit 2 is connected to the controlled terminal of the first switching circuit 11, and the second output terminal of the switch control circuit 2 is connected to the controlled terminal of the second switching circuit 12. The main control circuit 3 is used to control the third switching circuit 13 to conduct when the input voltage of the LDO chip U1 (i.e., the input power supply VIN in this embodiment) is less than a preset voltage threshold V1, and to control the first switching circuit 11 and the second switching circuit 12 to turn off when the input voltage of the LDO chip U1 is greater than or equal to the preset voltage threshold V1, and to control the first switching circuit 11 and the second switching circuit 12 to conduct when the input voltage of the LDO chip U1 is greater than or equal to the preset voltage threshold V1. In some specific embodiments, the voltage threshold V1 is set to 5V.

[0017] In this embodiment, the switch control circuit 2 includes a resistor R3, a fourth switch circuit 14, and a fifth switch circuit 15. The first end of the resistor R3 forms the first input terminal of the switch control circuit 2, and the second end of the resistor R3 is connected to the first conducting terminal of the fourth switch circuit 14, the controlled terminal of the second switch circuit 12, and the controlled terminal of the fifth switch circuit 15, respectively. The controlled terminal of the fourth switch circuit 14 forms the second input terminal of the switch control circuit 2, and the second conducting terminal of the fourth switch circuit 14 is grounded. The first conducting terminal of the fifth switch circuit 15 is connected to the controlled terminal of the first switch circuit 11, and the second conducting terminal of the fifth switch circuit 15 is grounded.

[0018] Specifically, the fourth switching circuit includes an NPN transistor Q4, resistors R10 and R8. The first terminal of resistor R10 constitutes the controlled terminal of the fourth switching circuit 14, and the collector and emitter of the NPN transistor Q4 constitute the first and second conducting terminals of the fourth switching circuit 14, respectively. The common junction of the second terminal of resistor R10 and the first terminal of resistor R8 is connected to the base of the NPN transistor Q4, and the second terminal of resistor R8 is grounded. The fifth switching circuit 15 includes an NPN transistor Q5 and resistor R6. The common junction of the base of NPN transistor Q5 and the first terminal of resistor R6 constitutes the controlled terminal of the fifth switching circuit, the collector of NPN transistor Q5 constitutes the first conducting terminal of the fifth switching circuit 15, and the common junction of the emitter of NPN transistor Q5 and the second terminal of resistor R6 constitutes the second conducting terminal of the fifth switching circuit 15.

[0019] In this embodiment, the first switching circuit 11 includes a PNP transistor Q1 and a resistor R4. The common junction of the emitter of the PNP transistor Q1 and the first end of the resistor R4 constitutes the first conducting terminal of the first switching circuit 11, the common junction of the base of the PNP transistor Q1 and the second end of the resistor R4 constitutes the controlled terminal of the first switching circuit 11, and the collector of the PNP transistor Q1 constitutes the second conducting terminal of the first switching circuit 11. Further, the low-power LDO chip output boosting circuit in this embodiment also includes a resistor R1. The first end of the resistor R1 is connected to the second conducting terminal of the first switching circuit 11, and the second end of the resistor R1 is connected to the cathode of the Zener diode D1, the first conducting terminal of the third switching circuit 13, and the common terminal pin GND of the LDO chip U1.

[0020] In this embodiment, the second switching circuit 12 includes an NPN transistor Q2, resistors R11 and R9. The first end of resistor R11 constitutes the controlled terminal of the second switching circuit 12, and the collector and emitter of the NPN transistor Q2 constitute the first conducting terminal and the second conducting terminal of the second switching circuit 12, respectively. The common junction of the second end of resistor R11 and the first end of resistor R9 is connected to the base of the NPN transistor Q2, and the second end of resistor R9 is grounded. The third switching circuit 13 includes an NPN transistor Q3, resistors R12 and R7. The first end of resistor R12 constitutes the controlled terminal of the third switching circuit, and the collector and emitter of the NPN transistor Q3 constitute the first conducting terminal and the second conducting terminal of the third switching circuit 13, respectively. The common junction of the second end of resistor R12 and the first end of resistor R7 is connected to the base of the NPN transistor Q3, and the second end of resistor R7 is grounded.

[0021] In this embodiment, the main control circuit 3 includes an input voltage sampling circuit 31 and an MCU 32. The input terminal of the input voltage sampling circuit 31 constitutes the input terminal of the main control circuit 3, and the output terminal of the MCU 32 constitutes the output terminal of the main control circuit 3. The output terminal of the input voltage sampling circuit 31 is connected to the input terminal of the MCU 32. The input voltage sampling circuit 31 is used to detect the input voltage of the LDO chip U1 and output a voltage signal proportional to the input voltage of the LDO chip U1 to the MCU. The MCU is used to compare the measured value of the input voltage sampling circuit 31 with a preset voltage threshold (which corresponds to the aforementioned preset voltage threshold V1). When the input voltage of the LDO chip U1 is less than the preset voltage threshold V1, the MCU controls the third switch circuit 13 to be turned on and causes the switch control circuit 2 to control the first switch circuit 11 and the second switch circuit 12 to be turned off. When the input voltage of the LDO chip U1 is greater than or equal to the preset voltage threshold V1, the MCU controls the third switch circuit 13 to be turned off and causes the switch control circuit 2 to control the first switch circuit 11 and the second switch circuit 12 to be turned on.

[0022] Specifically, the input voltage sampling circuit 31 includes resistors R2 and R5, which are connected in series. The first end of resistor R2 forms the input terminal of the input voltage sampling circuit 31, and the common connection point of the second end of resistor R2 and the first end of resistor R5 forms the output terminal of the input voltage sampling circuit 31. The second end of resistor R5 is grounded. Furthermore, the input voltage sampling circuit 31 also includes capacitor C1, which is connected in parallel with resistor R5.

[0023] The following combination Figure 2 The working principle of the low-power LDO chip output boost circuit in this embodiment will be explained in more detail.

[0024] VIN refers to the input power supply, and its output voltage is the input voltage of the input pin Vin of the LDO chip U1. Vldo refers to the output voltage of the output pin Vout of the LDO chip U1. MCU_ADC is the ADC sampling pin of the MCU32, used to monitor the input voltage value of the LDO chip U1. MCU_GPIO is the GPIO output pin of the MCU32, which outputs a high or low level according to the sampling signal of the input voltage value of the LDO chip.

[0025] The selection of resistors R2 and R5 ensures that when the input voltage of LDO chip U1 is less than V1, the ADC sampling pin of MCU32 detects a low level at point A. When the input voltage of LDO chip U1 is less than the preset voltage threshold V1, MCU32 controls the MCU_GPIO pin to output a high level. The selection of resistors R10 and R8 ensures that when the MCU_GPIO output is high, the voltage at point B is greater than the turn-on voltage of NPN transistor Q4, so NPN transistor Q4 is turned on, and point D is low. The voltage at point D is less than the turn-on voltage of NPN transistor Q5, so NPN transistor Q5 is in the off state (turn-off state), thus causing PNP transistor Q1 to be turned off. At the same time, NPN transistor Q2 is also turned off. The selection of resistors R7 and R12 ensures that when the MCU_GPIO outputs a high level, the voltage at point C is greater than the turn-on voltage of NPN transistor Q3. Therefore, NPN transistor Q3 is in the conducting state, and point G is at a low level. The GND pin of LDO chip U1 is grounded, which can be equivalent to zero potential. The output voltage of LDO chip U1 is not boosted, and the circuit can work normally.

[0026] The selection of resistors R2 and R5 ensures that when the input voltage of LDO chip U1 is greater than or equal to the preset voltage threshold V1, the ADC sampling pin of MCU32 detects a high level at point A. When the input voltage of LDO chip U1 is greater than or equal to the preset voltage threshold V1, MCU32 controls the MCU_GPIO pin to output a low level, thus making the voltage at point B low. Since the voltage at point B is less than the turn-on voltage of NPN transistor Q4, NPN transistor Q4 is turned off. Simultaneously, the voltage at point C is also low, which is less than the turn-on voltage of NPN transistor Q3, so NPN transistor Q3 is also in the off state. The selection of resistors R3 and R6 ensures that when point F is high, the voltage at point D is greater than the turn-on voltage of NPN transistor Q5. Since point F is high at this time, NPN transistor Q5 is turned on. Therefore, the emitter voltage of PNP transistor Q1 is higher than its base voltage, so PNP transistor Q1 is in the on state. The selection of resistors R11 and R9 ensures that when the voltage at point D is high, the voltage at point E must be greater than the turn-on voltage of NPN transistor Q2, thus ensuring that NPN transistor Q2 is conducting. The voltage at point G is the operating voltage of Zener diode D1. Zener diode D1 is selected based on the output boost voltage of LDO chip U1. With the GND pin voltage of LDO chip U1 boosted, the output voltage of LDO chip U1 is its rated output voltage plus the operating voltage of Zener diode D1, allowing the circuit to operate normally. Boosting the output voltage of LDO chip U1, with a fixed load current, reduces the voltage difference between the input and output of LDO chip U1, thereby reducing power consumption and alleviating overheating.

[0027] In this embodiment, the LDO chip U1 used is model LN20342Q1-DFR, but it is not limited to this.

[0028] Figure 3 A circuit diagram of a low-power LDO chip output boost circuit according to a second embodiment of the present invention is shown. The main difference between this second embodiment and the first embodiment lies in the different circuit structure of the main control circuit. In the second embodiment, the main control circuit 3 includes a voltage comparator U2 and a Zener diode D2. The cathode of the Zener diode D2 is connected to the input power supply VIN, the anode of the Zener diode D2 is connected to the inverting input terminal of the voltage comparator U2, the non-inverting input terminal of the voltage comparator is connected to the reference voltage V3, and the output terminal of the voltage comparator U2 is connected to the controlled terminal of the third switching circuit 13 and the second input terminal of the switching control circuit 2, respectively.

[0029] The magnitude of the reference voltage V3 connected to the non-inverting input of voltage comparator U2 and the selection of Zener diode D2 are both related to the magnitude of the preset voltage threshold V1. In some specific embodiments, the magnitude of the reference voltage V3 is equal to the output voltage Vldo of LDO chip U1 (that is, the non-inverting input of voltage comparator U2 is connected to the output pin Vout of LDO chip U1).

[0030] When the input voltage of LDO chip U1 is less than the preset voltage threshold V1, the voltage at point G is the input voltage of LDO chip U1 minus the voltage of Zener diode D2. Since the voltage at point G is less than the voltage at point H, voltage comparator U2 outputs a high level, NPN transistors Q4 and Q3 are turned on, while PNP transistors Q1, Q2, and Q5 are turned off. The GND pin of LDO chip U1 is grounded, which can be equivalent to zero potential, thus preventing the output voltage of LDO chip U1 from being boosted, and allowing the circuit to operate normally.

[0031] When the input voltage of LDO chip U1 is greater than or equal to the preset voltage threshold V1, the voltage at point G is greater than the voltage at point H. Voltage comparator U2 outputs a low level, NPN transistors Q4 and Q3 are turned off, and PNP transistors Q1, Q2, and Q5 are turned on. At this time, the voltage at point G is the operating voltage of Zener diode D1. The voltage at the GND pin of LDO chip U1 is boosted, and the output voltage of LDO chip U1 is its rated output voltage plus the operating voltage of Zener diode D1. The circuit can operate normally. Boosting the output voltage of LDO chip U1, with a fixed load current, reduces the voltage difference between the input and output of LDO chip U1, thereby reducing the power consumption of LDO chip U1 and alleviating heat generation.

Claims

1. A low-power LDO chip output boosting circuit, characterized in that, It includes an LDO chip U1, a Zener diode D1, a first switching circuit, a second switching circuit, a third switching circuit, a switching control circuit, and a main control circuit; The voltage input pin Vin of the LDO chip U1, the input terminal of the main control circuit, the first conducting terminal of the first switching circuit, and the first input terminal of the switch control circuit are respectively connected to the input power supply VIN. The common terminal pin GND of LDO chip U1 is connected to the cathode of Zener diode D1, the second conducting terminal of the first switching circuit, and the first conducting terminal of the third switching circuit, respectively. The anode of Zener diode D1 is connected to the first conducting terminal of the second switching circuit. The second conducting terminals of the second switching circuit and the second conducting terminals of the third switching circuit are grounded, respectively. The output terminal of the main control circuit is connected to the controlled terminal of the third switching circuit and the second input terminal of the switch control circuit, respectively. The first output terminal of the switch control circuit is connected to the controlled terminal of the first switching circuit, and the second output terminal of the switch control circuit is connected to the controlled terminal of the second switching circuit. The main control circuit is used to control the third switching circuit to turn on when the input voltage of the LDO chip U1 is less than a preset voltage threshold V1, and to control the first and second switching circuits to turn off when the input voltage of the LDO chip U1 is greater than or equal to the preset voltage threshold V1.

2. The low-power LDO chip output boosting circuit according to claim 1, characterized in that, The first switching circuit includes a PNP transistor Q1 and a resistor R4; the common connection point of the emitter of the PNP transistor Q1 and the first end of the resistor R4 constitutes the first conducting terminal of the first switching circuit, the common connection point of the base of the PNP transistor Q1 and the second end of the resistor R4 constitutes the controlled terminal of the first switching circuit, and the collector of the PNP transistor Q1 constitutes the second conducting terminal of the first switching circuit.

3. The low-power LDO chip output boosting circuit according to claim 1 or 2, characterized in that, The low-power LDO chip output boost circuit includes a resistor R1. The first end of the resistor R1 is connected to the second conducting end of the first switching circuit, and the second end of the resistor R1 is connected to the cathode of the Zener diode D1, the first conducting end of the third switching circuit, and the common terminal pin GND of the LDO chip U1.

4. The low-power LDO chip output boosting circuit according to claim 1, characterized in that, The second switching circuit includes an NPN transistor Q2, a resistor R11, and a resistor R9; The first end of resistor R11 forms the controlled end of the second switching circuit, and the collector and emitter of NPN transistor Q2 form the first conducting end and the second conducting end of the second switching circuit, respectively. The common connection point of the second end of resistor R11 and the first end of resistor R9 is connected to the base of NPN transistor Q2, and the second end of resistor R9 is grounded.

5. The low-power LDO chip output boosting circuit according to claim 1, characterized in that, The third switching circuit includes an NPN transistor Q3, a resistor R12, and a resistor R7; The first end of resistor R12 forms the controlled end of the third switching circuit, and the collector and emitter of NPN transistor Q3 form the first and second conducting ends of the third switching circuit, respectively. The common connection point of the second end of resistor R12 and the first end of resistor R7 is connected to the base of NPN transistor Q3, and the second end of resistor R7 is grounded.

6. The low-power LDO chip output boosting circuit according to claim 1, characterized in that, The switch control circuit includes resistor R3, a fourth switch circuit, and a fifth switch circuit; The first end of resistor R3 forms the first input terminal of the switch control circuit, and the second end of resistor R3 is connected to the first conducting terminal of the fourth switch circuit, the controlled terminal of the second switch circuit, and the controlled terminal of the fifth switch circuit, respectively. The controlled terminal of the fourth switching circuit constitutes the second input terminal of the switch control circuit, and the second conducting terminal of the fourth switching circuit is grounded. The first conducting terminal of the fifth switching circuit is connected to the controlled terminal of the first switching circuit, and the second conducting terminal of the fifth switching circuit is grounded.

7. The low-power LDO chip output boosting circuit according to claim 6, characterized in that, The fourth switching circuit includes an NPN transistor Q4, a resistor R10, and a resistor R8; The first end of resistor R10 forms the controlled end of the fourth switching circuit. The collector and emitter of NPN transistor Q4 form the first and second conducting ends of the fourth switching circuit, respectively. The common connection point of the second end of resistor R10 and the first end of resistor R8 is connected to the base of NPN transistor Q4. The second end of resistor R8 is grounded.

8. The low-power LDO chip output boosting circuit according to claim 6, characterized in that, The fifth switching circuit includes an NPN transistor Q5 and a resistor R6; The common junction of the base of NPN transistor Q5 and the first end of resistor R6 forms the controlled terminal of the fifth switching circuit. The collector of NPN transistor Q5 forms the first conducting terminal of the fifth switching circuit. The common junction of the emitter of NPN transistor Q5 and the second end of resistor R6 forms the second conducting terminal of the fifth switching circuit.

9. The low-power LDO chip output boosting circuit according to claim 1, characterized in that, The main control circuit includes an input voltage sampling circuit and an MCU; The input terminal of the input voltage sampling circuit constitutes the input terminal of the main control circuit, and the output terminal of the MCU constitutes the output terminal of the main control circuit. The output terminal of the input voltage sampling circuit is connected to the input terminal of the MCU. The input voltage sampling circuit is used to detect the input voltage of the LDO chip U1 and output a voltage signal proportional to the input voltage of the LDO chip U1 to the MCU.

10. The low-power LDO chip output boosting circuit according to claim 1, characterized in that, The main control circuit includes a voltage comparator and a Zener diode D2. The cathode of the Zener diode D2 is connected to the input power supply VIN, the anode of the Zener diode D2 is connected to the inverting input terminal of the voltage comparator, the non-inverting input terminal of the voltage comparator is connected to the reference voltage, and the output terminal of the voltage comparator is connected to the controlled terminal of the third switching circuit and the second input terminal of the switching control circuit, respectively.

11. The low-power LDO chip output boosting circuit according to claim 1, characterized in that, The model number of LDO chip U1 is LN20342Q1-DFR.

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