Small surface-mounted diode array packaging structure

Abstract

The utility model discloses a small surface-mounted diode array packaging structure, and belongs to the technical field of microelectronic device packaging. Comprising a ceramic base body, a side cavity, a sealing ring, a cover plate, a cover plate welding ring, an inner cavity, a bonding area bottom surface, a chip area bottom surface, a bonding area metallization layer, a chip area metallization layer, a bonding area electrode through hole, a chip area electrode through hole, a back electrode bonding pad, a chip and a bonding wire. The side cavity, the inner cavity, the bonding area bottom surface, the chip area bottom surface, the bonding area electrode through hole and the chip area electrode through hole are integrally manufactured in the ceramic base body. The bottom surface of the bonding area is higher than the bottom surface of the chip area, and the chip is welded in the chip area. And the bonding region and the chip region are connected with the corresponding electrode bonding pads on the bottom surface through metal via holes. The problems that an existing surface-mounted multi-array diode discrete device is low in packaging integration level, large in size, low in heat dissipation efficiency, low in product power integration density, large in parasitic impedance and low in reliability are solved. The method is widely applied to the technical field of miniaturized high-reliability packaging of component arrays.

Description

Technical Field

[0001] This utility model belongs to the field of microelectronic device packaging technology, and more specifically to the field of surface mount multi-array discrete device integrated packaging technology. In particular, it relates to a small surface mount diode array packaging structure. Background Technology

[0002] Semiconductor products are gradually becoming smaller and lighter. The integration of discrete devices can optimize circuit structure, reduce board area, and increase power density. This places increasingly higher demands on the integration, miniaturization, hermeticity, and reliability of packaged products.

[0003] Compared to organic plastic packaging, ceramic packaging offers higher mechanical strength, a lower coefficient of thermal expansion, and higher thermal conductivity. These characteristics meet the requirements of high hermeticity and heat dissipation in chip packaging. Ceramic packaging technology provides superior heat resistance, moisture resistance, corrosion resistance, and electromagnetic interference resistance. It maintains stable performance at high temperatures without performance degradation due to temperature increases.

[0004] Ceramic encapsulation has the following characteristics:

[0005] 1. High moisture resistance: It has good waterproof and moisture-proof properties and is suitable for environments with high humidity;

[0006] 2. High corrosion resistance: It has excellent corrosion resistance to chemicals such as acids, alkalis, salts and organic solvents;

[0007] 3. High resistance to electromagnetic interference: It has excellent electromagnetic shielding capabilities and can be used at high frequencies without being affected by electromagnetic interference;

[0008] 4. Excellent electrical performance: Ceramic materials have low resistivity and high insulation performance, which can effectively suppress electromagnetic interference and signal crosstalk;

[0009] 5. Excellent mechanical properties and stability: Ceramic materials have high hardness and impact resistance, which can effectively protect the chip from external physical impacts and damage;

[0010] 6. Good airtightness: Ceramic packaging is an airtight packaging, which can prevent moisture from entering the internal structure and contaminating the chip;

[0011] 7. Low coefficient of thermal expansion: Ceramic materials have a low coefficient of thermal expansion, which is similar to that of chip materials, which helps to improve the reliability of packaging.

[0012] Due to these significant characteristics, ceramic packaging is widely used in various high-performance electronic fields, including aerospace, military equipment, medical devices, high-end communication equipment, and functional electronics. For example, electronic devices operating in extreme temperature and radiation environments require highly reliable and long-term stable communication and navigation systems.

[0013] Current packaging structures using planar integration technology suffer from low integration density, large size, low heat dissipation efficiency, low power density, and high parasitic impedance. They cannot meet the requirements of high integration and miniaturized packaging for multi-array discrete devices.

[0014] In view of the above, this utility model is hereby proposed. Summary of the Invention

[0015] The technical problem to be solved by this utility model is to address the issues of low integration density, large size, low heat dissipation efficiency, low power integration density, high parasitic impedance, and low reliability of existing surface-mount multi-array diode discrete devices.

[0016] The inventive concept of this utility model is:

[0017] The packaging structure uses a ceramic shell (a combination of a multi-layer co-fired ceramic base and a metal cover) for encapsulation. The ceramic base and metal cover are precisely calculated and designed to ensure that the entire product is in an optimal state.

[0018] Within the ceramic housing, electrical signal transmission lines are embedded in each ceramic layer. The electrical signal transmission lines and wire bonding area (collectively referred to as the bonding area) on the bottom surface of the housing are arranged in the same area, while the chip bonding area (referred to as the chip area) is arranged in another area. The bonding area and the chip area are stepped, with the chip area being lower than the bonding area. The bonding area and the chip area are seamlessly isolated using staggered steps, which not only ensures the isolation between the bonding area and the chip area and reduces parasitic effects, but also greatly improves heat dissipation and integration.

[0019] Metallization layers are fabricated on the ceramic bottom planes of the bonding region and the chip region, respectively. The metallization layer in the bonding region is used for electrode wiring and wire bonding of the front electrode of the diode chip, and the metallization layer in the chip region is used for mounting and soldering the diode chip and electrode wiring of the back electrode.

[0020] The bottom areas at both ends of the ceramic base are the external electrode pad layout areas, where diode arrays are respectively arranged for positive electrode pad arrays and negative electrode pad arrays for external connection.

[0021] A through-hole is fabricated below the front electrode wiring layer of the bonding region metallization layer diode chip, penetrating the ceramic base body. The through-hole is filled with metal electrode material and connected to the corresponding electrode pads on the bottom surface of the ceramic base. Similarly, a through-hole is fabricated below the back electrode wiring layer of the chip region metallization layer diode chip, penetrating the ceramic base body. This through-hole is also filled with metal electrode material and connected to the corresponding electrode pads on the bottom surface of the ceramic base. This achieves internal and external electrical connection, significantly reducing the product's parasitic impedance and inductive reactance, while maximizing heat dissipation efficiency and increasing power density. This improves product reliability.

[0022] Therefore, a small surface-mount diode array package structure is provided, such as... Figure 1-4 As shown. Includes:

[0023] 1. Ceramic base body, 2. Side cavity, 3. Sealing ring, 4. Cover plate, 5. Cover plate welding ring, 6. Inner cavity, 7. Bottom surface of bonding area, 8. Bottom surface of chip area, 9. Metallization layer of bonding area, 10. Metallization layer of chip area, 11. Electrode through hole of bonding area, 12. Electrode through hole of chip area, 13. Back electrode pad, 14. Chip, 15. Bonding wire.

[0024] The ceramic base body 1 is a multi-layer co-fired ceramic, and the electrode wiring between each ceramic layer is connected through metal vias provided in the corresponding ceramic layers.

[0025] The side cavity 2, inner cavity 6, bonding area bottom surface 7, chip area bottom surface 8, bonding area electrode through hole 11, and chip area electrode through hole 12 are integrally fabricated within the ceramic base body 1. The bonding area bottom surface 7 is located in the upper region of the bottom of the ceramic base inner cavity, and the chip area bottom surface 8 is located in the lower region of the bottom of the ceramic base inner cavity. The bonding area bottom surface 7 is higher than the chip area bottom surface 8.

[0026] The bonding region metallization layer 9 is fabricated on the bottom surface 7 of the bonding region, and the chip region metallization layer 10 is fabricated on the bottom surface 8 of the chip region. The bonding region metallization layer 9 is used for the bonding region, the front electrode trace of the diode, and the connection with the external electrode, while the chip region metallization layer 10 is used for the chip assembly region, the back electrode trace of the diode, and the connection with the external electrode.

[0027] The chip region metallization layer 10 is lower than the bonding region metallization layer 9, and the chip region electrode via 12 is shorter than the bonding region electrode via 11, which greatly shortens the chip heat dissipation channel, reduces the chip heat dissipation thermal resistance, and facilitates rapid heat dissipation.

[0028] The bonding region electrode via 11 is located below the bonding region metallization layer 9, and the chip region electrode via 12 is located below the chip region metallization layer 10. They penetrate the ceramic base body, are filled with through-hole metal, and are connected to the corresponding back electrode pads 13 respectively.

[0029] The chip 14 is soldered onto the metallization layer 10 in the chip region, and the front electrode of the chip is bonded to the metallization layer 9 in the bonding region via bonding wire 15.

[0030] The cover plate 4 is a ceramic cover plate or a metal cover plate, and a cover plate welding ring 5 is made around the cover plate 4. The shape and size of the cover plate welding ring 5 are the same as those of the sealing ring 3.

[0031] The upper surface of the side cavity 2 is a sealing ring 3, and the cover plate 4 is sealed to the sealing ring 3 by high-temperature welding. Beneficial effects

[0032] This utility model product has the advantages of high packaging integration, small size, high heat dissipation efficiency, high product power integration density, low parasitic impedance, high mechanical strength, stable chemical properties, high insulation, good high frequency shielding, and high reliability.

[0033] It can be widely used in the field of high-reliability packaging technology for miniaturized component arrays. Attached Figure Description

[0034] Figure 1 This is a schematic diagram of the ceramic package structure for a diode array unit channel.

[0035] Figure 2 This is a schematic diagram of the internal cavity layout structure of a ceramic base for a three-channel diode array package.

[0036] Figure 3 This is a schematic diagram of the pin pad layout on the bottom surface of a ceramic base for a three-channel diode array package.

[0037] Figure 4 This is a schematic diagram of the planar structure of a three-channel diode array packaged ceramic base chip assembly.

[0038] In the diagram: 1 is the ceramic base body, 2 is the side cavity, 3 is the sealing ring, 4 is the cover plate, 5 is the cover plate welding ring, 6 is the inner cavity, 7 is the bottom surface of the bonding area, 8 is the bottom surface of the chip area, 9 is the metallization layer of the bonding area, 10 is the metallization layer of the chip area, 11 is the electrode through-hole of the bonding area, 12 is the electrode through-hole of the chip area, 13 is the back electrode pad, 14 is the chip, and 15 is the bonding wire.

[0039] A, B, C, D, E, and F are the serial numbers of the metallization layers distributed on the inner surface, and a, b, c, d, e, and f are the serial numbers of the back electrode pads. Detailed Implementation

[0040] like Figure 1-4 As shown, taking a three-channel diode array ceramic-metal package as an example, the specific implementation of the small surface-mount diode array package structure is as follows:

[0041] The packaging housing base (i.e., the ceramic base body) is a square ceramic base. The ceramic body material is 95% or more Al2O3 ceramic (alumina) or AlN ceramic (aluminum nitride). The external dimensions of the housing (i.e., the square ceramic base) are: length 2.0 mm ± 0.12 mm, width 2.2 mm ± 0.12 mm, height 1.0 mm ± 0.1 mm, internal cavity dimensions are length 1.4 mm, width 1.2 mm, bonding area bottom plane height is 0.4 mm ± 0.06 mm, chip area bottom plane height is 0.6 mm ± 0.06 mm, and border width is 0.4 mm.

[0042] The cover plate (i.e., the encapsulation shell cover) is a square metal cover plate with a composition of 4J42. The dimensions of the cover plate (i.e., the square metal cover plate) are: length 1.85 mm ± 0.1 mm, width 2.05 mm ± 0.1 mm, height 0.2 mm ± 0.05 mm, and the width of the solder ring is 0.45 mm. The solder ring material is gold-tin.

[0043] The sealing ring material is 4J42 / 4J29.

[0044] The base area layout consists of: a bonding area, a chip area, and an external electrode pad area, as follows: Figure 2 , Figure 3 As shown.

[0045] A surface metallization layer is fabricated in the bonding area, chip area, and electrode pad area.

[0046] The bonding region metallization layer 9 is distributed as follows: D, E, and F, located in the upper-middle part of the inner cavity bottom plane. Preferably, the pads D, E, and F have a size of 0.5mm × 0.3mm. Figure 2 As shown.

[0047] The chip region metallization layer 10 is distributed as A, B, and C, located in the lower middle part of the inner cavity bottom plane. Preferably, the A, B, and C pads have a size of 0.85mm × 0.3mm. Figure 2 As shown.

[0048] The electrode pad metallization layer 13 is located on the back of the ceramic base and is distributed as follows: a, b, c, d, e, f. Pads a, b, and c are located below A, B, and C respectively, and pads d, e, and f are located below D, E, and F respectively. Preferably, the pads a, b, c, d, e, and f are all 0.4 mm × 0.6 mm in size, with a spacing of 0.25 mm. Figure 3 As shown.

[0049] Both the bonding region metallization layer 9 and the chip region metallization layer 10 are composed of multiple layers of metal materials, specifically, multiple metal layers: a gold layer as the top layer, a nickel layer as the second layer, and a tungsten layer as the third layer. The top layer is gold, the second layer is nickel, and the third layer is tungsten. The top and second layers are electroplated, while the third layer is created by printing tungsten paste onto ceramic and then curing it. Preferably, the thickness of the gold layer is 1.3–5.7 μm, the nickel layer is 4.0–11.3 μm, and the tungsten layer is 5–30 μm.

[0050] The structure of the metallization layer 13 in the electrode pad area is to first print a tungsten metal layer in a designated area on the outside as the bottom layer, and then solder a metal block on the tungsten metal layer.

[0051] The bonding connections are as follows: A is connected to F, B is connected to E, and C is connected to D.

[0052] The internal and external connections are as follows: A connects to a, B connects to b, C connects to c, D connects to d, E connects to e, and F connects to f.

[0053] The outer casing sealing ring and the cover plate are connected by a fusion seal, such as Figure 1 As shown. The sealing ring and the cover plate are connected by airtight fusion welding with alloy solder, and the pad electrode sheet and the pad metal layer are connected by fusion welding with alloy solder.

[0054] Finally, it should be noted that the above embodiments are merely examples for clear illustration. This utility model includes, but is not limited to, the above embodiments, and it is neither necessary nor possible to exhaustively describe all implementation methods. Those skilled in the art can make other variations or modifications based on the above description. All implementation schemes that meet the requirements of this utility model are within the protection scope of this utility model.

Claims

1. A small surface-mount diode array package structure, characterized in that: The components include a ceramic base body (1), a side cavity (2), a sealing ring (3), a cover plate (4), a cover plate welding ring (5), an inner cavity (6), a bonding area bottom surface (7), a chip area bottom surface (8), a bonding area metallization layer (9), a chip area metallization layer (10), a bonding area electrode through hole (11), a chip area electrode through hole (12), a back electrode pad (13), a chip (14), and a bonding wire (15). The ceramic base body (1) is a multi-layer co-fired ceramic, and the electrode wiring between each ceramic layer is connected through metal vias provided in the corresponding ceramic layers; The side cavity (2), inner cavity (6), bonding area bottom surface (7), chip area bottom surface (8), bonding area electrode through hole (11), and chip area electrode through hole (12) are integrally fabricated in the ceramic base body (1). The bonding area bottom surface (7) is located in the upper region of the bottom of the ceramic base inner cavity, and the chip area bottom surface (8) is located in the lower region of the bottom of the ceramic base inner cavity. The bonding area bottom surface (7) is higher than the chip area bottom surface (8). The bonding region metallization layer (9) is fabricated on the bottom surface (7) of the bonding region, and the chip region metallization layer (10) is fabricated on the bottom surface (8) of the chip region; the bonding region metallization layer (9) is used for the bonding region, the front electrode wiring of the diode and the connection with the external electrode, and the chip region metallization layer (10) is used for the chip assembly region, the back electrode wiring of the diode and the connection with the external electrode. The chip region metallization layer (10) is lower than the bonding region metallization layer (9), and the chip region electrode via (12) is shorter than the bonding region electrode via (11). The bonding region electrode via (11) is located below the bonding region metallization layer (9), and the chip region electrode via (12) is located below the chip region metallization layer (10). They penetrate the ceramic base body and are connected to the corresponding back electrode pads (13) through the via metal. The chip (14) is soldered onto the metallization layer (10) of the chip region, and the front electrode of the chip is bonded to the metallization layer (9) of the bonding region through a bonding wire (15); The cover plate (4) is a ceramic cover plate or a metal cover plate. Cover plate welding rings (5) are made around the cover plate (4). The shape and size of the cover plate welding rings (5) are the same as those of the sealing rings (3). The upper surface of the side cavity (2) is a sealing ring (3), and the cover plate (4) is sealed to the sealing ring (3) by high-temperature welding.

2. The small surface-mount diode array package structure as described in claim 1, characterized in that: The base area is laid out as follows: bonding area, chip area, and external lead-out electrode pad area. A bonding region metallization layer (9) is formed in the bonding region area, a chip region metallization layer (10) is formed in the chip region area, and a back electrode pad (13) is formed in the electrode pad region area.

3. The small surface-mount diode array package structure as described in claim 1, characterized in that: The bonding region metallization layer (9) is distributed as follows: D, E, F, located in the upper middle part of the bottom plane of the inner cavity; The metallization layer (10) in the chip area is distributed as follows: A, B, and C, located in the lower middle part of the bottom plane of the inner cavity; The metallization layer of the electrode pad area of ​​the back electrode pad (13) is located on the back of the ceramic base and is distributed as follows: a, b, c, d, e, f. Pads a, b, and c are located below A, B, and C in sequence, and pads d, e, and f are located below D, E, and F in sequence.

4. The small surface-mount diode array package structure as described in claim 3, characterized in that: The dimensions of pads D, E, and F are 0.5mm × 0.3mm; The dimensions of pads A, B, and C are 0.85mm × 0.3mm; The pads for a, b, c, d, e, and f are all 0.4mm × 0.6mm in size, with a spacing of 0.25mm.

5. The small surface-mount diode array package structure as described in claim 1, characterized in that: The bonding connections are as follows: A is connected to F, B is connected to E, and C is connected to D. The internal and external connections are as follows: A connects to a, B connects to b, C connects to c, D connects to d, E connects to e, and F connects to f.

6. The small surface-mount diode array package structure as described in claim 1, characterized in that: The bonding region metallization layer (9) and the chip region metallization layer (10) are both composed of multiple metal layers, with the top layer being a gold layer, the second layer being a nickel layer, and the third layer being a tungsten layer.

7. The small surface-mount diode array package structure as described in claim 6, characterized in that: The thickness of the surface gold layer is 1.3–5.7 μm, the thickness of the second nickel layer is 4.0–11.3 μm, and the thickness of the third tungsten layer is 5–30 μm.

8. The small surface-mount diode array package structure as described in claim 1, characterized in that: The structure of the metallization layer in the electrode pad area of ​​the back electrode pad (13) is that the bottom layer is a tungsten layer, and a metal block is welded on the tungsten layer.

9. The miniature surface-mount diode array package structure as described in claim 1, characterized in that: The sealing ring and the cover plate are connected by airtight fusion welding using alloy solder, and the pad electrode sheet and the pad metal layer are connected by fusion welding using alloy solder.

10. The small surface-mount diode array package structure as described in claim 1, characterized in that: The ceramic base body is a square ceramic base; The external dimensions of the square ceramic base are: length 2.0 mm ± 0.12 mm, width 2.2 mm ± 0.12 mm, height 1.0 mm ± 0.1 mm, internal cavity dimensions are length 1.4 mm, width 1.2 mm, bonding area bottom plane height is 0.4 mm ± 0.06 mm, chip area bottom plane height is 0.6 mm ± 0.06 mm, and frame width is 0.4 mm. The cover plate is a square metal cover plate; The dimensions of the square metal cover plate are: length 1.85 mm ± 0.1 mm, width 2.05 mm ± 0.1 mm, height 0.2 mm ± 0.05 mm, and weld ring width 0.45 mm.

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