Analog front-end battery cell management device and battery management system with analog front-end battery cell management device

Abstract

The utility model provides an analog front-end battery cell management device and a battery management system with the analog front-end battery cell management device. The analog front-end battery cell management device comprises a main chip circuit and an analog front-end chip circuit, and the analog front-end chip circuit is used for being connected with a battery pack so as to detect the voltage, current and temperature of the battery pack; the analog front-end chip circuit comprises an analog front-end chip cell detection circuit; the analog front-end chip cell detection circuit comprises a lithium battery management front-end chip U1 and N voltage acquisition circuits which are connected in sequence, and N voltage acquisition pins of the lithium battery management front-end chip U1 are connected with N single batteries through the N voltage acquisition circuits respectively; and each voltage acquisition circuit comprises a first triode, a first resistor, a second resistor, a third resistor and a first capacitor which are used for equalizing the voltage of the battery, so that a passive equalization mode is realized, an equalization strategy with low cost is realized, and the monitoring and management precision of the battery pack is improved.

Description

Technical Field

[0001] This application relates to the field of battery management device technology, and more particularly to an analog front-end cell management device and a battery management system having thereon. Background Technology

[0002] In the electric vehicle market, the Battery Management System (BMS) is a key technology ensuring the safe and efficient operation of battery packs. The BMS is responsible for real-time monitoring of parameters such as battery voltage, current, and temperature to ensure the battery operates at its optimal state, extending battery life and improving the overall vehicle safety and reliability. The analog front-end circuitry of the BMS in electric vehicles is primarily used to monitor the voltage and temperature of individual battery cells, as well as changes in current during charging and discharging. High-precision analog signal processing technology ensures the accuracy of the monitoring data, providing reliable foundational data for the electric vehicle's control system, thereby optimizing energy management and vehicle performance.

[0003] In electric vehicle battery packs, voltage imbalance is common due to differences in the characteristics of individual cells. Analog front-end circuit design needs to incorporate equalization management technology to ensure that each cell remains balanced during charging and discharging, thereby improving the overall performance and lifespan of the battery pack. However, existing equalization management technologies employ active balancing to address cell voltage imbalances, typically requiring more complex circuit designs and more components, leading to increased system costs. Active balancing systems may also generate more heat, increasing the complexity of heat dissipation design. Furthermore, existing analog front-end circuits need improvement in charge / discharge control management, energy consumption reduction, and interference immunity. Summary of the Invention

[0004] This application provides a simulated front-end cell management device and a battery management system having the same, a simple balancing circuit, and improved monitoring and management accuracy of the battery pack. The technical solution of this application is as follows:

[0005] In a first aspect, embodiments of this application provide a simulated front-end cell management device, characterized in that the device includes a main chip circuit and a simulated front-end chip circuit, the main chip circuit includes a microcontroller connected to the simulated front-end chip circuit, the simulated front-end chip circuit is used to connect to a battery pack to detect the voltage, current and temperature of the battery pack; the simulated front-end chip circuit includes a simulated front-end chip cell detection circuit and a simulated front-end chip charge and discharge protection circuit;

[0006] The analog front-end chip cell detection circuit includes a lithium battery management front-end chip U1 and N voltage acquisition circuits connected in sequence. The N voltage acquisition pins of the lithium battery management front-end chip U1 are respectively connected to N individual cells through the N voltage acquisition circuits.

[0007] The voltage acquisition circuits all include a first transistor, a first resistor, a second resistor, a third resistor, and a first capacitor for balancing battery voltage;

[0008] For each voltage acquisition circuit in the Nth to the second voltage acquisition circuits connected in sequence, the collector of the first transistor is connected to the single cell and the first terminal of the second resistor through the first resistor, the second terminal of the second resistor is connected to the lithium battery management front-end chip U1, the emitter of the first transistor is connected to the first terminal of the second resistor of the adjacent voltage acquisition circuit, the base of the first transistor is connected to the second terminal of the second resistor of the adjacent voltage acquisition circuit through the third resistor, the first terminal of the first capacitor is connected to the second terminal of the second resistor, and the second terminal of the first capacitor is connected to the second terminal of the second resistor of the adjacent voltage acquisition circuit; the first terminal of the second resistor of the Nth voltage acquisition circuit is connected to the B+ interface of the battery pack.

[0009] For the first voltage acquisition circuit, the emitter of the first transistor is grounded through a resistor, and the base of the first transistor is connected to the B- interface of the battery pack through the third resistor.

[0010] In some implementations, the analog front-end chip charge / discharge protection circuit is connected to the microcontroller;

[0011] The analog front-end chip charge / discharge protection circuit includes a field-effect transistor (FET) Q16, a transistor Q13, FETs Q1 to Q4, and FETs Q9 to Q12. The gate of FET Q16 is connected to the pre-charge control terminal PCHG of the lithium battery management front-end chip U1 via a resistor. The source of FET Q16 is connected to the B- interface of the battery pack via a capacitor. The drain of FET Q16 is connected to the drains of FETs Q1 to Q4 and the drains of FETs Q9 to Q12. The gates of FETs Q9 to Q12 are connected to the transistors via resistors. The collector of transistor Q13 is connected to the collector of transistors Q9 to Q12. The sources of transistors Q9 to Q12 are connected to the drains of their respective transistors via a parallel voltage suppression diode structure. The emitter of transistor Q13 is connected to the charging control terminal CHG of the lithium battery management front-end chip U1. The base of transistor Q13 is connected to CHG and ground via two resistors. The gates of transistors Q9 to Q12 are connected to the discharging control terminal DGS of the lithium battery management front-end chip U1 via resistors. The sources of transistors Q9 to Q12 are connected to the drains of their respective transistors via a parallel voltage suppression diode structure.

[0012] In some implementations, pin RS1 of the lithium battery management front-end chip U1 is connected to the B- interface of the battery pack through resistor R71, and pin RS2 of the lithium battery management front-end chip U1 is connected to the B- interface of the battery pack through resistor R72 and a parallel resistor structure. A capacitor C18 is connected between pin RS1 and pin RS2, and the two ends of the capacitor C18 are grounded through capacitor C19 and capacitor C20 respectively.

[0013] In some implementations, the parallel voltage suppression diode structure includes multiple voltage suppression diodes connected in parallel.

[0014] In some implementations, the device further includes a warehouse transportation mode control circuit, which is connected to the microcontroller;

[0015] The warehouse operation mode control circuit includes a MOSFET Q19 and an optocoupler U23. The source of the MOSFET Q19 is connected to the battery voltage VBAT, the drain of the MOSFET Q19 is grounded through a resistor R115, the gate of the MOSFET Q19 is connected to the first terminal of a resistor R116, the second terminal of a resistor R116 is connected to the battery voltage VBAT, the drain of the MOSFET Q19 is connected to the battery voltage VBAT through a pin H6, and the drain of the MOSFET Q19 is also connected to the SHIP input signal. The first terminal of the resistor R116 is connected to the input terminal of the optocoupler U23 through a resistor R126, and the output terminal of the optocoupler U23 outputs the SHIP mode control signal.

[0016] In some implementations, the device further includes a communication circuit connected to the microcontroller; the communication circuit includes a 485 transceiver and its peripheral circuitry, wherein the 485 transceiver is model SP3485EEN.

[0017] In some implementations, the main chip circuit further includes a crystal oscillator circuit, a reset circuit, a download circuit, a BOOT enable circuit, and a power supply circuit, all of which are connected to the microcontroller.

[0018] In some implementations, the T1, T2, and T3 pins of the lithium battery management front-end chip U1 are connected to temperature resistors to collect temperature data of the battery pack.

[0019] In some implementations, the lithium battery management front-end chip U1 is model SH367309.

[0020] Secondly, embodiments of this application provide a battery management system, including: the simulated front-end cell management device described in the first aspect.

[0021] The technical solution provided in this application has at least the following beneficial effects:

[0022] The passive balancing circuit design, implemented through a simulated front-end chip cell detection circuit, is more suitable for small- to medium-sized battery packs. It boasts low cost, simple design, and high stability. Energy management is achieved through simple discharge during charging, helping to prevent overcharging or over-discharging. The simulated front-end chip charge / discharge protection circuit includes interface circuits for discharge, charging, and pre-charge modes. Multiple MOSFETs are used to protect the circuit and control the charging and discharging process. Warehouse and transportation mode control functionality is implemented, dynamically adjusting the battery pack's operating state according to the actual storage and transportation environment to ensure optimal performance and safety under different usage scenarios. High-precision analog signal processing technology ensures the accuracy of monitoring data and charge / discharge control management functions. This provides reliable basic data for the electric vehicle control system, thereby optimizing energy management and vehicle performance.

[0023] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0024] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application, and do not constitute an undue limitation of this application.

[0025] Figure 1 This is a block diagram illustrating a simulated front-end cell management device according to an exemplary embodiment.

[0026] Figure 2 This is a circuit diagram illustrating a simulated front-end chip cell detection circuit according to an exemplary embodiment.

[0027] Figure 3 This is a circuit diagram illustrating a charge / discharge protection circuit for an analog front-end chip according to an exemplary embodiment.

[0028] Figure 4 This is a circuit diagram illustrating a warehouse operation mode control circuit according to an exemplary embodiment.

[0029] Figure 5 This is a circuit diagram illustrating a communication circuit according to an exemplary embodiment.

[0030] Figure 6 This is a circuit diagram of a main chip circuit according to an exemplary embodiment. Detailed Implementation

[0031] The technical solutions of the embodiments of this application will be described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0032] In the following description, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0033] Furthermore, in this application, directional terms such as "upper" and "lower" are defined relative to the orientation of the components shown in the accompanying drawings. It should be understood that these directional terms are relative concepts, used for relative description and clarification, and can change accordingly depending on the orientation of the components in the accompanying drawings.

[0034] In this application, unless otherwise expressly specified and limited, the term "connection" shall be interpreted broadly. For example, "connection" may be a fixed connection, a detachable connection, or an integral part; it may be a direct connection or an indirect connection through an intermediate medium.

[0035] Figure 1 This is a block diagram illustrating a simulated front-end cell management device according to an exemplary embodiment. (Refer to...) Figure 1 The simulated front-end cell management device may include: a main chip circuit and a simulated front-end chip circuit. The main chip circuit includes a microcontroller connected to the simulated front-end chip circuit. The simulated front-end chip circuit is used to connect to a battery pack to detect the voltage, current, and temperature of the battery pack. The simulated front-end chip circuit includes a simulated front-end chip cell detection circuit and a simulated front-end chip charge / discharge protection circuit.

[0036] The main chip circuit includes a microcontroller, which is connected to the analog front-end chip cell detection circuit; for example... Figure 2 As shown, the analog front-end chip cell detection circuit includes a lithium battery management front-end chip U1 and N voltage acquisition circuits connected in sequence. The N voltage acquisition pins of the lithium battery management front-end chip U1 are respectively connected to N individual batteries through the N voltage acquisition circuits.

[0037] The voltage acquisition circuits all include a first transistor, a first resistor, a second resistor, a third resistor, and a first capacitor for balancing battery voltage;

[0038] For each voltage acquisition circuit in the Nth to the second voltage acquisition circuits connected in sequence, the collector of the first transistor is connected to the single cell and the first terminal of the second resistor through the first resistor, the second terminal of the second resistor is connected to the lithium battery management front-end chip U1, the emitter of the first transistor is connected to the first terminal of the second resistor of the adjacent voltage acquisition circuit, the base of the first transistor is connected to the second terminal of the second resistor of the adjacent voltage acquisition circuit through the third resistor, the first terminal of the first capacitor is connected to the second terminal of the second resistor, and the second terminal of the first capacitor is connected to the second terminal of the second resistor of the adjacent voltage acquisition circuit; the first terminal of the second resistor of the Nth voltage acquisition circuit is connected to the B+ interface of the battery pack.

[0039] For the first voltage acquisition circuit, the emitter of the first transistor is grounded through a resistor, and the base of the first transistor is connected to the B- interface of the battery pack through the third resistor.

[0040] In some embodiments, the T1, T2, and T3 pins of the lithium battery management front-end chip U1 are connected to temperature resistors to collect battery temperature data.

[0041] The external battery pack collects battery data through an analog front-end chip circuit, processes the collected signals through the main chip circuit, and transmits the data through the signal transmission module.

[0042] Optionally, the lithium battery management front-end chip U1 is model SH367309. This chip is a highly integrated, precise monitoring, low-power 5-16 series lithium battery management front-end chip U1 with multiple protections and communication interfaces. It is suitable for efficient and safe battery management systems and can detect the voltage, current, and temperature data of the battery cells. The first transistor is model SS8050.

[0043] Therefore, when the voltage of some individual cells in the battery pack is too high, a resistor is connected to reduce the voltage of these cells and achieve balance. This is achieved by a first transistor, which conducts when a cell's voltage is detected to be higher than a set value, discharging through the resistor and reducing the voltage. When the battery voltage returns to the normal range, the first transistor deactivates, closing the discharge circuit of the resistor.

[0044] As can be seen, the first transistor in the voltage acquisition circuit is used for battery voltage balancing. When the voltage of a certain battery cell is higher than that of other cells, the lithium battery management front-end chip U1 will drive the corresponding first transistor to conduct, release some energy through the resistor, and gradually pull the voltage down to the same level as other battery cells, thus achieving a passive balancing method.

[0045] The working principle of the voltage balancing mechanism is as follows: pins 1-17 of the lithium battery management front-end chip U1 acquire the voltage value of a single battery cell. When in acquisition mode, VC1-17 are in a high-impedance analog input state, and the single battery cell voltage is acquired through a 1KΩ resistor. When there is a voltage difference between the batteries or the voltage difference is too large, the acquisition I / O port detects the voltage difference and outputs a high level. Taking VC16 and VC15 as an example, when there is a 1V voltage difference between VC15 and VC16, the I / O port detects the voltage difference, VC15 outputs a high level, and the corresponding first transistor conducts. VC16, 51Ω, and VC15 form a loop, and the balancing current is about 0.02A. At this time, during the discharge stage, the single battery voltage at the VC16 terminal is pulled down to balance the single battery voltage at the VC15 terminal.

[0046] The simulated front-end cell management device of this application realizes passive balancing circuit design through simulated front-end chip cell detection circuit, which is more suitable for small and medium-sized battery packs. It has low cost, simple design and high stability. Energy management is achieved through simple discharge during charging, which helps to avoid overcharging or over-discharging of the battery.

[0047] In some embodiments, the analog front-end chip charge / discharge protection circuit is connected to the microcontroller; such as Figure 3 As shown, the analog front-end chip charge / discharge protection circuit includes a field-effect transistor (FET) Q16, a transistor Q13, FETs Q1 to Q4, and FETs Q9 to Q12. The gate of FET Q16 is connected to the pre-charge control terminal PCHG of the lithium battery management front-end chip U1 via a resistor. The source of FET Q16 is connected to the B- interface of the battery pack via a capacitor. The drain of FET Q16 is connected to the drains of FETs Q1 to Q4 and the drains of FETs Q9 to Q12. The gates of FETs Q9 to Q12 are connected to the transistors Q13 and Q14 via resistors. The collector of transistor Q13 is connected to the collector of transistors Q9 to Q12. The sources of transistors Q9 to Q12 are connected to the drains of their respective transistors via a parallel voltage suppression diode structure. The emitter of transistor Q13 is connected to the charging control terminal CHG of the lithium battery management front-end chip U1. The base of transistor Q13 is connected to CHG and ground via two resistors. The gates of transistors Q9 to Q12 are connected to the discharging control terminal DGS of the lithium battery management front-end chip U1 via resistors. The sources of transistors Q9 to Q12 are connected to the drains of their respective transistors via a parallel voltage suppression diode structure.

[0048] Therefore, during the charging phase, the pre-charge control terminal PCHG and the charging control terminal CHG are connected to a high level, and the B+ interface is connected to positive power. Figure 2Resistors R2 and R113 in the circuit divide the voltage, with R113 being positively charged. During the charging phase, pin 3 of Q12 is grounded. Since CHG is high, Q9, Q10, Q11, and Q12 are all turned on, and pin 2 of Q12 is also pulled to ground. At this time, because it's charging, pin 3 of Q1 is high, and pin 2 is grounded, so the body diode of Q1 is turned on, and the charging circuit operates normally. When the battery is discharging: First, the discharge control terminal DGS is connected to a high level. During the discharge phase, external devices must be connected to provide power. Therefore... Figure 3 During the discharge phase, terminals U25 and B+ are connected to external devices by default. The battery pack discharges through terminal B+ and reaches terminal U25 via the external device. Since DSG is connected to 3.3V, it passes through Q4, Q3, Q2, and Q1, and pin 3 of Q1 is grounded, so the corresponding MOSFETs are turned on. Because the right end of the body diode of Q12 is positive and the left end is grounded, the body diode is turned on, and pin 3 of Q12 is grounded, so the discharge circuit operates normally.

[0049] In some embodiments, pin RS1 of the lithium battery management front-end chip U1 is connected to the B-interface of the battery pack via resistor R71, and pin RS2 of the lithium battery management front-end chip U1 is connected to the B-interface of the battery pack via resistor R72 and a parallel resistor structure. A capacitor C18 is connected between pins RS1 and RS2, and the two ends of capacitor C18 are grounded via capacitors C19 and C20, respectively. Resistors R71 (10Ω) and R72 (10Ω) mainly serve the functions of current limiting and impedance matching. Capacitors C18, C19, C20, and resistors R71 and R72 together form a simple filter network. The voltage across the R74-R79 parallel circuit structure can be acquired through pins RS1 and RS2. The parallel connection of R74-R79 increases the overcurrent capacity and reduces the total parallel resistance.

[0050] Therefore, the RS1 and RS2 pins acquire the voltage data across the resistor, which is then converted into current data by the ADC.

[0051] In some embodiments, the parallel voltage suppression diode structure includes a plurality of voltage suppression diodes connected in parallel.

[0052] The analog front-end chip charge and discharge protection circuit of this embodiment includes discharge, charge and pre-charge mode interface circuits. By connecting multiple field-effect transistors, the circuit is protected and the charging or discharging process is controlled, thereby improving the monitoring and management accuracy of the battery pack.

[0053] In some embodiments, the device further includes a warehouse transportation mode control circuit, which is connected to the microcontroller; such as Figure 4As shown, the warehouse operation mode control circuit includes a MOSFET Q19 and an optocoupler U23. The source of the MOSFET Q19 is connected to the battery voltage VBAT, the drain of the MOSFET Q19 is grounded through a resistor R115, the gate of the MOSFET Q19 is connected to the first terminal of a resistor R116, the second terminal of a resistor R116 is connected to the battery voltage VBAT, the drain of the MOSFET Q19 is connected to the battery voltage VBAT through a pin H6, and the drain of the MOSFET Q19 is also connected to the SHIP input signal. The first terminal of the resistor R116 is connected to the input terminal of the optocoupler U23 through a resistor R126, and the output terminal of the optocoupler U23 outputs the SHIP mode control signal.

[0054] The purpose of setting up the warehouse operation mode control circuit is to switch the battery module to a sleep state under certain conditions to save power. When H6 is shorted: When H6 is shorted, pins 2 and 1 of H6 are directly connected, which is equivalent to SHIP being directly connected to VBAT at a high level. Therefore, when H6 is shorted, regardless of whether SHIP_C is high or low, SHIP will be high. This exits the warehouse operation mode and generates a reset. When H6 is open: When H6 is open, the gate of Q19 can only be controlled through the optocoupler U23 (referred to as the optocoupler). When SHIP_C is low: The optocoupler is on, and the VBAT terminal forms a loop through R116, R126, and the optocoupler to ground. The gate of Q19 is divided by the voltage across R116, R126, and the optocoupler circuit. At this time, Vgs < Vgs(th), Q19 is in the on state, and SHIP is pulled high. When SHIP_C is high: the optocoupler is not conducting, and the gate of Q19 is pulled high through R116. At this time, Vgs > Vgs(th), and Q19 is in the off state. SHIP is low at this time. Therefore, when H6 is off, SHIP is high when SHIP_C is low, exiting warehouse operation mode; SHIP is low when SHIP_C is high, entering warehouse operation mode.

[0055] The warehousing and transportation mode control circuit in this embodiment ensures the safety and lifespan of the battery pack during long-term storage and transportation by simplifying the chip's workflow and reducing energy consumption. Upon entering warehousing and transportation mode, the chip only maintains basic monitoring functions for the battery pack to prevent over-discharge or other problems, and can return to normal operating mode when necessary. This enables warehousing and transportation mode control, dynamically adjusting the battery pack's operating state according to the actual warehousing and transportation environment to ensure optimal performance and safety under different usage scenarios.

[0056] In some embodiments, the device further includes a communication circuit connected to the microcontroller for data transmission with external devices. Figure 5As shown, the communication circuit includes a 485 transceiver and its peripheral circuits. The model of the 485 transceiver is SP3485EEN. Figure 5 The illustrated RS-485 communication circuit connects the VCC pin of the SP3485EEN to a +3.3V power supply via the microcontroller MCU. To ensure power supply stability, 10uF (C63) and 100nF (C64) capacitors are connected between VCC and GND to filter out power supply noise. The GND pin of the RS-485 transceiver is connected to ground. The RO (Receive Output) pin is connected to the microcontroller's input pin (labeled RS485_RXD, connected to PB11). The DE (Drive Enable) and / RE (Receive Enable) pins are connected and controlled by the microcontroller MCU (labeled RS485_DE_NRE, connected to PG10) to control whether the RS-485 transceiver is in transmit or receive mode. The DI (Drive Input) pin is connected to the microcontroller's output pin (labeled RS485_TXD, connected to PB10). A (485A) and B (485B) are the differential data lines for RS-485 communication. These two lines are connected to the external RS-485 bus via the PZ254V-11-03P header on the right. Line A is pulled up with a 10kΩ resistor, and line B is pulled down with a 10kΩ resistor. Ensure the receiver outputs a high level when the bus is idle or open. A 120Ω resistor is connected between lines A and B for impedance matching. SMBJ6.5CA (U26, U27, U28) are bidirectional TVS (Transient Voltage Suppressor) diodes, connected across the A / B data lines and ground respectively, to protect the circuit from voltage spikes or surges on the RS-485 bus.

[0057] The 485 communication circuit in this embodiment uses differential signals, which has strong anti-interference ability and low error rate.

[0058] In some embodiments, such as Figure 1 As shown, the main chip circuit also includes a crystal oscillator circuit, a reset circuit, a download circuit, a BOOT enable circuit, and a power supply circuit. The crystal oscillator circuit, reset circuit, download circuit, BOOT enable circuit, and power supply circuit are all connected to the microcontroller.

[0059] Thus, the basic system circuit is constructed by connecting the microcontroller (MCU) to external circuitry (reset circuit, crystal oscillator circuit, BOOT enable circuit, and download circuit).

[0060] Optional, such as Figure 6As shown, the microcontroller MCU is model AIR32F103RPT6, using the AIR32F103RPT6 chip as the main chip. It includes an 8MHz crystal oscillator circuit, a reset circuit, a download circuit, a boot enable circuit, and a power supply circuit. During both charging and discharging, the microcontroller MCU is connected to a 3.3V power supply through pins 1, 13, 19, 32, and 48. The crystal oscillator is connected between pins 5 and 6, and pins 5 and 6 of the microcontroller MCU are grounded through capacitors C56 and C57 respectively, forming a clock circuit. Pin 7 of the microcontroller MCU is connected to the reset circuit, pins 42 and 43 are connected to the serial communication port, and pins 46 and 49 are connected to the download port.

[0061] The SH367309 connects to an external battery pack, detecting voltage, current, and temperature. It transmits the data to the MCU, which then relays it to other peripherals via a RS-485 communication circuit. The data collected by the SH367309 is processed by the MCU to monitor battery status and control the operation of the warehouse transportation control circuit, determining whether the SH367309 enters warehouse transportation mode.

[0062] This application also provides a battery management system, which includes the analog front-end cell management device described in the above embodiments.

[0063] The Battery Management System (BMS) is responsible for monitoring parameters such as battery voltage, current, and temperature in real time to ensure that the battery operates in optimal condition, extend battery life, and improve the safety and reliability of the entire vehicle.

[0064] The battery management system of this application embodiment can provide more accurate battery status monitoring, providing strong support for battery safety and performance optimization, thereby improving the overall system reliability and efficiency.

[0065] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only.

[0066] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A simulated front-end battery cell management device, characterized in that, The device includes a main chip circuit and an analog front-end chip circuit. The main chip circuit includes a microcontroller connected to the analog front-end chip circuit. The analog front-end chip circuit is used to connect to a battery pack to detect the voltage, current, and temperature of the battery pack. The analog front-end chip circuit includes an analog front-end chip cell detection circuit and an analog front-end chip charge / discharge protection circuit. The analog front-end chip cell detection circuit includes a lithium battery management front-end chip U1 and N voltage acquisition circuits connected in sequence. The N voltage acquisition pins of the lithium battery management front-end chip U1 are respectively connected to N individual cells through the N voltage acquisition circuits. The voltage acquisition circuits all include a first transistor, a first resistor, a second resistor, a third resistor, and a first capacitor for balancing battery voltage; For each voltage acquisition circuit in the Nth to the second voltage acquisition circuits connected in sequence, the collector of the first transistor is connected to the single cell and the first terminal of the second resistor through the first resistor, the second terminal of the second resistor is connected to the lithium battery management front-end chip U1, the emitter of the first transistor is connected to the first terminal of the second resistor of the adjacent voltage acquisition circuit, the base of the first transistor is connected to the second terminal of the second resistor of the adjacent voltage acquisition circuit through the third resistor, the first terminal of the first capacitor is connected to the second terminal of the second resistor, and the second terminal of the first capacitor is connected to the second terminal of the second resistor of the adjacent voltage acquisition circuit; the first terminal of the second resistor of the Nth voltage acquisition circuit is connected to the B+ interface of the battery pack. For the first voltage acquisition circuit, the emitter of the first transistor is grounded through a resistor, and the base of the first transistor is connected to the B- interface of the battery pack through the third resistor.

2. The analog front-end cell management device according to claim 1, characterized in that, The analog front-end chip charge / discharge protection circuit is connected to the microcontroller. The analog front-end chip charge and discharge protection circuit includes a field-effect transistor Q16, a transistor Q13, field-effect transistors Q1 to Q4, and field-effect transistors Q9 to Q12. The gate of the field-effect transistor Q16 is connected to the pre-charge control terminal PCHG of the lithium battery management front-end chip U1 through a resistor. The source of the field-effect transistor Q16 is connected to the B- interface of the battery pack through a capacitor. The drain of the field-effect transistor Q16 is connected to the drains of the field-effect transistors Q1 to Q4 and the drains of the field-effect transistors Q9 to Q12. The gates of the field-effect transistors Q9 to Q12 are connected to the collector of the transistor Q13 through resistors. The sources of the field-effect transistors Q9 to Q12 are connected to the drains of their respective field-effect transistors through a parallel structure of voltage suppression diodes. The emitter of the transistor Q13 is connected to the charging control terminal CHG of the lithium battery management front-end chip U1. The base of the transistor Q13 is connected to CHG and ground through two resistors respectively. The gates of the field-effect transistors Q9 to Q12 are connected to the discharging control terminal DGS of the lithium battery management front-end chip U1 through resistors. The sources of the field-effect transistors Q9 to Q12 are connected to the drains of their respective field-effect transistors through a parallel structure of voltage suppression diodes.

3. The analog front-end cell management device according to claim 2, characterized in that, Pin RS1 of the lithium battery management front-end chip U1 is connected to the B- interface of the battery pack through resistor R71. Pin RS2 of the lithium battery management front-end chip U1 is connected to the B- interface of the battery pack through resistor R72 and a parallel resistor structure. A capacitor C18 is connected between pin RS1 and pin RS2. The two ends of the capacitor C18 are grounded through capacitor C19 and capacitor C20 respectively.

4. The analog front-end cell management device according to claim 2, characterized in that, The voltage suppression diode parallel structure includes multiple voltage suppression diodes connected in parallel.

5. The analog front-end cell management device according to claim 1, characterized in that, The device also includes a warehouse transportation mode control circuit, which is connected to the microcontroller; The warehouse operation mode control circuit includes a MOSFET Q19 and an optocoupler U23. The source of the MOSFET Q19 is connected to the battery voltage VBAT, the drain of the MOSFET Q19 is grounded through a resistor R115, the gate of the MOSFET Q19 is connected to the first terminal of a resistor R116, the second terminal of a resistor R116 is connected to the battery voltage VBAT, the drain of the MOSFET Q19 is connected to the battery voltage VBAT through a pin H6, and the drain of the MOSFET Q19 is also connected to the SHIP input signal. The first terminal of the resistor R116 is connected to the input terminal of the optocoupler U23 through a resistor R126, and the output terminal of the optocoupler U23 outputs the SHIP mode control signal.

6. The simulated front-end cell management device according to claim 1, characterized in that, The device also includes a communication circuit connected to the microcontroller; the communication circuit includes a 485 transceiver and its peripheral circuits, and the 485 transceiver is model SP3485EEN.

7. The analog front-end cell management device according to claim 1, characterized in that, The main chip circuit also includes a crystal oscillator circuit, a reset circuit, a download circuit, a BOOT enable circuit, and a power supply circuit, all of which are connected to the microcontroller.

8. The analog front-end cell management device according to claim 1, characterized in that, The T1, T2, and T3 pins of the lithium battery management front-end chip U1 are connected to temperature resistors to collect temperature data of the battery pack.

9. The analog front-end cell management device according to claim 1, characterized in that, The lithium battery management front-end chip U1 is model number SH367309.

10. A battery management system, characterized in that, include: The analog front-end cell management device as described in any one of claims 1 to 9.

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