LED video processing circuit and device

Abstract

The utility model discloses an LED video processing circuit and device. The circuit comprises a video signal processing module and at least one video signal transceiver module. The video signal processing module comprises a video interface and a V-By-One interface; the video interface is connected with a video source, the plurality of video signal receiving and transmitting modules are sequentially connected in series and are respectively connected with an LED, and the V-By-One interface is connected with the first video signal receiving and transmitting module. According to the technical scheme provided by the embodiment of the utility model, the video signal processing module adopts the V-By-One interface to carry out video signal transmission, supports video information transmission with 4K super-definition resolution, is higher in transmission rate, supports synchronous transmission of image information and audio information, greatly reduces the number of I / O interfaces occupied during video signal transmission, and improves the transmission efficiency. The display effect of the LED during video projection is improved, and the on-load requirements of medium and large LED application scenes are met.

Description

Technical Field

[0001] This utility model relates to the field of video signal processing technology, and in particular to an LED video processing circuit and device. Background Technology

[0002] When displaying images on medium to large-sized LEDs, the video signal from the video source needs to be processed. Currently, the main processing method involves the TV chip's LCDC interface transmitting the image information from the video source to the LED using RGB888 data format, and then... 2 The S-interface transmits audio information from the video source to the LED. Existing LED video processing methods cannot meet the load requirements of medium and large-scale LED applications, require a large number of I / O interfaces, and produce poor display effects when spliced ​​from multiple video processing devices, failing to achieve overall image integrity and not supporting 4K video signal processing. Utility Model Content

[0003] This invention provides an LED video processing circuit and device to solve the technical problem that existing LED video processing methods occupy too many I / O interfaces and cannot meet the load requirements of medium and large LED application scenarios.

[0004] According to one aspect of the present invention, an LED video processing circuit is provided, comprising: a video signal processing module and at least one video signal transceiver module;

[0005] The video signal processing module includes a video interface and a V-By-One interface; the video interface is connected to a video source, multiple video signal transceiver modules are connected in series and connected to LEDs respectively, and the V-By-One interface is connected to the first video signal transceiver module.

[0006] Optionally, the video signal transceiver module includes: a first SerDes interface, a second SerDes interface, and an RGMII interface;

[0007] The V-By-One interface is connected to the first Serdes interface of the first video signal transceiver module, the second Serdes interfaces of the plurality of video signal transceiver modules are sequentially connected to the first Serdes interface, and the RGMII interface is connected to the LED.

[0008] Optionally, the LED video processing circuit further includes at least one video signal conversion module, which is connected to the video signal transceiver module.

[0009] The first end of the video signal conversion module is connected to the RGMII interface, and the second end of the video signal conversion module is connected to the LED via a network cable.

[0010] Optionally, the LED video processing circuit further includes a filtering module;

[0011] The first end of the filtering module is connected to the video signal processing module, and the second end of the filtering module is connected to the video signal transceiver module.

[0012] Optionally, the filtering module includes a capacitor;

[0013] The first end of the capacitor is connected to the V-By-One interface, and the second end of the capacitor is connected to the first Serdes interface.

[0014] Optionally, the video signal output by the V-By-One interface includes audio signals and image signals.

[0015] Optionally, the video signal transceiver module includes an FPGA chip.

[0016] Optionally, the video signal conversion module includes a gigabit PHY chip.

[0017] Optionally, the video interface includes at least two different types of video signal interfaces.

[0018] According to another aspect of the present invention, an LED video processing circuit is provided, including the LED video processing circuit described in any embodiment of the present invention.

[0019] The technical solution provided in this embodiment of the invention decodes and encodes the video information output from the video source using a video signal processing module. The processed video signal is then transmitted to a video signal transceiver module via a V-By-One interface. This transceiver module transmits its respective controlled video information to the LED, thus projecting the video information from the video source onto the LED for display. This technical solution uses a V-By-One interface for video signal transmission, supports 4K ultra-high-definition video information transmission, has a high transmission rate, and supports simultaneous transmission of image and audio information. This significantly reduces the number of I / O interfaces required for video signal transmission, improves the display effect when projecting video onto the LED, and meets the load requirements of medium to large-sized LED applications.

[0020] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this utility model, nor is it intended to limit the scope of this utility model. Other features of this utility model will become readily apparent from the following description. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of this utility model, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a schematic diagram of the structure of an LED video processing circuit according to an embodiment of the present utility model;

[0023] Figure 2 This is a schematic diagram of another LED video processing circuit provided according to an embodiment of the present utility model;

[0024] Figure 3 This is a schematic diagram of another LED video processing circuit provided according to an embodiment of the present utility model;

[0025] Figure 4 This is a partial structural schematic diagram of an LED video processing circuit provided according to an embodiment of the present utility model. Detailed Implementation

[0026] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the protection scope of the present invention.

[0027] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this utility model are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the utility model described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0028] Figure 1 This is a schematic diagram of an LED video processing circuit according to an embodiment of the present invention. See also... Figure 1The LED video processing circuit 10 includes: a video signal processing module 100 and at least one video signal transceiver module 200; the video signal processing module 100 includes a video interface 110 and a V-By-One interface 120; the video interface 110 is connected to the video source 300, multiple video signal transceiver modules 200 are connected in series and connected to the LED respectively, and the V-By-One interface 120 is connected to the first video signal transceiver module 200.

[0029] Specifically, the video source 300 can be a computer, a video playback box, or other video playback device. The video source 300 outputs 4K, 2K, or other resolution video information to the video signal processing module 100. The video signal processing module 100 can be a TV chip, which decodes and encodes the video information output by the video source 300 and transmits the processed video information to the first video signal transceiver module 200 via the V-By-One interface 120. The V-By-One interface 120 has high-speed transmission capabilities, supports 4K ultra-high-definition video information transmission, and can synchronously transmit image and audio information from the video signal, thereby significantly reducing the number of I / O interfaces required by the video signal processing module 100 and the video signal transceiver module 200. The number of video signal transceiver modules 200 can be adjusted according to the video information output by the video source 300 or the size of the LED screen. For example, ... Figure 1 As shown, the LED video processing circuit 10 is equipped with two video signal transceiver modules 200. Each video signal transceiver module 200 controls the display of a portion of the LED screen. Each video signal transceiver module 200 transmits the video information it controls to the LED screen and sequentially passes the remaining video information to the other video signal transceiver modules 200, thereby projecting the video information from the video source 300 onto the LED screen for display.

[0030] The technical solution provided in this embodiment of the invention decodes and encodes the video information output from the video source using a video signal processing module. The processed video signal is then transmitted to a video signal transceiver module via a V-By-One interface. The video signal transceiver module transmits its respective controlled video information to the LED, thereby projecting the video information from the video source onto the LED for display. This technical solution uses a V-By-One interface for video signal transmission, supports 4K ultra-high-definition video information transmission, has a high transmission rate, and supports simultaneous transmission of image and audio information. This significantly reduces the number of I / O interfaces required for video signal transmission, improves the display effect when projecting video onto the LED, and meets the load requirements of medium to large-sized LED applications.

[0031] Optionally, Figure 2This is a schematic diagram of another LED video processing circuit provided according to an embodiment of the present invention. Based on the above embodiments, see... Figure 2 The video signal transceiver module 200 includes: a first SerDes interface 210, a second SerDes interface 220, and an RGMII interface 230; the V-By-One interface 120 is connected to the first SerDes interface 210 of the first video signal transceiver module 200, the second SerDes interfaces 220 of multiple video signal transceiver modules 200 are sequentially connected to the first SerDes interface 210, and the RGMII interface 230 is connected to the LED.

[0032] Specifically, the first SerDes interface 210 of the first video signal transceiver module 200 can be connected to the V-By-One interface 120 of the video signal processing module 100, and the second SerDes interface 220 of the first video signal transceiver module 200 can be connected to the first SerDes interface 210 of the next video signal transceiver module 200. Multiple video signal transceiver modules 200 are connected in series in this manner. The SerDes interface circuit has a simple structure and good compatibility, supporting multiple protocols such as V-By-One / EDP / LVDS. It also possesses efficient encoding / decoding and transmission capabilities, significantly improving the processing capabilities of LED video source image and audio information. The video signal transceiver module 200 can be an FPGA chip. The video signal transceiver module 200 receives the video signal processed by the V-By-One interface 120 through the first Serdes interface 210, decodes and re-encodes the video information corresponding to its control display, and then transmits it to the LED through the RGMII interface 230. On the other hand, the remaining video signal is transmitted to the next video signal transceiver module 200 through the second Serdes interface 220, until it is transmitted to the last video signal transceiver module 200, so that all the video information is projected onto the LED.

[0033] Optionally, Figure 3 This is a schematic diagram of another LED video processing circuit provided according to an embodiment of the present invention. Based on the above embodiments, see... Figure 3 The LED video processing circuit 10 also includes at least one video signal conversion module 400, which is connected to the video signal transceiver module 200. The first end of the video signal conversion module 400 is connected to the RGMII interface 230, and the second end of the video signal conversion module 400 is connected to the LED via a network cable.

[0034] Specifically, a video signal conversion module 400 is connected one-to-one with a video signal transceiver module 200. The video signal conversion module 400 converts the video signal output from the RGMII interface 230 of the video signal transceiver module 200 into an MDI format signal, which is then transmitted to the LED via a network cable, thereby reducing the number of wires between the LED and the transceiver module and further improving transmission efficiency. Each video signal conversion module 400 may include multiple gigabit PHY chips, and the number of gigabit PHY chips can be set according to the number of I / O interfaces available to the video signal transceiver module 200. For example, when the video signal transceiver module 200 is an FPGA chip, one FPGA chip can support 8-10 gigabit PHY network port outputs.

[0035] Optionally, based on the above embodiments, see below. Figure 3 The LED video processing circuit 10 also includes a filtering module 500; the first end of the filtering module 500 is connected to the video signal processing module 100, and the second end of the filtering module 500 is connected to the video signal transceiver module 200.

[0036] Specifically, the filtering module 500 is connected between the video signal processing module 100 and the video signal transceiver module 200, thereby avoiding signal interference from causing bit errors in signal transmission and improving signal transmission quality. For example, as... Figure 3 The filter module 500 shown can be a capacitor C. The first end of capacitor C is connected to the V-By-One interface 120, and the second end of capacitor C is connected to the first SerDes interface 210. The signal transmission rate between the V-By-One interface 120 and the first SerDes interface 210 is relatively high, and the signal amplitude transmitted on the signal line is relatively low. Even a small DC component on the signal line can affect the encoding and decoding of the high-speed serial signal, causing bit errors and affecting video signal transmission. Connecting a capacitor in series between the V-By-One interface 120 and the first SerDes interface 210 can effectively filter out DC interference and avoid bit errors in signal transmission.

[0037] Figure 4 This is a partial structural schematic diagram of an LED video processing circuit according to an embodiment of the present invention. See also... Figure 3 and Figure 4In one embodiment, the V-By-One interface 120 of the video signal processing module 100 can be connected to the first SerDes interface 210 of a video signal transceiver module 200 via eight pairs of differential signal lines connected in series with capacitors, thereby fulfilling the LED video processing requirement of 20 Ethernet ports. In other embodiments, the V-By-One interface 120 can also be connected to four video signal transceiver modules 200 respectively via eight pairs of differential signal lines, with each video signal transceiver module 200 connected to two pairs of signal lines, thereby fulfilling the LED video processing requirement of 40 Ethernet ports.

[0038] like Figure 4 As shown, the LED video processing circuit 10 includes two video signal transceiver modules 200, namely FPGA1 chip and FPGA2 chip. The V-By-One interface 120 and the first SerDes interface 210 of the FPGA1 chip are connected via eight pairs of differential signal lines. The second SerDes interface 220 of the FPGA1 chip is connected to the first SerDes interface 210 of the FPGA2 chip via eight pairs of signal lines. The V-By-One 0+ series capacitor C... 0+ Then it connects to AD6 of FPGA1, and AF6 of FPGA1 connects to AD6 of FPGA2; V-By-One 0-Series capacitor C 0- Then it connects to AD7 of FPGA1, and AF7 of FPGA1 connects to AD7 of FPGA2; V-By-One 1+ series capacitor C 1+ Then it connects to AD8 of FPGA1, and AF8 of FPGA1 connects to AD8 of FPGA2; V-By-One 1-Series capacitor C 1- Then it connects to AD9 of FPGA1, and AF9 of FPGA1 connects to AD9 of FPGA2; V-By-One 2+ series capacitor C 2+ Then connect to AD10 of FPGA1; connect AF10 of FPGA1 to AD10 of FPGA2; V-By-One 2-series capacitor C 2- It is then connected to AD11 of FPGA1, and AF11 of FPGA1 is connected to AD11 of FPGA2; V-By-One3+ series capacitor C 3+ Then it connects to AD12 of FPGA1, and AF12 of FPGA1 connects to AD12 of FPGA2; V-By-One 3-series capacitor C 3- It is then connected to AD13 of FPGA1, and AF13 of FPGA1 is connected to AD13 of FPGA2; V-By-One 4+ series capacitor C 4+Then it connects to AD14 of FPGA1, and AF14 of FPGA1 connects to AD14 of FPGA2; V-By-One 4-series capacitor C 4- Then it connects to AD15 of FPGA1, and AF15 of FPGA1 connects to AD15 of FPGA2; V-By-One 5+ series capacitor C 5+ Then it connects to AD16 of FPGA1, and AF16 of FPGA1 connects to AD16 of FPGA2; V-By-One 5-series capacitor C 5- It is then connected to AD17 of FPGA1, and AF17 of FPGA1 is connected to AD27 of FPGA2; V-By-One 6+ series capacitor C 6+ Then it connects to AD18 of FPGA1, and AF18 of FPGA1 connects to AD18 of FPGA2; V-By-One 6-series capacitor C 6- It is then connected to AD19 of FPGA1, and AF19 of FPGA1 is connected to AD19 of FPGA2; V-By-One7+ series capacitor C 7+ Then it connects to AD20 of FPGA1, and AF20 of FPGA1 connects to AD20 of FPGA2; V-By-One 7-series capacitor C 7- It is then connected to AD21 of FPGA1, and AF21 of FPGA1 is connected to AD21 of FPGA2. The video signal processing module 100 encodes and decodes the video signal input from the video source 300, and then transmits it to the first Serdes interface 210 of the video signal transceiver module 200 after encoding via the V-By-One interface 120. The audio data in the video signal from the video source 300 is embedded in the V-By-One high-speed serial interface signal transmission link and can be transmitted to the video signal transceiver module 200 along with the video image data. The video signal transceiver module 200 then decodes and recovers part of the audio and video image signals from the first Serdes interface 210, and transmits the remaining video signal to the first Serdes interface 210 of the next video signal transceiver module 200 via the second Serdes interface 220. Existing LED video processing methods use the LCDC interface to transmit the image information from the video source to the LED, requiring 24 signal lines, through I... 2The S-interface requires 5 signal lines to transmit audio information from the video source to the LED, totaling 29 signal lines for synchronized audio and video transmission. In this embodiment, the video signal processing module 100 and the video signal transceiver module 200 only require 16 signal lines to achieve synchronized audio and video transmission, and it supports 4K video signal transmission and processing. Compared to existing technologies, this significantly reduces the number of connections, achieving 4K ultra-high-definition resolution and synchronized audio and video functions with only a small number of I / O pins on the TV chip and FPGA chip.

[0039] Optionally, based on the above embodiments, see below. Figure 1 The video interface 100 includes at least two different types of video signal interfaces.

[0040] Specifically, the video interface 100 can support various types of video signal interfaces, thereby receiving video signals output from different types of video sources 300. For example, the video interface 100 may include video signal interfaces of types such as HDMI 2.0, DP 1.2, HDMI 1.4, DVI, and VGA.

[0041] This utility model embodiment also provides an LED video processing device, which includes the LED video processing circuit provided in any embodiment of this utility model and has the same beneficial effects as the LED video processing circuit provided in any of the above embodiments, and will not be described again here.

[0042] It should be understood that the various forms of the process shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this utility model can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this utility model can be achieved, and this is not limited herein.

[0043] The specific embodiments described above do not constitute a limitation on the scope of protection of this utility model. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this utility model should be included within the scope of protection of this utility model.

Claims

1. An LED video processing circuit, characterized in that, include: A video signal processing module and at least one video signal transceiver module; The video signal processing module includes a video interface and a V-By-One interface; the video interface is connected to a video source, multiple video signal transceiver modules are connected in series and connected to LEDs respectively, and the V-By-One interface is connected to the first video signal transceiver module.

2. The LED video processing circuit according to claim 1, characterized in that, The video signal transceiver module includes: a first SerDes interface, a second SerDes interface, and an RGMII interface; The V-By-One interface is connected to the first Serdes interface of the first video signal transceiver module, and the first Serdes interface of the subsequent video signal transceiver module is sequentially connected to the second Serdes interface of the preceding video signal transceiver module. The RGMII interface is connected to the LED.

3. The LED video processing circuit according to claim 2, characterized in that, The LED video processing circuit further includes at least one video signal conversion module, which is connected to the video signal transceiver module. The first end of the video signal conversion module is connected to the RGMII interface, and the second end of the video signal conversion module is connected to the LED via a network cable.

4. The LED video processing circuit according to claim 2, characterized in that, The LED video processing circuit also includes a filtering module; The first end of the filtering module is connected to the video signal processing module, and the second end of the filtering module is connected to the video signal transceiver module.

5. The LED video processing circuit according to claim 4, characterized in that, The filtering module includes capacitors; The first end of the capacitor is connected to the V-By-One interface, and the second end of the capacitor is connected to the first Serdes interface.

6. The LED video processing circuit according to claim 1, characterized in that, The video signal output by the V-By-One interface includes audio and image signals.

7. The LED video processing circuit according to claim 2, characterized in that, The video signal transceiver module includes an FPGA chip.

8. The LED video processing circuit according to claim 3, characterized in that, The video signal conversion module includes a gigabit PHY chip.

9. The LED video processing circuit according to claim 1, characterized in that, The video interface includes at least two different types of video signal interfaces.

10. An LED video processing device, characterized in that, Includes the LED video processing circuit according to any one of claims 1-9.

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