Si IGBT (Insulated Gate Bipolar Translator) and SiC Mosfet hybrid parallel double-pulse test circuit
By designing a dual-pulse test circuit that combines Si IGBTs and SiC MOSFETs in parallel and controlling the timing of the drive signals, the problems of high cost and high switching losses in the testing of Si IGBTs and SiC MOSFETs are solved, achieving a comprehensive effect of low cost and low switching losses.
Patent Information
- Application Number
- CN202422849600.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-22
- Publication Date
- 2025-11-14
- Estimated Expiration
- 2034-11-22
AI Technical Summary
Existing technologies such as Si IGBTs and SiC MOSFETs suffer from high costs and high switching losses during testing, making it difficult to simultaneously achieve low cost and low switching losses.
Design a dual-pulse test circuit that combines Si IGBTs and SiC MOSFETs in parallel. By controlling the timing of the drive signals of the devices, and utilizing the low cost of Si IGBTs and the low switching loss characteristics of SiC MOSFETs, a dual-pulse drive signal is provided using a bus capacitor and a load inductor to test the switching characteristics and reverse recovery characteristics of the devices.
This approach achieves lower switching losses while reducing costs during testing, combining the advantages of Si IGBTs and SiC MOSFETs.
Smart Images
Figure CN223551835U_ABST
Abstract
Description
Technical Field
[0001] This utility model belongs to the field of power device testing technology, and relates to a dual-pulse test circuit that combines Si IGBT and SiC MOSFET in parallel. Background Technology
[0002] Currently, silicon insulated gate bipolar transistors (Si IGBTs) and silicon carbide metal-oxide-semiconductor field-effect transistors (SiC MOSFETs) are the mainstream in the market. SiC MOSFETs have the advantage of low switching losses, while Si IGBTs have the advantages of low cost and low conduction losses. However, correspondingly, SiC MOSFETs are expensive, and Si IGBTs have high switching losses, which are objective disadvantages. This test scheme combines the advantages of both Si IGBTs and SiC MOSFETs. When testing dual pulses, they are connected in parallel to reduce cost and switching losses. The gate drives of the two are separate, and lower switching losses are obtained by controlling the timing of the drive signals of Si IGBT / SiC MOSFETs.
[0003] To address this, a dual-pulse test circuit combining Si IGBTs and SiC MOSFETs in parallel was designed. Utility Model Content
[0004] The purpose of this invention is to overcome the shortcomings of the existing technology and provide a simple, reasonable, stable, and convenient dual-pulse test circuit that combines Si IGBT and SiC MOSFET in parallel.
[0005] This utility model is achieved through the following technical solution: a dual-pulse test circuit with Si IGBT and SiC MOSFETs connected in parallel, including a test circuit and a bus capacitor disposed on the test circuit. The bus capacitor is supplied with a bus voltage by a high-voltage source. An upper bridge element and a lower bridge element are respectively disposed on the lines connected in parallel with the bus capacitor on the test circuit. The upper bridge element is composed of a Si IGBT silicon power transistor and a SiC MOSFET, with the Q1 terminal of the Si IGBT silicon power transistor and the M1 terminal of the SiC MOSFET serving as switching transistors. The lower bridge element is also composed of a Si IGBT silicon power transistor and a SiC MOSFET, with a signal source connected in parallel to the Q2 terminal of the Si IGBT silicon power transistor and the M2 terminal of the SiC MOSFET, while the M2 and Q2 terminals remain closed. The signal source supplies power to the upper bridge element Q1. The terminal provides a dual-pulse drive signal VGE, and the terminal of the upper bridge element M1 provides a dual-pulse drive signal VGS, thereby testing the switching characteristics of the terminals Q1 and M1 in the upper bridge element and the reverse recovery characteristics of the terminals Q2 and M2 in the lower bridge element.
[0006] Preferably, the signal source is a load inductor, with its two ends connected in parallel to the Q2 terminal of the Si IGBT silicon power transistor and the M2 terminal of the SiC MOSFET silicon carbide metal oxide semiconductor field-effect transistor, respectively. The load inductor provides a dual-pulse drive signal VGE to the Q1 terminal of the upper bridge element and a dual-pulse drive signal VGS to the M1 terminal of the upper bridge element, thereby testing the switching characteristics of the Q1 and M1 terminals of the upper bridge element and the reverse recovery characteristics of the Q2 and M2 terminals of the lower bridge element.
[0007] The beneficial effects of this utility model are as follows:
[0008] The dual-pulse test circuit designed in this invention, which combines Si IGBT and SiC MOSFET in parallel, can achieve both lower switching losses and reduced costs, thus combining the advantages of both Si IGBT and SiC MOSFET. Attached Figure Description
[0009] Figure 1 It is a traditional Si IGBT dual-pulse test circuit.
[0010] Figure 2 This is a traditional SiC MOSFET dual-pulse test circuit.
[0011] Figure 3 This is a schematic diagram of the structure of this utility model.
[0012] Figure 4 This is the test circuit diagram of this utility model. Detailed Implementation
[0013] To enable those skilled in the art to more clearly understand the purpose, technical solution and advantages of this utility model, the present utility model will be further described below in conjunction with the accompanying drawings and embodiments.
[0014] In the description of this utility model, it should be understood that the orientation or positional relationship indicated by terms such as "upper", "lower", "left", "right", "inner", "outer", "horizontal", and "vertical" are based on the orientation or positional relationship shown in the accompanying drawings and are only for the convenience of describing this utility model, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, and therefore should not be construed as a limitation of this utility model.
[0015] The present invention will now be described in detail with reference to the accompanying drawings: Figure 3-4 As shown, a dual-pulse test circuit with a hybrid parallel connection of Si IGBT and SiC MOSFET includes a test circuit 1 and a bus capacitor 2 disposed on the test circuit 1. The bus capacitor 2 is supplied with a bus voltage 3 from a high-voltage source. An upper bridge element 4 and a lower bridge element 5 are respectively disposed on the lines in parallel with the bus capacitor on the test circuit 1. The upper bridge element 4 is composed of a Si IGBT silicon power transistor 6 and a SiC MOSFET silicon metal oxide semiconductor field-effect transistor 7. The Q1 terminal of the Si IGBT silicon power transistor 6 and the M1 terminal of the SiC MOSFET silicon metal oxide semiconductor field-effect transistor 7 serve as switching transistors. The lower bridge element 5 is also composed of a Si IGBT silicon power transistor and a SiC MOSFET silicon metal oxide semiconductor field-effect transistor. A signal source is connected in parallel to the Q2 terminal of the Si IGBT silicon power transistor and the M2 terminal of the SiC MOSFET silicon metal oxide semiconductor field-effect transistor. The signal source controls the upper bridge element 4 Q1. The terminal provides a dual-pulse drive signal VGE, and the terminal of the upper bridge element M1 provides a dual-pulse drive signal VGS, thereby testing the switching characteristics of the Q1 and M1 terminals of the upper bridge element 4 and the reverse recovery characteristics of the Q2 and M2 terminals of the lower bridge element 5.
[0016] The signal source is a load inductor 8. The two ends of the load inductor 8 are connected in parallel with the Q2 terminal of the Si IGBT silicon power transistor and the M2 terminal of the SiC MOSFET silicon carbide metal oxide semiconductor field-effect transistor, respectively. The load inductor 8 provides a double-pulse drive signal VGE to the Q1 terminal of the upper bridge element 4 and a double-pulse drive signal VGS to the M1 terminal of the upper bridge element 4, thereby testing the switching characteristics of the Q1 and M1 terminals of the upper bridge element 4 and the reverse recovery characteristics of the Q2 and M2 terminals of the lower bridge element 5.
[0017] To facilitate understanding, a detailed explanation of the principles behind the above circuit is provided:
[0018] Studies have shown that when both the Si IGBT and SiC MOSFET are turned on simultaneously (i.e., when Ton_delay is 0), the hybrid switch can achieve the lowest conduction loss. This is because the relatively slow turn-on speed of the Si IGBT allows it to achieve zero-voltage turn-on even when both devices are driven simultaneously. Conversely, if Ton_delay is not zero (i.e., the SiC MOSFET turns on first and then the Si IGBT is driven), the hybrid switch loss will actually increase before the Si IGBT is fully turned on due to the higher conduction loss of the SiC MOSFET. Therefore, for the Si / SiC hybrid switch to achieve low switching losses, Ton_delay should be 0.
[0019] Because SiC MOSFETs have higher switching speeds and lower switching losses, SiCMosfets should be turned off before Si IGBTs during turn-off, i.e., Tdoff_delay > 0.
[0020] In summary, the test circuit that combines Si IGBTs and SiC MOSFETs in parallel can achieve both lower switching losses and reduced costs, thus combining the advantages of both Si IGBTs and SiC MOSFETs.
[0021] The specific embodiments described herein are merely illustrative of the principles and effects of this utility model and are not intended to limit the scope of this utility model. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this utility model. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this utility model should still be covered by the claims of this utility model.
Claims
1. A dual-pulse test circuit for a hybrid parallel connection of Si IGBT and SiC MOSFET, comprising a test circuit (1) and a bus capacitor (2) disposed on the test circuit (1), wherein the bus capacitor (2) is applied to the bus capacitor (2) by a bus voltage (3) provided by a high voltage source, characterized in that: The test circuit (1) is equipped with an upper bridge element (4) and a lower bridge element (5) on the line connected in parallel with the bus capacitor. The upper bridge element (4) is composed of a Si IGBT silicon power transistor (6) and a SiC MOSFET silicon metal oxide semiconductor field-effect transistor (7). The Q1 terminal of the Si IGBT silicon power transistor (6) and the M1 terminal of the SiC MOSFET silicon metal oxide semiconductor field-effect transistor (7) serve as switching transistors. The lower bridge element (5) is also composed of a Si IGBT silicon power transistor and a SiC MOSFET silicon metal oxide semiconductor field-effect transistor. A signal source is connected in parallel to the Q2 terminal of the Si IGBT silicon power transistor and the M2 terminal of the SiC MOSFET silicon metal oxide semiconductor field-effect transistor. The M2 terminal and the Q2 terminal are kept off. The signal source controls the Q1 terminal of the upper bridge element (4). The terminal provides a double pulse drive signal VGE, and the terminal of the upper bridge element M1 provides a double pulse drive signal VGS, thereby testing the switching characteristics of the Q1 and M1 terminals of the upper bridge element (4) and the reverse recovery characteristics of the Q2 and M2 terminals of the lower bridge element (5).
2. The dual-pulse test circuit of Si IGBT and SiC MOSFET in parallel according to claim 1, characterized in that: The signal source is a load inductor (8). The two ends of the load inductor (8) are connected in parallel with the Q2 terminal of the Si IGBT silicon power transistor and the M2 terminal of the SiC MOSfet silicon carbide metal oxide semiconductor field-effect transistor, respectively. The load inductor (8) provides a double pulse drive signal VGE to the Q1 terminal of the upper bridge element (4) and a double pulse drive signal VGS to the M1 terminal of the upper bridge element (4), thereby testing the switching characteristics of the Q1 and M1 terminals of the upper bridge element (4) and the reverse recovery characteristics of the Q2 and M2 terminals of the lower bridge element (5).