Chip interface verification device and system
By designing a chip interface verification device and utilizing high-speed and low-speed signal connectors and sub-card groups, the high cost and complexity of the EVB platform in SoC chip testing were solved, enabling rapid iteration and automated testing of multiple chips, reducing EVB area and cost, and improving testing accuracy.
Patent Information
- Application Number
- CN202422925474.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-28
- Publication Date
- 2025-11-14
- Estimated Expiration
- 2034-11-28
AI Technical Summary
The existing EVB platform is costly and complex in SoC chip R&D and testing, making it difficult to effectively support the verification of diverse IPs, which affects test accuracy and reusability.
Design a chip interface verification device, including high-speed and low-speed signal connectors and corresponding sub-card groups. Through a unified interface definition and evaluation board, it supports multiple chips to share verification sub-cards, enabling rapid iteration and automated testing.
It reduces the area and cost of EVB, improves test accuracy and reusability, and supports rapid verification iteration and unified test schemes for multiple chips.
Smart Images
Figure CN223552094U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of chip testing and verification, and more specifically, to a chip interface verification device and system. Background Technology
[0002] EVB (Evaluation Board) is a hardware platform used for testing and verifying chips. It exposes the interface of the chip under test, making it easy for developers to test it directly, check its performance under various extreme conditions, and ensure the stability and reliability of the chip.
[0003] A System-on-Chip (SoC) typically integrates multiple IPs (Intellectual Property). During chip development and testing, the functionality and electrical characteristics of all IPs in the SoC need to be tested and verified. Due to the diversity of IPs, verification schemes vary. Integrating all verification schemes onto a single EVB increases the cost of the EVB, and the increased EVB area can affect the testing accuracy of some IPs. Furthermore, as SoC development iterates, the design of the EVB becomes increasingly complex. Utility Model Content
[0004] In view of this, the purpose of this utility model is to provide a chip interface verification device and method that can be reused multiple times, so as to solve the above problems.
[0005] In a first aspect, this application provides a chip interface verification device, comprising:
[0006] High-speed signal connectors are used for physical connection to various high-speed signal interfaces of the chip under test (DUT) mounted on the evaluation board.
[0007] A low-speed signal connector is used for physical connection with various low-speed signal interfaces of the chip under test disposed on the evaluation board.
[0008] A high-speed signal sub-card group includes a high-speed signal sub-card connector used in pairs and physically connected to each other, and a high-speed interface verification sub-card, wherein the high-speed signal sub-card connector is physically connected to the high-speed signal connector;
[0009] A low-speed signal sub-card group includes a low-speed signal sub-card connector used in pairs and physically connected to each other, and a low-speed interface verification sub-card, wherein the low-speed signal sub-card connector is physically connected to the high-speed signal connector.
[0010] In some embodiments, the high-speed interface verification subcard includes a high-speed interface verification subcard for verifying the electrical characteristics of the high-speed signal interface of the chip under test and a high-speed interface verification subcard for verifying the functional characteristics of the high-speed signal interface of the chip under test.
[0011] In some embodiments, the low-speed interface verification sub-card includes a low-speed interface verification sub-card for verifying the electrical characteristics of the low-speed signal interface of the chip under test and a low-speed interface verification sub-card for verifying the functional characteristics of the low-speed signal interface of the chip under test.
[0012] In some embodiments, the high-speed signal interface is a signal interface with a rate greater than or equal to 500MHz, and the low-speed signal interface is a signal interface with a rate less than 500MHz.
[0013] In some embodiments, the high-speed signal interface is one or more of a MIPI interface, a USB interface, and a PCIe interface, and the low-speed signal interface is one or more of a RGMII, an SDIO interface, and a BT1120 interface.
[0014] In some embodiments, the high-speed interface verification daughter card is a MIPI-electrical characteristics test daughter card, a MIPI-functional test daughter card, a USB-electrical characteristics test daughter card, a USB-functional test daughter card, a PCIE-electrical characteristics test daughter card, or a PCIE-functional test daughter card.
[0015] In some embodiments, the low-speed interface verification sub-card is an RGMII-electrical characteristic test sub-card, an RGMII-functional test sub-card, an SDIO-electrical characteristic test sub-card, an SDIO-functional test sub-card, a BT1120-electrical characteristic test sub-card, or a BT1120-functional test sub-card.
[0016] In some embodiments, when performing electrical characteristic testing and verification, the corresponding S-parameters are imported into an oscilloscope for de-embedding, and the probe of the oscilloscope is physically connected to the verification daughter card for verifying electrical characteristics.
[0017] In some embodiments, the high-speed signal connector and the low-speed signal connector are integrated into the evaluation board.
[0018] Secondly, this application provides a chip interface verification system, comprising:
[0019] The aforementioned chip interface verification device;
[0020] An evaluation board adapted to the chip under test, wherein the chip under test is mounted on the evaluation board.
[0021] The chip interface verification device and system provided by this utility model, through the pre-defined interface between the evaluation board and the verification daughter card, enables different chips to share the same interface verification daughter card, supporting rapid verification iteration in chip development. Furthermore, based on this chip interface verification device, different chips can adopt a unified test network and test scheme, which is beneficial for the development of automated testing. Moreover, the evaluation board adapted to the chip can integrate only basic system circuitry, thereby reducing the area and cost of the evaluation board. And by aggregating multiple verification daughter cards adapted to various interface types, the interface verification of most chips can be completed. Attached Figure Description
[0022] The above and other objects, features and advantages of the present invention will become clearer from the following description of embodiments of the present invention with reference to the accompanying drawings, in which:
[0023] Figure 1 This is a schematic diagram of the chip interface verification system provided by this utility model;
[0024] Figure 2 Examples of high-speed interface verification sub-cards and low-speed interface verification sub-cards are given. Detailed Implementation
[0025] The following description describes embodiments of the present invention based on examples; however, the embodiments of the present invention are not limited to these embodiments. In the detailed description of the embodiments of the present invention below, certain specific details are described in detail. Those skilled in the art can fully understand the embodiments of the present invention without these details. To avoid obscuring the essence of the embodiments of the present invention, well-known methods, processes, and procedures are not described in detail. Furthermore, the accompanying drawings are not necessarily drawn to scale.
[0026] The following examples involve the following terms.
[0027] De-embedding is a crucial technique in high-speed circuit design and testing. Its main purpose is to eliminate the influence of parasitic elements and components on the actual device under test (DUT), thereby obtaining more accurate circuit performance parameters.
[0028] The MIPI (Mobile Industry Processor Interface) is a serial communication interface designed specifically for mobile devices and embedded systems.
[0029] USB, short for Universal Serial Bus, is a widely used serial interface with hot-swappable features, and is widely used in various information and communication products.
[0030] PCIe (Peripheral Component Interconnect Express) is a high-speed serial computer expansion bus standard, mainly used for connecting internal computer hardware components, especially for connecting high-performance devices such as graphics processing units (GPUs), solid-state drives (SSDs), and network interface cards (NICs).
[0031] RGMII (Reduced Gigabit Media Independent Interface) is a network interface standard used for the interface between Gigabit Ethernet chips and PHY chips.
[0032] SDIO (Secure Digital Input / Output) is an interface standard developed based on the SD card interface. It is not only compatible with SD cards, but can also connect to various SDIO interface devices, such as Bluetooth, WIFI, GPS, etc.
[0033] In chip design, S-parameters (Scattering parameters) are a set of key parameters that describe the frequency domain characteristics of a linear passive transmission channel.
[0034] S-parameters (Scattering parameters) are parameters used in electrical testing to describe the electrical behavior of the input and output ports of a linear network under radio frequency signal excitation.
[0035] Figure 1 This is a schematic diagram of the chip interface verification system provided by this utility model. The chip interface verification system includes a chip under test (DUT) 120, an evaluation board 110, and a chip interface verification device 130. The evaluation board 110 can integrate a power management circuit to provide power to the DUT 120 and the connector. The evaluation board 110 can also integrate a communication module to communicate with the DUT 120. The communication between the evaluation board 110 and the DUT 120 can be achieved through various interfaces, depending on the function of the DUT 120 and the design of the evaluation board 110. Several common high-speed signal interfaces and low-speed signal interfaces are shown in the figure. Low-speed signal interfaces include, for example, RGMII, SDIO, and BT1120 interfaces. High-speed signals include, for example, MIPI, USB, and PCIe interfaces. Here, high-speed signal interfaces are signal interfaces with a rate greater than or equal to a set threshold (e.g., 500MHz), and low-speed signal interfaces are signal interfaces with a rate less than the set threshold (e.g., 500MHz).
[0036] The interface verification daughter card, as an extension of the evaluation board, is used for physical connection to the corresponding interface to perform electrical characteristic tests, such as physical layer compliance testing for MIPI interfaces; and functional tests, such as data transmission testing for USB interfaces. High-speed signal connector 131 and low-speed signal connector 132 are standard and universal high-speed and low-speed signal connectors, supporting at least several common high-speed and low-speed signal interfaces. High-speed signal connector 131 and low-speed signal connector 132 can be integrated into the evaluation board 110.
[0037] The high-speed interface verification daughter card 142 is physically connected to a high-speed signal interface of the chip under test 120 to test and verify that high-speed signal interface. As shown in the figure, the high-speed interface verification daughter card 142 is physically connected to the high-speed signal connector 131 through the high-speed signal daughter card connector 141. The low-speed interface verification daughter card 151 is physically connected to a low-speed signal interface of the chip under test 120 to test and verify that low-speed signal interface. As shown in the figure, the low-speed interface verification daughter card 151 is physically connected to the low-speed signal connector 132 through the low-speed signal daughter card connector 153.
[0038] Verification daughter cards and daughter card connectors are used in pairs during evaluation board verification. Currently, there is no universal daughter card connector that can be used for various chips and evaluation boards. However, we can summarize the common interface types in chips and prepare corresponding interface verification daughter cards and daughter card connectors for each interface type. Then, by using the corresponding interface verification daughter cards and daughter card connectors to test and verify each interface type in a SoC, we can basically complete the interface testing and verification of the SoC.
[0039] Figure 1 In the illustrated device, the high-speed interface verification daughter card 142 can be categorized into a high-speed signal daughter card for electrical characteristic testing and verification and a high-speed signal daughter card for functional testing and verification. Similarly, the low-speed interface verification daughter card 151 can be categorized into a low-speed signal daughter card for electrical characteristic testing and verification and a low-speed signal daughter card for functional testing and verification. Electrical characteristic testing and verification refers to testing and verifying the electrical characteristics of the interface, such as voltage levels, signal timing, jitter, and eye diagram analysis. Therefore, in Figure 1 The document also provides six signal test nodes for electrical characteristic testing and verification: TP1 is the high-speed signal test point for the chip under test (DUT) 120; TP2 is the test point for the high-speed signal connector 131; TP3 is the test point for the high-speed signal connector of the daughter card 142; TP4 is the low-speed signal test point for the DUT 120; TP5 is the test point for the low-speed signal connector 132; and TP6 is the test point for the low-speed signal connector of the daughter card 151. Functional testing and verification will connect peripheral ports 143 and 152 on the daughter card to devices such as camera modules, Wi-Fi, and TF card storage devices to test and verify the peripheral interface functions of the DUT 120.
[0040] exist Figure 1 In the device shown, to ensure the signal integrity of the verification scheme, it is also necessary to perform full-link simulation on verification link 1 and verification link 2 to ensure that the insertion loss, return loss and crosstalk indicators of the signal link meet the protocol specifications of the corresponding interface. At the same time, during electrical characteristic testing and verification, the corresponding S-parameters need to be imported into the oscilloscope for de-embedding. Then, the oscilloscope probe is physically connected to the daughter card used for electrical characteristic testing and verification to eliminate the influence of the connectors added in verification links 1 and 2 on the test results. The calculation process of the S-parameters of link 1 includes the following steps: First, test points TP2 and TP3 are used as the input and output ports of link 1. The incident and reflected waves of test points TP2 and TP3 are measured. Then, the incident and reflected waves of test points TP2 and TP3 are substituted into equations (1) to (3) to obtain the S-parameters of link 1:
[0041] S= (1)
[0042] = = (2)
[0043] = = (3)
[0044] Where a1 and a2 are the incident waves at test points TP2 and TP3, respectively, b1 and b2 are the reflected waves at test points TP2 and TP3, and S represents the S-parameter matrix.
[0045] The calculation process of the S-parameters of link 2 is to take test points TP5 and TP6 as the input and output ports of link 2, then measure the incident and reflected waves of test points TP5 and TP6, and substitute them into the above equations (1) to 3 to obtain the S-parameters of link 2.
[0046] Figure 2 Given Figure 1Examples of high-speed interface verification daughterboard 142 and low-speed interface verification daughterboard 151 are provided. High-speed interface verification daughterboard 142 includes: MIPI-electrical characteristic test daughterboard 1, USB-electrical characteristic test daughterboard 3, PCIE-electrical characteristic test daughterboard 5, and MIPI-functional test daughterboard 2, USB-functional test daughterboard 4, and PCIE-functional test daughterboard 6. Low-speed interface verification daughterboard 151 includes: RGMII-electrical characteristic test daughterboard 7, SDIO-electrical characteristic test daughterboard 9, BT1120-electrical characteristic test daughterboard 11, and RGMII-functional test daughterboard 8, SDIO-functional test daughterboard 10, and BT1120-functional test daughterboard 12.
[0047] For the device provided by this utility model, although the models and specifications of SoCs are different during the development and verification process of different SOC platforms, their high-speed and low-speed interfaces have a large degree of consistency. Therefore, this device can realize the sharing of interface verification daughter cards between different chips through the well-planned interface definition between the evaluation board and the verification daughter card, so as to support the rapid verification iteration of chip development. Furthermore, based on this chip interface verification device, different chips can adopt a unified test network and test scheme, which is conducive to the development of automated testing.
[0048] Furthermore, the verification method corresponding to the aforementioned device may include the following steps:
[0049] Step 1: Select an evaluation board based on the chip model and choose various daughter cards according to the verification requirements;
[0050] Step 2: If high-speed signal electrical characteristic testing is required, the corresponding S-parameters need to be imported into the oscilloscope for de-embedding. Then, the oscilloscope probe is connected to, for example... Figure 2 Sub-cards 1, 3, and 5 were tested.
[0051] Step 3, if you want to perform a high-speed signal function test, select, for example... Figure 2 Then, connect the corresponding peripherals (MIPI selects the image sensor, USB selects the USB flash drive, and PCIE selects another chip for docking) to the daughter cards 2 / 4 / 6, and perform functional tests.
[0052] Step 4: If low-speed signal electrical characteristic testing is required, the corresponding S-parameters need to be imported into the oscilloscope for de-embedding. Then, the oscilloscope probe is connected to, for example... Figure 2 Sub-cards 7 / 9 / 11 were tested.
[0053] Step 5: If you want to perform a low-speed signal function test, select, for example... Figure 2The daughter cards 8 / 10 / 12 are then physically connected to the corresponding peripherals (RGMII selects the Ethernet transceiver chip, SDIO selects the wireless module, and BT1120 selects the video bridging chip), and functional tests are performed.
[0054] The embodiments of this utility model have been described above, but these embodiments do not exhaustively describe all details, nor do they limit the utility model to only the specific embodiments described. Obviously, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the embodiments of this utility model, thereby enabling those skilled in the art to make good use of the embodiments of this utility model and modifications based on them. The embodiments of this utility model are limited only by the claims and their full scope and equivalents.
Claims
1. A chip interface verification device, comprising: High-speed signal connector, used for physical connection to the high-speed signal interface of the chip under test set on the evaluation board; A low-speed signal connector is used for physical connection with the low-speed signal interface of the chip under test disposed on the evaluation board. A high-speed signal daughter card connector and a high-speed interface verification daughter card are used together and physically connected, wherein the high-speed signal daughter card connector is physically connected to the high-speed signal connector; A low-speed signal daughter card connector and a low-speed interface verification daughter card are used together and physically connected, wherein the low-speed signal daughter card connector is physically connected to the high-speed signal connector.
2. The chip interface verification device according to claim 1, wherein, The high-speed interface verification sub-card includes: a high-speed interface verification sub-card for verifying the electrical characteristics of the high-speed signal interface of the chip under test and a high-speed interface verification sub-card for verifying the functional characteristics of the high-speed signal interface of the chip under test.
3. The chip interface verification device according to claim 1, wherein, The low-speed interface verification sub-card includes: a low-speed interface verification sub-card for verifying the electrical characteristics of the low-speed signal interface of the chip under test and a low-speed interface verification sub-card for verifying the functional characteristics of the low-speed signal interface of the chip under test.
4. The chip interface verification device according to claim 1, wherein, The high-speed signal interface has a speed greater than or equal to 500MHz, and the low-speed signal interface has a speed less than 500MHz.
5. The chip interface verification device according to claim 1, wherein, The high-speed signal interface is a MIPI interface, a USB interface, or a PCIE interface, and the low-speed signal interface is an RGMII interface, an SDIO interface, or a BT1120 interface.
6. The chip interface verification device according to claim 2, wherein, The high-speed interface verification sub-card is a MIPI-electrical characteristic test sub-card, a MIPI-functional test sub-card, a USB-electrical characteristic test sub-card, a USB-functional test sub-card, a PCIE-electrical characteristic test sub-card, or a PCIE-functional test sub-card.
7. The chip interface verification device according to claim 3, wherein, The low-speed interface verification sub-card is RGMII-Electrical Characteristics Test Sub-card, RGMII-Functional Test Sub-card, SDIO-Electrical Characteristics Test Sub-card, SDIO-Functional Test Sub-card, BT1120-Electrical Characteristics Test Sub-card, or BT1120-Functional Test Sub-card.
8. The chip interface verification device according to claim 2 or 3, wherein, During electrical characteristic testing and verification, the corresponding S-parameters are imported into the oscilloscope for de-embedding, and the oscilloscope probe is physically connected to the verification daughter card for verifying electrical characteristics.
9. The chip interface verification device according to claim 1, wherein, The high-speed signal connector and the low-speed signal connector are integrated in the evaluation board.
10. A chip interface verification system, comprising: The chip interface verification apparatus as described in any one of claims 1 to 8; An evaluation board adapted to the chip under test, wherein the chip under test is mounted on the evaluation board.