Gallium nitride MOSFET conduction loss power limiting improved circuit

Abstract

The utility model discloses an improved circuit for limiting conduction loss power of a gallium nitride MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor). Comprising a signal input end, a control signal processing module connected with the signal input end, a driving module connected with the control signal processing module, a first MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) and a second MOSFET which are respectively connected with the driving module, a first sampling circuit connected with the first MOSFET, and a second sampling circuit connected with the second MOSFET, the feedback processing module is respectively connected with the first sampling circuit, the second sampling circuit and the control signal processing module, the first sampling circuit comprises a second triode and a third triode, the base electrode of the second triode is connected with the source electrode of the first MOSFET tube through a second diode and a first diode in sequence, and the base electrode of the third triode is connected with the source electrode of the second MOSFET tube; the source electrode of the first MOSFET tube is connected with the emitter electrode of the second triode through a fourth diode, the emitter electrode of the second triode is connected with the base electrode of the third triode through a fourth resistor, the sampling precision is improved, and the protection effect and the working stability can be further improved.

Description

Technical Field

[0001] This utility model belongs to the field of audio power amplifiers, and in particular relates to an improved circuit for limiting the conduction loss power of gallium nitride MOSFETs. Background Technology

[0002] Gallium nitride (GaN) MOSFETs are a type of field-effect transistor based on gallium nitride (GaN) and aluminum gallium nitride (AlGaN). Due to GaN's high breakdown electric field, high saturation velocity, and good temperature characteristics, GaN MOSFETs have broad application prospects in high-power, high-frequency energy conversion and high-frequency microwave communication, such as in professional audio power amplifiers. However, when operating under extreme conditions (high temperature, overload, load short circuit), the maximum conduction loss power limit of the GaN MOSFET cannot be adaptively adjusted in real-time according to changes in the GaN junction temperature. Therefore, a rapid increase in the junction temperature of the GaN MOSFET can cause the GaN power transistor to fail. In existing patents, such as CN115276627B published on October 24, 2023, a gallium nitride MOSFET conduction loss power limiting circuit includes a signal input terminal, a first MOSFET and a second MOSFET, a first sampling circuit connected to the first MOSFET for real-time sampling of its operating voltage, a second sampling circuit connected to the second MOSFET for real-time sampling of its operating voltage, a feedback processing module connected to both the first and second sampling circuits for processing the sampled signals according to settings to produce a limit feedback signal, and a driving module for driving the first and second MOSFETs to turn on and off according to the signals. The feedback processing module and the signal input terminal are respectively connected to a control signal processing module for generating control signals input to the driving module to control the on and off of the first and second MOSFETs, thereby forming an automatic power loss limiting structure. The sampling stability of the sampling circuit in this circuit needs improvement during operation; otherwise, it will lead to a certain deviation in sampling accuracy. Therefore, an improved circuit is needed to meet the application requirements. Utility Model Content

[0003] The purpose of this invention is to provide an improved circuit for limiting the conduction loss power of gallium nitride MOSFETs, which improves sampling stability to ensure sampling accuracy and further enhances protection effect and operational stability.

[0004] To achieve this objective, this utility model provides an improved power limiting circuit for gallium nitride MOSFET conduction losses, including a signal input terminal, a control signal processing module connected to the signal input terminal, a drive module connected to the control signal processing module, a first MOSFET and a second MOSFET connected to the drive module, a first sampling circuit connected to the first MOSFET, a second sampling circuit connected to the second MOSFET, and a feedback processing module connected to the first sampling circuit, the second sampling circuit, and the control signal processing module. The first sampling circuit includes a second transistor and a third transistor. The base of the second transistor is connected to the drain of the first MOSFET through a second resistor, and the base of the second transistor is connected to the source of the first MOSFET through a second diode and a first diode in sequence. The negative terminal of the second diode is connected to the negative terminal of the first diode and is connected to the collector of the second transistor through the third diode. The negative terminal of the first diode is connected to ground through the first resistor. The drain of the first MOSFET and the emitter of the second transistor are both connected to the first positive power supply. The source of the first MOSFET is connected to the emitter of the second transistor through the fourth diode. The emitter of the second transistor is connected to the base of the third transistor through the fourth resistor and is also connected to ground through the third resistor. The base of the third transistor is connected to the first positive power supply through the fifth resistor. The emitter of the third transistor is connected to the first positive power supply through the sixth resistor. The collector of the third transistor is connected to the feedback processing module. The collector of the third transistor is also connected to ground through the seventh resistor and the first capacitor.

[0005] Preferably, a first Zener diode is disposed between the negative terminal of the second diode and the negative terminal of the first diode, and the positive terminal of the first Zener diode is connected to the negative terminal of the first diode.

[0006] Preferably, the second sampling circuit includes a fifth transistor and a sixth transistor. The base of the fifth transistor is connected to the source of the second MOSFET through a ninth resistor. The base of the fifth transistor is connected to the drain of the second MOSFET through a sixth diode and a fifth diode in sequence. The positive terminal of the sixth diode is connected to the positive terminal of the fifth diode and to the collector of the fifth transistor through a seventh diode. The positive terminal of the fifth diode is connected to ground through an eighth resistor. The source of the second MOSFET and the emitter of the fifth transistor are both connected to a first negative power supply. The drain of the second MOSFET is connected to the collector of the fifth transistor through an eighth diode. The collector of the fifth transistor is connected to the base of the sixth transistor through an eleventh resistor and is also connected to ground through a tenth resistor. The base of the sixth transistor is connected to the first negative power supply through a twelfth resistor. The emitter of the sixth transistor is connected to the first negative power supply through a thirteenth resistor. The collector of the sixth transistor is connected to the feedback processing module. The collector of the sixth transistor is also connected to ground through a fourteenth resistor and a second capacitor.

[0007] Preferably, a second Zener diode is disposed between the positive terminal of the sixth diode and the positive terminal of the fifth diode, and the positive terminal of the second Zener diode is connected to the positive terminal of the sixth diode.

[0008] Preferably, the feedback processing module includes a first amplifier for comparing the sampled signal of the first sampling circuit and a second amplifier for comparing the sampled signal of the second sampling circuit. The inverting input of the first amplifier is connected to the first sampling circuit, and the non-inverting input of the first amplifier is connected to ground through a sixteenth resistor and to a second positive power supply through a fifteenth resistor to form a first comparison voltage for comparing the sampled signal of the first sampling circuit. The output of the first amplifier is connected to the control signal processing module and to a third power supply through a nineteenth resistor. The non-inverting input of the second amplifier is connected to the second sampling circuit, and the inverting input of the second amplifier is connected to ground through an eighteenth resistor and to a second negative power supply through a seventeenth resistor to form a second comparison voltage for comparing the sampled signal of the second sampling circuit. The output of the second amplifier is connected to the control signal processing module and to a third power supply through a twentieth resistor.

[0009] Preferably, the control signal processing module includes a first AND gate and a second AND gate. The input terminals of the first AND gate are respectively connected to the output terminal of the first amplifier and the first input terminal of the signal input terminal. The input terminals of the second AND gate are respectively connected to the output terminal of the second amplifier and the second input terminal of the signal input terminal. The output terminals of the first AND gate and the second AND gate are respectively connected to the driving module.

[0010] Preferably, the driving module is a MOSFET driver, and the output terminal of the driving module is connected to the gate of the first MOSFET and the gate of the second MOSFET in a one-to-one correspondence.

[0011] Compared with the prior art, the advantages of this utility model are as follows:

[0012] In this invention, improvements to the sampling circuit effectively ensure the accuracy and stability of the real-time sampling signal, improving the accuracy of the processing module in controlling the on / off state of the first and second MOSFETs, thereby further enhancing the protection effect and operational stability. The inclusion of a Zener diode in the sampling circuit effectively ensures stability. In the feedback processing module, the amplifier generates a comparison voltage through resistor division, allowing control of the comparison voltage input via the power supply voltage. With the comparison voltage constant, a proportional increase in the sampling voltage effectively lowers the maximum current limit threshold of the gallium nitride power transistor. Consequently, while the on-resistance of the gallium nitride MOSFET increases due to the rise in junction temperature, the maximum current limit threshold decreases, enabling adaptive real-time limiting of the maximum conduction loss of the gallium nitride power transistor. Attached Figure Description

[0013] Figure 1 This is a circuit structure block diagram of the present invention;

[0014] Figure 2 This is a schematic diagram of the circuit structure of this utility model. Detailed Implementation

[0015] The technical solution of this utility model is described in further detail below with reference to the accompanying drawings, but the scope of protection of this utility model is not limited to the following description.

[0016] like Figure 1-2As shown, this utility model provides an improved circuit for limiting the conduction loss power of a gallium nitride MOSFET, including a signal input terminal 1, a control signal processing module 6 connected to the signal input terminal 1, a drive module 2 connected to the control signal processing module 6, a first MOSFET Q1 and a second MOSFET Q4 connected to the drive module 2 respectively, a first sampling circuit 3 connected to the first MOSFET Q1, a second sampling circuit 4 connected to the second MOSFET Q4, and a feedback processing module 5 connected to the first sampling circuit 3, the second sampling circuit 4, and the control signal processing module 6 respectively. The first sampling circuit 3 includes a second transistor Q2 and a third transistor Q3. The base of the second transistor Q2 is connected to the drain of the first MOSFET Q1 through a second resistor R2. The base of the second transistor Q2 is connected to the source of the first MOSFET Q1 through a second diode D2 and a first diode D1 in sequence. The negative terminal of transistor D2 is connected to the negative terminal of the first diode D1 and is connected to the collector of the second transistor Q2 through the third diode D3. The negative terminal of the first diode D1 is connected to ground through the first resistor R1. The drain of the first MOSFET Q1 and the emitter of the second transistor Q2 are both connected to the first positive power supply VH+. The source of the first MOSFET Q1 is connected to the emitter of the second transistor Q2 through the fourth diode D4. The emitter of the second transistor Q2 is connected to the base of the third transistor Q3 through the fourth resistor R4 and is also connected to ground through the third resistor R3. The base of the third transistor Q3 is connected to the first positive power supply VH+ through the fifth resistor R5. The emitter of the third transistor Q3 is connected to the first positive power supply VH+ through the sixth resistor R6. The collector of the third transistor Q3 is connected to the feedback processing module 5. The collector of the third transistor Q3 is also connected to ground through the seventh resistor R7 and the first capacitor C1. A first Zener diode Z1 is disposed between the negative terminal of the second diode D2 and the negative terminal of the first diode D1, and the positive terminal of the first Zener diode Z1 is connected to the negative terminal of the first diode D1.

[0017] The second sampling circuit 4 includes a fifth transistor Q5 and a sixth transistor Q6. The base of the fifth transistor Q5 is connected to the source of the second MOSFET Q4 through a ninth resistor R9. The base of the fifth transistor Q5 is connected to the drain of the second MOSFET Q4 through a sixth diode D6 and a fifth diode D5 in sequence. The positive terminal of the sixth diode D6 is connected to the positive terminal of the fifth diode D5 and is connected to the collector of the fifth transistor Q5 through a seventh diode D7. The positive terminal of the fifth diode D5 is connected to ground through an eighth resistor R8. The source of the second MOSFET Q4 and the emitter of the fifth transistor Q5 are both connected to the first negative power supply VH. The drain of the second MOSFET Q4 is connected to the collector of the fifth transistor Q5 through the eighth diode D8. The collector of the fifth transistor Q5 is connected to the base of the sixth transistor Q6 through the eleventh resistor R11 and also to ground through the tenth resistor R10. The base of the sixth transistor Q6 is connected to the first negative power supply VH- through the twelfth resistor R12. The emitter of the sixth transistor Q6 is connected to the first negative power supply VH- through the thirteenth resistor R13. The collector of the sixth transistor Q6 is connected to the feedback processing module 5. The collector of the sixth transistor Q6 is also connected to ground through the fourteenth resistor R14 and the second capacitor C2. A second Zener diode Z2 is placed between the positive terminal of the sixth diode D6 and the positive terminal of the fifth diode D5, and the positive terminal of the second Zener diode Z2 is connected to the positive terminal of the sixth diode D6.

[0018] In this embodiment, the source of the first MOSFET Q1 and the drain of the second MOSFET Q4 are connected to the same end of the first capacitor L1. The other end of the first capacitor L1 is connected to the ground line through the third capacitor C3 and the twenty-first resistor R21, forming a filter circuit. The connection of the first positive power supply VH+ and the first negative power supply VH-, as well as the resistance values ​​of each voltage, are set according to actual use.

[0019] The feedback processing module 5 includes a first amplifier OCP1 for comparing the sampled signal of the first sampling circuit 3 and a second amplifier OCP2 for comparing the sampled signal of the second sampling circuit 4. The inverting input terminal of the first amplifier OCP1 is connected to the first sampling circuit 3, and the non-inverting input terminal of the first amplifier OCP1 is connected to ground through the sixteenth resistor R16 and to the second positive power supply VCC+ through the fifteenth resistor R15 to form a first comparison voltage for comparing the sampled signal of the first sampling circuit 3. The output terminal of the first amplifier OCP1 is connected to the control signal processing module 6 and to the third power supply VCC through the nineteenth resistor R19. The non-inverting input terminal of the second amplifier OCP2 is connected to the second sampling circuit 4, and the inverting input terminal of the second amplifier OCP2 is connected to ground through the eighteenth resistor R18 and to the second negative power supply VCC- through the seventeenth resistor R17 to form a second comparison voltage for comparing the sampled signal of the second sampling circuit 4. The output terminal of the second amplifier OCP2 is connected to the control signal processing module 6 and to the third power supply VCC through the twentieth resistor R20. In this embodiment, the comparison structure of the first amplifier OCP1 and the second amplifier OCP2 operates on the same principle. The second positive power supply VCC+, the second negative power supply VCC-, and the third power supply VCC are set according to actual use. In the first amplifier OCP1, the voltage of the second positive power supply VCC+ is divided by the sixteenth resistor R16 and the fifteenth resistor R15 to form a stable first comparison voltage. The magnitude of the first comparison voltage can be controlled by controlling the magnitude of the second positive power supply VCC+. When the overall circuit operates under extreme conditions (high temperature, overload, load short circuit), the junction temperature of the first MOSFET Q1 rises sharply, the on-resistance of the first MOSFET Q1 increases sharply, and the sampling voltage obtained by the first sampling circuit 3 increases proportionally. With the first comparison voltage remaining unchanged, this is equivalent to reducing the maximum current limit threshold of the first MOSFET Q1. Thus, while the on-resistance of the first MOSFET Q1 increases due to the increase in junction temperature, the maximum current limit threshold decreases, thereby enabling adaptive real-time limiting of the maximum conduction loss of the gallium nitride power transistor.

[0020] The control signal processing module 6 includes a first AND gate IC3A and a second AND gate IC3B. The two input terminals of the first AND gate IC3A are respectively connected to the output terminal of the first amplifier OCP1 and the first input terminal PWM+ of the signal input terminal 1. The two input terminals of the second AND gate IC3B are respectively connected to the output terminal of the second amplifier OCP2 and the second input terminal PWM- of the signal input terminal 1. The output terminals of the first AND gate IC3A and the second AND gate IC3B are respectively connected to the drive module 2.

[0021] The driving module 2 is a MOSFET driver, and the output terminal of the driving module 2 is connected to the gate of the first MOSFET Q1 and the gate of the second MOSFET Q4 in a one-to-one correspondence.

[0022] In this embodiment, the sampling principles of the first sampling circuit 3 and the second sampling circuit 4 are the same, and the control principles of the first MOSFET Q1 and the second MOSFET Q4 are the same. During operation, when the first MOSFET Q1 is on, the second transistor Q2 is off. Current flows through the first MOSFET Q1, generating a potential difference across its on-resistance. The first diode D1 is forward-biased, turning off the second transistor Q2. The fourth diode D4 is forward-biased, sampling the first MOSFET Q1. The voltage generated by the current flowing through the on-resistance of the first MOSFET Q1 is then amplified by the base bias resistor (i.e., the fourth resistor R4) of the third transistor Q3 before being input to the feedback processing module 5. When the drive module 2 controls the first MOSFET Q1 to turn off, the first diode D1 and the fourth diode D4 are reverse-biased and cut off, causing the second transistor Q2 to turn on and the third transistor Q3 to turn off, thus obtaining a cycle-by-cycle sampling voltage that varies with the current of the first MOSFET Q1. The sampled voltage is input to the inverting input of the first amplifier OCP1. When the sampled voltage is greater than the first comparison voltage generated by the voltage division of the fifteenth resistor R15 and the sixteenth resistor R16, the first amplifier OCP1 outputs a low level. Then, through the action of the first AND gate IC3A, the input signal of the first input terminal PWM+ is shielded, causing the drive module 2 to work and turn off the first MOSFET Q1. This continues until the current drops below the set threshold, at which point the first amplifier OCP1 outputs a high level and then starts the next cycle, thus achieving current limiting. Therefore, this invention improves sampling stability and ensures sampling accuracy, further enhancing the protection effect and operational stability.

[0023] The above are merely preferred embodiments of this utility model. It should be understood that this utility model is not limited to the forms disclosed herein and should not be construed as excluding other embodiments. It can be used in various other combinations, modifications, and environments, and can be altered within the scope of the concept described herein through the above teachings or related technologies or knowledge. Modifications and variations made by those skilled in the art that do not depart from the spirit and scope of this utility model should be protected within the scope of the appended claims.

Claims

1. An improved circuit for limiting the conduction loss power of a gallium nitride MOSFET, comprising a signal input terminal (1), a control signal processing module (6) connected to the signal input terminal (1), a drive module (2) connected to the control signal processing module (6), a first MOSFET (Q1) and a second MOSFET (Q4) respectively connected to the drive module (2), a first sampling circuit (3) connected to the first MOSFET (Q1), a second sampling circuit (4) connected to the second MOSFET (Q4), and a feedback processing module (5) respectively connected to the first sampling circuit (3), the second sampling circuit (4), and the control signal processing module (6), characterized in that, The first sampling circuit (3) includes a second transistor (Q2) and a third transistor (Q3). The base of the second transistor (Q2) is connected to the drain of the first MOSFET (Q1) through a second resistor (R2). The base of the second transistor (Q2) is connected to the source of the first MOSFET (Q1) through a second diode (D2) and a first diode (D1). The negative terminal of the second diode (D2) is connected to the negative terminal of the first diode (D1) and to the collector of the second transistor (Q2) through the third diode (D3). The negative terminal of the first diode (D1) is connected to ground through a first resistor (R1). The drain of the first MOSFET (Q1) and the emitter of the second transistor (Q2) are both connected to the first positive power supply. The source of the first MOSFET (Q1) is connected to the emitter of the second transistor (Q2) through the fourth diode (D4). The emitter of the second transistor (Q2) is connected to the base of the third transistor (Q3) through the fourth resistor (R4) and is also connected to the ground through the third resistor (R3). The base of the third transistor (Q3) is connected to the first positive power supply (VH+) through the fifth resistor (R5). The emitter of the third transistor (Q3) is connected to the first positive power supply (VH+) through the sixth resistor (R6). The collector of the third transistor (Q3) is connected to the feedback processing module (5). The collector of the third transistor (Q3) is also connected to the ground through the seventh resistor (R7) and the first capacitor (C1).

2. The improved circuit for limiting the conduction loss of a gallium nitride MOSFET according to claim 1, characterized in that, A first Zener diode (Z1) is disposed between the negative terminal of the second diode (D2) and the negative terminal of the first diode (D1), and the positive terminal of the first Zener diode (Z1) is connected to the negative terminal of the first diode (D1).

3. The improved circuit for limiting the conduction loss of a gallium nitride MOSFET according to claim 1, characterized in that, The second sampling circuit (4) includes a fifth transistor (Q5) and a sixth transistor (Q6). The base of the fifth transistor (Q5) is connected to the source of the second MOSFET (Q4) through a ninth resistor (R9). The base of the fifth transistor (Q5) is connected to the drain of the second MOSFET (Q4) through a sixth diode (D6) and a fifth diode (D5) in sequence. The positive terminal of the sixth diode (D6) is connected to the positive terminal of the fifth diode (D5) and is connected to the collector of the fifth transistor (Q5) through a seventh diode (D7). The positive terminal of the fifth diode (D5) is connected to ground through an eighth resistor (R8). The source of the second MOSFET (Q4) and the emitter of the fifth transistor (Q5) are both connected to the first negative power supply (VH-). The drain of the second MOSFET (Q4) is connected to the collector of the fifth transistor (Q5) through the eighth diode (D8). The collector of the fifth transistor (Q5) is connected to the base of the sixth transistor (Q6) through the eleventh resistor (R11) and also to the ground through the tenth resistor (R10). The base of the sixth transistor (Q6) is connected to the first negative power supply (VH-) through the twelfth resistor (R12). The emitter of the sixth transistor (Q6) is connected to the first negative power supply (VH-) through the thirteenth resistor (R13). The collector of the sixth transistor (Q6) is connected to the feedback processing module (5). The collector of the sixth transistor (Q6) is also connected to the ground through the fourteenth resistor (R14) and the second capacitor (C2).

4. The improved circuit for limiting the conduction loss of a gallium nitride MOSFET according to claim 3, characterized in that, A second Zener diode (Z2) is disposed between the positive terminal of the sixth diode (D6) and the positive terminal of the fifth diode (D5), and the positive terminal of the second Zener diode (Z2) is connected to the positive terminal of the sixth diode (D6).

5. An improved circuit for limiting the conduction loss of a gallium nitride MOSFET according to claim 1 or 3, characterized in that, The feedback processing module (5) includes a first amplifier (OCP1) for comparing the sampled signal of the first sampling circuit (3) and a second amplifier (OCP2) for comparing the sampled signal of the second sampling circuit (4). The inverting input terminal of the first amplifier (OCP1) is connected to the first sampling circuit (3), and the non-inverting input terminal of the first amplifier (OCP1) is connected to ground through a sixteenth resistor (R16) and to a second positive power supply (VCC+) through a fifteenth resistor (R15) to form a first comparison voltage for comparing the sampled signal of the first sampling circuit (3). The output terminal of the first amplifier (OCP1) is... The second amplifier (OCP2) is connected to the control signal processing module (6) and to the third power supply (VCC) through the nineteenth resistor (R19); the non-inverting input of the second amplifier (OCP2) is connected to the second sampling circuit (4), the inverting input of the second amplifier (OCP2) is connected to the ground through the eighteenth resistor (R18) and to the second negative power supply (VCC-) through the seventeenth resistor (R17) to form a second comparison voltage for comparing the sampling signal of the second sampling circuit (4), and the output of the second amplifier (OCP2) is connected to the control signal processing module (6) and to the third power supply (VCC) through the twentieth resistor (R20).

6. The improved circuit for limiting the conduction loss of a gallium nitride MOSFET according to claim 5, characterized in that, The control signal processing module (6) includes a first AND gate (IC3A) and a second AND gate (IC3B). The input terminals of the first AND gate (IC3A) are respectively connected to the output terminal of the first amplifier (OCP1) and the first input terminal (PWM+) of the signal input terminal (1). The input terminals of the second AND gate (IC3B) are respectively connected to the output terminal of the second amplifier (OCP2) and the second input terminal (PWM-) of the signal input terminal (1). The output terminals of the first AND gate (IC3A) and the second AND gate (IC3B) are respectively connected to the drive module (2).

7. The improved circuit for limiting the conduction loss of a gallium nitride MOSFET according to claim 1, characterized in that, The driving module (2) is a MOSFET driver, and the output terminal of the driving module (2) is connected to the gate of the first MOSFET (Q1) and the gate of the second MOSFET (Q4) in a one-to-one correspondence.

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