Intermediate frequency signal processing board card based on FPGA

Abstract

The utility model discloses an intermediate frequency signal processing board card based on a field programmable gate array (FPGA). Comprising a high-speed AD conversion chip used for collecting an analog intermediate frequency signal and converting the analog intermediate frequency signal into a digital intermediate frequency signal in an LVDS format; the FPGA chip is used for acquiring a digital intermediate frequency signal and transmitting the digital intermediate frequency signal to the MCU chip; the MCU chip is used for receiving the working clock transmitted by the first crystal oscillator assembly and configuring the clock PLL chip according to the working clock; receiving the digital intermediate frequency signal transmitted by the FPGA chip, and transmitting the digital intermediate frequency signal to a far-end upper computer, so that the far-end upper computer processes the digital intermediate frequency signal; and the clock PLL chip is used for converting the reference clock signal input by the second crystal oscillator component and then outputting the converted reference clock signal into clock signals with different frequencies under the configuration of the MCU chip. According to the scheme provided by the utility model, the board card software development amount is small, the hardware circuit is simple, and the cost is reduced.

Description

Technical Field

[0001] This utility model relates to the field of signal processing technology, and in particular to an FPGA-based intermediate frequency signal processing board. Background Technology

[0002] Currently, existing intermediate frequency (IF) signal processing boards mainly adopt an FPGA+DSP+ARM architecture. The FPGA chip receives digital IF data acquired by the AD conversion chip, performs simple preprocessing, and then transmits it to the DSP chip via a high-speed interface for data algorithm processing. The processed data is then transmitted to the ARM chip, which in turn communicates with the PC. In this approach, communication between multiple processing chips is complex, increasing peripheral circuitry and resulting in high hardware costs, while also making software development difficult. Utility Model Content

[0003] To address the technical challenges of complex peripheral circuits, high costs, and complex software development associated with multiprocessor chips in FPGA+DSP+ARM architectures, this utility model provides an FPGA-based intermediate frequency signal processing board.

[0004] The technical solution of this utility model embodiment is implemented as follows:

[0005] This utility model provides an FPGA-based intermediate frequency (IF) signal processing board, characterized in that the FPGA-based IF signal processing board includes an FPGA chip, an MCU chip, a first crystal oscillator assembly connected to the MCU chip, a high-speed AD converter chip, a clock PLL chip, and a second crystal oscillator assembly connected to the clock PLL chip; wherein the FPGA chip, the MCU chip, the high-speed AD converter chip, and the clock PLL chip are interconnected in pairs; the high-speed AD converter chip is used to acquire analog IF signals and convert the analog IF signals into digital IF signals in LVDS format; the FPGA chip is used to acquire digital IF signals and transmit the digital IF signals to the MCU chip; the MCU chip is used to receive the working clock transmitted by the first crystal oscillator assembly and configure the clock PLL chip according to the working clock; it also receives the digital IF signals transmitted by the FPGA chip and transmits the digital IF signals to a remote host computer so that the remote host computer can process the digital IF signals; the clock PLL chip, under the configuration of the MCU chip, converts the reference clock signal input by the second crystal oscillator assembly and outputs clock signals of different frequencies.

[0006] In one embodiment, the FPGA-based intermediate frequency signal processing board further includes a power conversion chip, which is used to output a power supply voltage to provide power to other devices on the intermediate frequency signal processing board.

[0007] In one embodiment, the FPGA-based intermediate frequency signal processing board further includes a signal input connector and a data output connector; the signal input connector is used to input signals, and the data output connector is used to output signals.

[0008] In one embodiment, the FPGA-based intermediate frequency signal processing board further includes a logic analyzer connector for performing data analysis and processing.

[0009] In one embodiment, the FPGA-based intermediate frequency signal processing board further includes a program loading FLASH chip and a data storage DDR chip. The program loading FLASH chip is used to load the FPGA startup program; the data storage DDR chip is used to store the processed data.

[0010] In one embodiment, the FPGA chip is connected to the digital output of a high-speed AD conversion chip via HP BANK32; the FPGA chip is connected to a data storage DDR chip via HP BANK33 and HP BANK34; the FPGA chip is connected to a program loading FLASH chip via HR BANK0 and HR BANK14; the FPGA chip is connected to an MCU chip via HR BANK12; and the FPGA chip is connected to a logic analyzer connector via HR BANK16.

[0011] In one embodiment, the high-speed AD conversion chip is a four-channel synchronous sampling AD conversion chip, and the number of the high-speed AD conversion chips is one or more.

[0012] In one embodiment, the clock PLL chip has a multi-channel low-jitter clock signal output function. The SPI configuration port of the clock PLL chip is connected to the MCU chip and is used to output clock signals of different frequencies after being configured by the MCU chip. The clock PLL chip is also connected to the MRCC or SRCC port of the FPGA chip and is used to output clock signals in LVDS or LVCMOS format to the FPGA chip. The clock PLL chip is also connected to the high-speed AD conversion chip and is used to output clock signals in LVDS or LVPECL format to the high-speed AD conversion chip.

[0013] In one embodiment, the lower eight data lines, address lines, and control lines of the data storage DDR chip are connected to the HP BANK34 terminal of the FPGA chip, and the higher eight data lines of the data storage DDR chip are connected to the HP BANK33 terminal of the FPGA chip.

[0014] In one embodiment, the 16 GPIO pins of the MCU chip are connected to the HR BANK12 pin of the FPGA chip, for sending the data processed by the FPGA chip to the MCU chip.

[0015] Compared with the prior art, the beneficial effects of this utility model are as follows:

[0016] This invention provides an FPGA-based intermediate frequency (IF) signal processing board, comprising an FPGA chip, an MCU chip, a first crystal oscillator assembly connected to the MCU chip, a high-speed AD converter chip, a clock PLL chip, and a second crystal oscillator assembly connected to the clock PLL chip; wherein the FPGA chip, the MCU chip, the high-speed AD converter chip, and the clock PLL chip are interconnected in pairs; the high-speed AD converter chip is used to acquire analog IF signals and convert the analog IF signals into digital IF signals in LVDS format; the FPGA chip is used to acquire digital IF signals and transmit the digital IF signals to the MCU chip; the MCU chip is used to receive the working clock transmitted by the first crystal oscillator assembly and configure the clock PLL chip according to the working clock; it also receives the digital IF signals transmitted by the FPGA chip and transmits the digital IF signals to a remote host computer so that the remote host computer can process the digital IF signals; the clock PLL chip, under the configuration of the MCU chip, is used to convert the reference clock signal input by the second crystal oscillator assembly and output clock signals of different frequencies. This invention overcomes the challenges of complex inter-chip communication in FPGA+DSP+ARM architectures and the high cost and complexity of peripheral circuits for multiple processor chips. It reduces software development effort, simplifies hardware circuitry, and lowers costs. By employing a four-channel synchronous sampling AD conversion chip, multiple chips can meet the needs of more sampling channels, reducing the hardware requirements of the AD conversion circuit and further minimizing board size. This meets the requirements for high integration, small size, and compatibility, allowing for more flexible processing of various intermediate frequency signals. The use of an MCU to configure a PLL chip, with multiple flexible clock signal outputs, allows for changing the reference clock by modifying the software configuration, reducing the need for hardware modifications to switch the reference clock. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the structure of the FPGA-based intermediate frequency signal processing board according to an embodiment of the present invention;

[0018] Figure 2 This is a schematic diagram of the structure of the frequency signal processing board in the embodiment of this utility model;

[0019] Figure 3 This is a schematic diagram of the structure of the high-speed AD conversion chip according to an embodiment of the present invention;

[0020] Figure 4 This is a schematic diagram of the FPGA chip structure according to an embodiment of the present invention;

[0021] Figure 5 This is a schematic diagram of the data storage DDR chip in an embodiment of the present invention;

[0022] Figure 6 This is a schematic diagram of the structure of the clock PLL chip in an embodiment of this utility model;

[0023] Figure 7 This is a schematic diagram of the structure of the MCU chip in an embodiment of this utility model. Detailed Implementation

[0024] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments.

[0025] This utility model embodiment provides an FPGA-based intermediate frequency signal processing board, such as... Figure 1 As shown, the FPGA-based intermediate frequency signal processing board includes an FPGA chip 101, an MCU chip 102 and a first crystal oscillator assembly 103 connected to the MCU chip 102, a high-speed AD conversion chip 104, a clock PLL chip 105 and a second crystal oscillator assembly 106 connected to the clock PLL chip 105; wherein, the FPGA chip 101, the MCU chip 102, the high-speed AD conversion chip 104 and the clock PLL chip 105 are interconnected in pairs; the high-speed AD conversion chip 104 is used to acquire analog intermediate frequency signals and convert the analog intermediate frequency signals into digital intermediate frequency signals in LVDS format; ... high-speed AD conversion chip 104 and the clock PLL chip 105 are interconnected in pairs; the high-speed AD conversion chip 104 is used to acquire analog intermediate frequency signals and convert the analog intermediate frequency signals into digital intermediate frequency signals in LVDS format; the high-speed AD Chip A 101 is used to acquire a digital intermediate frequency (IF) signal and transmit the IF signal to MCU chip 102. MCU chip 102 is used to receive the operating clock transmitted by the first crystal oscillator assembly 103 and configure clock PLL chip 105 according to the operating clock. It also receives the IF signal transmitted by the FPGA chip 101 and transmits the IF signal to a remote host computer so that the remote host computer can process the IF signal. Clock PLL chip 105, under the configuration of MCU chip 102, converts the reference clock signal input by the second crystal oscillator assembly 106 and outputs it as clock signals of different frequencies.

[0026] In addition, in one embodiment, the FPGA-based intermediate frequency signal processing board further includes a power conversion chip for outputting power supply voltage to provide power to other devices on the intermediate frequency signal processing board; it also includes a signal input connector and a data output connector; the signal input connector is used to input signals, and the data output connector is used to output signals; it further includes a logic analyzer connector for performing data analysis and processing; and it also includes a program loading FLASH chip and a data storage DDR chip, the program loading FLASH chip being used to load the FPGA startup program; and the data storage DDR chip being used to store processed data.

[0027] Specifically, see Figure 2 The intermediate frequency signal processing board in this embodiment adopts an FPGA+MCU architecture, including an FPGA chip, an MCU chip and related crystal oscillators, a high-speed AD conversion chip, a clock PLL chip and related crystal oscillators, a program loading FLASH chip, a data storage DDR chip, a power conversion chip, a logic analyzer connector, a data output connector and a signal input connector.

[0028] Here, the high-speed AD conversion chip can be AD9653BCPZ-125; the data storage DDR chip can be MT41K256M16TW-107IT; the program loading FLASH chip can be W25Q64JVXGIQ; the MCU chip can be STM32F103VET6; the clock PLL chip can be AD9516-3BCPZ; the logic analyzer connector can be PZ254-2-18-Z; the power conversion chip can be TC2-1T+; and the signal input connector can be SMA-KHD.

[0029] In one embodiment, the FPGA chip is connected to the digital output of a high-speed AD conversion chip via HP BANK32; the FPGA chip is connected to a data storage DDR chip via HP BANK33 and HP BANK34; the FPGA chip is connected to a program loading FLASH chip via HR BANK0 and HR BANK14; the FPGA chip is connected to an MCU chip via HR BANK12; and the FPGA chip is connected to a logic analyzer connector via HR BANK16.

[0030] In this embodiment, the FPGA chip can be an XC7K160T-2FFG676I chip. It connects to the digital output of the high-speed AD converter chip via HP BANK32 to achieve digital intermediate frequency data acquisition. It connects to a single-chip microcontroller via HP BANK33 and HP BANK34 for storing the processed data. It connects to a program loading FLASH chip via HR BANK0 and HR BANK14 to load the FPGA boot program. It connects to an MCU chip via HR BANK12 to output the processed data to the MCU chip for serial port printing. It connects to a logic analyzer connector via HR BANK16 to output the processed data to the logic analyzer for subsequent data analysis. The PLL chip also connects to the high-speed AD converter chip and the FPGA chip via a clock output interface.

[0031] In one embodiment, the high-speed AD conversion chip is a four-channel synchronous sampling AD conversion chip, and the number of the high-speed AD conversion chips is one or more.

[0032] This embodiment uses a four-channel synchronous sampling AD conversion chip, while an eight-channel version only requires two AD conversion chips, reducing the hardware requirements of the AD conversion circuit.

[0033] In one embodiment, the clock PLL chip has a multi-channel low-jitter clock signal output function. The SPI configuration port of the clock PLL chip is connected to the MCU chip and is used to output clock signals of different frequencies after being configured by the MCU chip. The clock PLL chip is also connected to the MRCC or SRCC port of the FPGA chip and is used to output clock signals in LVDS or LVCMOS format to the FPGA chip. The clock PLL chip is also connected to the high-speed AD conversion chip and is used to output clock signals in LVDS or LVPECL format to the high-speed AD conversion chip.

[0034] The clock PLL chip in this embodiment has multiple outputs, and only one PLL is needed to provide a common reference clock for the AD+FPGA.

[0035] Specifically, see Figure 3 and Figure 4After the high-speed AD converter chip and the FPGA chip are connected, the first intermediate frequency (IF) analog signal is input from the signal input connector, converted into a differential signal after passing through the power conversion chip and appropriate matching circuitry, and connected to the VIN+A and VIN-A terminals of the high-speed AD converter chip. The other three signals are input from the signal input connector, and after passing through the same matching circuitry, are connected to the VIN+B, VIN-B, VIN+C, VIN-C, VIN+D, and VIN-D terminals respectively. After passing through the high-speed AD converter chip, the analog IF signal is converted into a digital IF signal in LVDS format, and connected to the LVDS port of the HP BANK32 on the FPGA chip. The accompanying clock signals DCO and FCO output from the high-speed AD converter chip are connected to the MRCC or SRCC ports of the HP BANK32 on the FPGA chip.

[0036] In one embodiment, the lower eight data lines, address lines, and control lines of the data storage DDR chip are connected to the HP BANK34 terminal of the FPGA chip, and the higher eight data lines of the data storage DDR chip are connected to the HP BANK33 terminal of the FPGA chip.

[0037] See Figure 5 After the data storage DDR chip is connected to the FPGA chip, the lower eight data lines, address lines and control lines of the data storage DDR chip are connected to the HP BANK34 terminal of the FPGA chip, and the higher eight data lines of the data storage DDR chip are connected to the HP BANK33 terminal of the FPGA chip, so as to realize the data storage after processing by the FPGA chip.

[0038] Additionally, see Figure 6 After the clock PLL chip is connected to the FPGA chip and the high-speed AD converter chip, the reference clock input of the clock PLL chip can be obtained from the onboard high-precision 10MHz temperature-compensated crystal oscillator or from an external signal input connector. After passing through the power conversion chip, it is converted into a differential reference clock, which is then connected to the REFIN_P and REFIN_N terminals of the clock PLL chip. The SPI configuration port of the clock PLL chip is connected to the MCU chip. After configuration by the MCU chip, it can output clock signals of different frequencies. The output clock signals in LVDS and LVCMOS formats are connected to the corresponding MRCC or SRCC ports of the FPGA chip, respectively. The output clock signals in LVDS and LVPECL formats are connected to the CLK+ and CLK- terminals of the high-speed AD converter chip, respectively.

[0039] The clock PLL chip used in this embodiment has multiple low-jitter clock signal outputs, which can provide the same clock signal for high-speed AD conversion chips and FPGA chips. The clock PLL chip can be configured by software through the MCU chip to output clock signals of different frequencies, reducing the need for hardware modifications to switch clocks.

[0040] In one embodiment, the 16 GPIO pins of the MCU chip are connected to the HR BANK12 pin of the FPGA chip, for sending the data processed by the FPGA chip to the MCU chip.

[0041] See Figure 7 After the MCU chip and FPGA chip are connected, the ordinary 10M crystal oscillator 1 provides the working clock for the MCU chip. The 16 GPIO ports of the MCU chip are connected to the HR BANK12 of the FPGA chip, which can send the data processed by the FPGA chip to the MCU chip. The MCU chip can print data through the serial port.

[0042] This invention provides an FPGA-based intermediate frequency (IF) signal processing board, comprising an FPGA chip, an MCU chip, a first crystal oscillator assembly connected to the MCU chip, a high-speed AD converter chip, a clock PLL chip, and a second crystal oscillator assembly connected to the clock PLL chip; wherein the FPGA chip, the MCU chip, the high-speed AD converter chip, and the clock PLL chip are interconnected in pairs; the high-speed AD converter chip is used to acquire analog IF signals and convert the analog IF signals into digital IF signals in LVDS format; the FPGA chip is used to acquire digital IF signals and transmit the digital IF signals to the MCU chip; the MCU chip is used to receive the working clock transmitted by the first crystal oscillator assembly and configure the clock PLL chip according to the working clock; it also receives the digital IF signals transmitted by the FPGA chip and transmits the digital IF signals to a remote host computer so that the remote host computer can process the digital IF signals; the clock PLL chip, under the configuration of the MCU chip, is used to convert the reference clock signal input by the second crystal oscillator assembly and output clock signals of different frequencies. This invention overcomes the challenges of complex inter-chip communication in FPGA+DSP+ARM architectures and the high cost and complexity of peripheral circuits for multiple processor chips. It reduces software development effort, simplifies hardware circuitry, and lowers costs. By employing a four-channel synchronous sampling AD conversion chip, multiple chips can meet the needs of more sampling channels, reducing the hardware requirements of the AD conversion circuit and further minimizing board size. This meets the requirements for high integration, small size, and compatibility, allowing for more flexible processing of various intermediate frequency signals. The use of an MCU to configure a PLL chip, with multiple flexible clock signal outputs, allows for changing the reference clock by modifying the software configuration, reducing the need for hardware modifications to switch the reference clock.

[0043] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0044] The above are merely embodiments of this application and are not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

Claims

1. An FPGA-based intermediate frequency signal processing board, characterized in that, The FPGA-based intermediate frequency signal processing board includes an FPGA chip, an MCU chip and a first crystal oscillator assembly connected to the MCU chip, a high-speed AD conversion chip, a clock PLL chip and a second crystal oscillator assembly connected to the clock PLL chip; wherein the FPGA chip, the MCU chip, the high-speed AD conversion chip and the clock PLL chip are interconnected in pairs; The high-speed AD conversion chip is used to acquire analog intermediate frequency signals and convert the analog intermediate frequency signals into digital intermediate frequency signals in LVDS format; The FPGA chip is used to acquire the digital intermediate frequency signal and transmit the digital intermediate frequency signal to the MCU chip; The MCU chip is used to receive the working clock transmitted by the first crystal oscillator component and configure the clock PLL chip according to the working clock; receive the digital intermediate frequency signal transmitted by the FPGA chip and transmit the digital intermediate frequency signal to the remote host computer so that the remote host computer can process the digital intermediate frequency signal; The clock PLL chip is used, under the configuration of the MCU chip, to convert the reference clock signal input from the second crystal oscillator component and output it as a clock signal of different frequencies.

2. The FPGA-based intermediate frequency signal processing board according to claim 1, characterized in that, The FPGA-based intermediate frequency signal processing board also includes a power conversion chip, which is used to output power voltage to provide power supply voltage for other devices on the intermediate frequency signal processing board.

3. The FPGA-based intermediate frequency signal processing board according to claim 1, characterized in that, The FPGA-based intermediate frequency signal processing board also includes a signal input connector and a data output connector; the signal input connector is used to input signals, and the data output connector is used to output signals.

4. The FPGA-based intermediate frequency signal processing board according to claim 1, characterized in that, The FPGA-based intermediate frequency signal processing board also includes a logic analyzer connector, which is used for data analysis and processing.

5. The FPGA-based intermediate frequency signal processing board according to claim 4, characterized in that, The FPGA-based intermediate frequency signal processing board also includes a program loading FLASH chip and a data storage DDR chip. The program loading FLASH chip is used to load the FPGA startup program; the data storage DDR chip is used to store the processed data.

6. The FPGA-based intermediate frequency signal processing board according to claim 5, characterized in that, The FPGA chip is connected to the digital output of the high-speed AD conversion chip via HP BANK32; the FPGA chip is connected to the data storage DDR chip via HP BANK33 and HPBANK34; the FPGA chip is connected to the program loading FLASH chip via HR BANK0 and HR BANK14; the FPGA chip is connected to the MCU chip via HR BANK12; and the FPGA chip is connected to the logic analyzer connector via HRBANK16.

7. The FPGA-based intermediate frequency signal processing board according to claim 1, characterized in that, The high-speed AD conversion chip is a four-channel synchronous sampling AD conversion chip, and the number of the high-speed AD conversion chips is one or more.

8. The FPGA-based intermediate frequency signal processing board according to claim 1, characterized in that, The clock PLL chip has a multi-channel low-jitter clock signal output function. The SPI configuration port of the clock PLL chip is connected to the MCU chip and is used to output clock signals of different frequencies after being configured by the MCU chip. The clock PLL chip is also connected to the MRCC or SRCC port of the FPGA chip and is used to output clock signals in LVDS and LVCMOS formats to the FPGA chip. The clock PLL chip is also connected to the high-speed AD conversion chip and is used to output clock signals in LVDS and LVPECL formats to the high-speed AD conversion chip.

9. The FPGA-based intermediate frequency signal processing board according to claim 6, characterized in that, The lower eight data lines, address lines, and control lines of the data storage DDR chip are connected to the HP BANK34 terminal of the FPGA chip, and the higher eight data lines of the data storage DDR chip are connected to the HP BANK33 terminal of the FPGA chip.

10. The FPGA-based intermediate frequency signal processing board according to claim 9, characterized in that, The 16 GPIO pins of the MCU chip are connected to the HR BANK12 pin of the FPGA chip, which is used to send the data processed by the FPGA chip to the MCU chip.

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