Semiconductor device

Abstract

The utility model provides a semiconductor device. The semiconductor device comprises a semiconductor tube core. The semiconductor die includes a substrate including at least one active member, an interconnect disposed over and electrically coupled to the at least one active member, and at least one first thermal control component disposed within the interconnect and thermally coupled to the at least one active member. In a vertical projection along a stacking direction of the substrate and the interconnect, the at least one active member is surrounded by the at least one first thermal control component.

Description

Technical Field

[0001] This utility model relates to a semiconductor device. Background Technology

[0002] The miniaturization of semiconductor devices and electronic components has made it possible to integrate more devices and components into a given volume, and to achieve high integration density for various semiconductor devices and / or electronic components. Utility Model Content

[0003] This invention provides a semiconductor device, comprising: a semiconductor die, including: a substrate including at least one active component; an interconnect disposed on and electrically coupled to the at least one active component; and at least one first thermal control component disposed inside the interconnect and thermally coupled to the at least one active component, wherein the at least one active component is surrounded by the at least one first thermal control component in a vertical projection along the stacking direction of the substrate and the interconnect.

[0004] This invention provides a semiconductor device, comprising: a redistributed circuit structure; a first die disposed on and electrically coupled to the redistributed circuit structure, and comprising: a first substrate including at least one first active component; a first interconnect disposed on and electrically coupled to the at least one first active component; and at least one first thermal control component disposed inside the first interconnect and thermally coupled to the at least one first active component, wherein the at least one first active component is surrounded by the at least one first thermal control component in a vertical projection; a second die disposed on and electrically coupled to the redistributed circuit structure, and comprising: a second substrate including at least one second active component; a second interconnect disposed on and electrically coupled to the at least one second active component; and at least one via disposed on and electrically coupled to the redistributed circuit structure, and electrically coupling the first die and the second die. Attached Figure Description

[0005] The various aspects of the embodiments of this utility model are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, according to industry standard practice, the various features are not drawn to scale. In fact, for clarity of explanation, the dimensions of the various features may be arbitrarily increased or decreased.

[0006] Figures 1 to 17 Schematic cross-sectional views are shown of various stages in a method of manufacturing a semiconductor device according to some embodiments of this disclosure.

[0007] Figures 18 to 36Semiconductor devices according to alternative embodiments of the present disclosure are shown respectively.

[0008] Figure 37 and Figure 38 A schematic plan view showing the positioning architecture of hot spots and thermal control components included in a semiconductor device according to various embodiments of the present disclosure.

[0009] Figures 39 to 42 Schematic cross-sectional views are shown of various stages in a method of manufacturing a semiconductor device according to some embodiments of this disclosure.

[0010] Figures 43 to 46 Semiconductor devices according to alternative embodiments of the present disclosure are shown respectively.

[0011] Figure 47 A schematic cross-sectional view illustrating the application of a semiconductor device according to some embodiments of this disclosure.

[0012] [Icon Symbol Explanation]

[0013] 110, 20, 30: Semiconductor dies;

[0014] 40A, 40B, 40C, 40D, 40E, 1000, 2000: Stacking units;

[0015] 50: Carrier;

[0016] 52, 206, 5101, 5102, 5103, 5104, 510 N-3 510 N-2 510 N-1 510 N 1600, 1700, 6001, 6002, 6003, 15101, 15102: Dielectric layers;

[0017] 54: Supporting substrate;

[0018] 56: Release layer;

[0019] 110, 130, 150: Lining layer;

[0020] 120, 140, 160: Through holes;

[0021] 200A, 200B: Substrate;

[0022] 202: Semiconductor substrate;

[0023] 204: Isolation structure;

[0024] 208: Contact plug;

[0025] 300: Transistor;

[0026] 310: Gate structure;

[0027] 312: Gate;

[0028] 314: Gate dielectric layer;

[0029] 316: Gate spacer wall;

[0030] 320: Source / Drain region;

[0031] 330: Well area;

[0032] 400m: Thermal energy storage material;

[0033] 412, 414, 422, 424, 430, 440, 450, 470, 480: Thermal control components;

[0034] 500: Internal connection;

[0035] 5201, 5202, 5203, 5204, 520 N-3 520 N-2 520 N-1 520 N 15201, 15202: Seed layers;

[0036] 5301, 5302, 5303, 5304, 530 N-3 53 0N-2 530 N-1 530 N 15301, 15302: Conductive layers;

[0037] 6201, 6202, 6203: Bonding layers;

[0038] 710, 720: Thermally conductive adhesive;

[0039] 800: Cover;

[0040] 900: Radiator;

[0041] 1001, 1002, 1003: Perforation;

[0042] 1500: Re-layout circuit structure;

[0043] 1800: Conductive terminal;

[0044] 1800c: Conductive component;

[0045] 1800u: UBM pattern;

[0046] 1900, 1910, 1920, 1930: Insulating encapsulation;

[0047] 10000A, 10000B, 10000C, 10000D, 10000E, 10000F, 10000G, 10000H, 10000I, 10000J, 10000K, 10000L, 10000M, 10000N, 10000O, 10000P, 10000Q, 10000R, 10000S, 10000T, 20000, 30000, 40000, 50000, 60000: Semiconductor devices;

[0048] C1: First component;

[0049] C2: Second component;

[0050] CT: Terminal;

[0051] DL1, DL1', DL2, DL2', DL3, DL4, DL N-3 DL N-2 DL N-1 DL N Dielectric structure;

[0052] IF1, IF2, IF3, IF4, IF5, IF6: Joining interfaces;

[0053] L1: Construction layer, first construction layer;

[0054] L2: Construction layer, second construction layer;

[0055] L3: Construction layer, third construction layer;

[0056] L4: Construction layer, fourth construction layer;

[0057] L N-1 : Construction layer, N-1th construction layer;

[0058] L N-2 : Construction layer, N-2nd construction layer;

[0059] L N-3 : Construction layer, N-3rd construction layer;

[0060] L N : Construction layer, Nth construction layer;

[0061] L1', L2': Construction layers;

[0062] ML1, ML1', ML2, ML2', ML3, ML4, ML N-3 ML N-2 MLN-1 ML N Metallization layer;

[0063] OP1: Opening;

[0064] S1, S50, S52, S110, S120, S130, S140, S150, S160, S202b, S206, S412, S5101, S510 N S5201, S520 N S5301, S530 N S800, S1001: Surface;

[0065] S202: Patterned bottom surface;

[0066] S500, S1002, S1003, S1900, S6001, S6002, S6003: The top surface shown;

[0067] SC: Component assembly;

[0068] T1: First level;

[0069] T2: Second level;

[0070] T3: Third level;

[0071] UF: Bottom filler adhesive;

[0072] W1, W2, W3: Circuit chips;

[0073] X, Y, Z: Direction. Detailed Implementation

[0074] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided object. Specific examples of components, values, operations, materials, arrangements, or similar elements are described below to simplify this disclosure. These are merely examples and are not intended to be limiting. Other components, values, operations, materials, arrangements, or similar elements are contemplated. For example, the following description of a first feature formed on or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, thereby preventing direct contact between the first and second features. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. Such repetition is for the purpose of brevity and clarity and is not intended to indicate a relationship between the various embodiments and / or configurations discussed.

[0075] Furthermore, for ease of explanation, spatially relative terms such as "beneath," "below," "lower," "above," and "upper" may be used herein to describe the relationship between one component or feature shown in the figures and another component or feature. These spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly.

[0076] In addition, for ease of explanation, terms such as "first," "second," "third," and "fourth" may be used in this document to describe similar or different components or features illustrated in the figure, and may be used interchangeably depending on the order of their existence or the context of the description.

[0077] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Furthermore, terms (e.g., those defined in common dictionaries) shall be interpreted as having the same meaning as they have in the context of the relevant art and this disclosure, and shall not be interpreted as having an idealized or overly formal meaning unless expressly defined herein.

[0078] This disclosure may also include other features and processes. For example, test structures may be included to aid in the verification testing of three-dimensional (3D) packages or three-dimensional integrated circuit (3DIC) devices. These test structures may, for example, include test pads formed in redistribution layers or on a substrate to enable testing of 3D packages or 3DIC devices, use of probes and / or probe cards, and similar operations. Verification testing can be performed on intermediate and final structures. Furthermore, the structures and methods disclosed herein can be combined with testing methods including intermediate verification of known good dies to improve yield and reduce costs.

[0079] It should be understood that the following embodiments of this disclosure provide feasible concepts that can be implemented in a wide variety of specific contexts. The specific embodiments described herein relate to semiconductor devices (or semiconductor packages or semiconductor structures) with a multi-level stacked structure, each level including at least one semiconductor die or chip, and are not intended to limit the scope of this disclosure. Due to the use of thermal control components with thermal energy storage materials in the interconnects of one or more levels of the stacked structure, the thermal management of the semiconductor device is well controlled. That is, heat dissipation of hot spots in the semiconductor device is greatly improved, resulting in better reliability of the semiconductor device. In the embodiments of this disclosure, the thermal control components with thermal energy storage materials can be disposed within the interconnects of one or more levels in the stacked structure, wherein the thermal control components with thermal energy storage materials can be in the form of an array (with multiple pillars or cylinders) surrounding the hot spot, in the form of a block or plate with openings surrounding the hot spot, or in the form of a continuous plate overlapping the hot spot. In the embodiments of this disclosure, the thermal control components with thermal energy storage materials can be formed to penetrate one or more dielectric layers in the interconnects of one or more levels in the stacked structure.

[0080] In some embodiments, the manufacturing method is part of a wafer-level packaging process. It should be understood that additional processes may be provided before, during, and after the illustrated methods, and only a few other processes may be briefly described herein. In this disclosure, it should be understood that the illustrations of components in all figures are schematic and not drawn to scale. In all the various views and illustrative embodiments of this disclosure, components similar to or substantially identical to those previously illustrated will use the same reference numerals, and certain details or descriptions of the same components (e.g., materials, forming processes, positioning configurations, electrical connections, etc.) will not be repeated. For clarity of illustration, the figures are illustrated using orthogonal axes (X, Y, and Z) of a Cartesian coordinate system, according to which the views are oriented; however, this disclosure is not specifically limited thereto.

[0081] Figures 1 to 17 These are schematic cross-sectional views of various stages of a method for manufacturing a semiconductor device (e.g., 10000A) according to some embodiments of this disclosure. Figures 18 to 36 Schematic cross-sectional views of semiconductor devices (e.g., 10000B, 10000C, 10000D, 10000E, 10000F, 10000G, 10000H, 10000I, 10000J, 10000K, 10000L, 10000M, 10000N, 10000O, 10000P, 10000Q, 10000R, 10000S, or 10000T) according to alternative embodiments of the present disclosure are shown respectively. Figure 37and Figure 38 Schematic plan views illustrating the positioning architecture of a hot spot (e.g., hot spot 300 or the like) of a semiconductor device according to various embodiments of the present disclosure and a thermal control assembly (e.g., thermal control assembly 412, 414, 422, 424, 430, 440, 470, or 480) including thermal energy storage material. The embodiments are intended to provide further illustration but are not intended to limit the scope of the present disclosure.

[0082] refer to Figure 1 In some embodiments, an initial structure is provided. For example, the initial structure includes a substrate 200A comprising multiple components of various types (also referred to as semiconductor components) formed in a semiconductor substrate 202 and stacked structures disposed on the semiconductor substrate 202, such as... Figure 1 As shown. The plurality of components may include active components, passive components, or combinations thereof. The plurality of components may include integrated circuit (IC) devices. The plurality of components may include transistors, capacitors, resistors, diodes, photodiodes, fuse devices, jumpers, sensors, or other similar devices. The functions of the plurality of components may include memory, processors, sensors, amplifiers, power distribution, input / output circuit systems, etc. The plurality of components may be referred to individually as the semiconductor components disclosed herein.

[0083] In some embodiments, the semiconductor substrate 202 includes a bulk semiconductor substrate, a crystalline silicon substrate, a doped semiconductor substrate (e.g., a p-type semiconductor substrate or an n-type semiconductor substrate), a semiconductor-on-insulator (SOI) substrate, or the like. In some embodiments, the semiconductor substrate 202 includes one or more doped regions or various types of doped regions, depending on requirements and / or product design requirements / layout. In some embodiments, the doped regions are doped with p-type dopants and / or n-type dopants. For example, the p-type dopant is boron or BF2, and the n-type dopant is phosphorus or arsenic. The doped regions can be configured as n-type metal-oxide-semiconductor (NMOS) transistors or p-type metal-oxide-semiconductor (PMOS) transistors. The semiconductor substrate 202 can be a wafer, such as a silicon wafer. Generally, an SOI substrate is a layer of semiconductor material formed over an insulating layer. The insulating layer is, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The semiconductor substrate 202 may also use other substrates, such as multilayer substrates or gradient substrates. In some alternative embodiments, the semiconductor substrate 202 comprises a semiconductor substrate made of other suitable elemental semiconductors, such as diamond or germanium; suitable compound semiconductors, such as gallium arsenide, silicon carbide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide; suitable alloy semiconductors such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and GaInAsP; or combinations thereof. For example, the semiconductor substrate 202 is a bulk silicon substrate.

[0084] like Figure 1As shown, the plurality of components (e.g., one or more transistors 300) may be formed in the semiconductor substrate 202. In some embodiments, a plurality of isolation structures 204 are formed in the semiconductor substrate 202 to separate the transistors 300. In some embodiments, the isolation structure 204 is a trench isolation structure. In other embodiments, the isolation structure 204 includes a local oxidation of silicon (LOCOS) structure. In some embodiments, the insulating material of the isolation structure 204 includes silicon oxide, silicon nitride, silicon oxynitride, spin-coated dielectric material, or a low-k dielectric material. For example, a low-k dielectric material typically has a dielectric constant below 3.9. In one embodiment, the insulating material can be formed via chemical vapor deposition (CVD) (such as high-density plasma CVD (HDP-CVD) and sub-atmospheric CVD (SACVD)) or by spin-on coating. In some embodiments, components (e.g., transistor 300) and isolation structures 204 are formed in the substrate 200A during a front-end-of-line (FEOL) process. In one embodiment, transistor 300 is formed following a complementary MOS (CMOS) process. The number and arrangement of components formed in the semiconductor substrate 202 should not be limited to the embodiments or figures disclosed herein. That is, the number of components may be more than two. It should be understood that, depending on the product design, the number and arrangement of components may have different materials or configurations.

[0085] Transistor 300 may be a PMOS transistor independently. For example, each of transistors 300 includes a gate structure 310 and a plurality of source / drain regions 320 located on two opposite sides of the gate structure 310, wherein the gate structure 310 is formed on an n-well region 330, and the source / drain regions 320 are formed within the n-well region 330. In one embodiment, the gate structure 310 includes a gate electrode 312, a gate dielectric layer 314, and a gate spacer 316. The gate dielectric layer 314 may extend between the gate electrode 312 and the semiconductor substrate 202, and may or may not further cover the sidewalls of the gate electrode 312. The gate spacer 316 may laterally surround the gate electrode 312 and the gate dielectric layer 314. In one embodiment, the source / drain region 320 includes a plurality of p-type doped regions formed in the n-well region 330 by ion implantation. In an alternative embodiment, the source / drain region 320 includes a plurality of epitaxial structures formed in and protruding from the surface of the semiconductor substrate 202 by epitaxial growth.

[0086] Alternatively, transistor 300 includes a gate structure 310 and a plurality of source / drain regions 320 located on two opposite sides of the gate structure 310, wherein the gate structure 310 is formed on a p-well region 330 and the source / drain regions 320 are formed within the p-well region 330. In one embodiment, the gate structure 310 includes a gate electrode 312, a gate dielectric layer 314, and a gate spacer 316. The gate dielectric layer 314 may extend between the gate electrode 312 and the semiconductor substrate 202 and may or may not further cover the sidewalls of the gate electrode 312. The gate spacer 316 may laterally surround the gate electrode 312 and the gate dielectric layer 314. In one embodiment, the source / drain regions 320 include a plurality of n-type doped regions formed in the p-well region 330 by ion implantation. In an alternative embodiment, the source / drain regions 320 include a plurality of epitaxial structures formed in and protruding from the surface of the semiconductor substrate 202 by epitaxial growth.

[0087] In a non-limiting example, all transistors 300 may have the same type. For example, all transistors 300 may be NMOS transistors. Or, for another example, all transistors 300 may be PMOS transistors. This disclosure is not limited thereto. In yet another non-limiting example, one or some of the transistors 300 may have a different type than the rest of the transistors 300. For example, one or some of the transistors 300 may be NMOS transistors, while the rest may be PMOS transistors, or vice versa.

[0088] In some embodiments, some or all of the transistors 300 may be logic components or part of logic components, and may or may not interact with each other. Furthermore, at least some of the transistors 300 may be memory components or part of memory components, and may or may not interact with each other. The memory components may be, for example, static random-access memory (SRAM), wherein the transistors 300 used as logic components and the transistors 300 used as memory components are electrically coupled and electrically communicated.

[0089] For illustrative purposes, transistor 300 is shown in the form of a planar transistor; however, this disclosure is not limited thereto. Transistor 300 may independently be a field-effect transistor (FET), such as a planar FET, tunnel field-effect transistor (TFET), or fin-type FET (FINFET); a gate-all-around (GAA) transistor; a nanosheet transistor; a nanowire transistor; the like; or a combination thereof, depending on requirements and / or product design requirements / layout. According to some embodiments, transistor 300 may be a planar FET and / or TFET device or part of a planar FET and / or TFET device, which may include a silicon body standing on a substrate and a gate standing on the silicon body (i.e., the channel region) to provide control from the top side of the channel region. According to some embodiments, transistor 300 may be a FinFET device or part of a FinFET device, which may include a thin (vertical) fin having a silicon body above a substrate and a gate wrapped around the fin (i.e., the channel region) to provide control from three sides of the channel region. According to some embodiments, transistor 300 may be a nanostructure transistor device (e.g., a GAA transistor device, a nanosheet transistor, or a nanowire transistor) or part of a nanostructure transistor device, which may include a gate structure surrounding (e.g., bonding) the periphery of one or more nanostructures (i.e., the channel region) to improve channel current control.

[0090] like Figure 1 As shown, for example, substrate 200A further includes a dielectric layer 206 stacked above semiconductor substrate 202 and a plurality of contact plugs 208 penetrating dielectric layer 206 and electrically connected to transistor 300. In some embodiments, dielectric layer 206 and contact plugs 208 are also formed in substrate 200A during FEOL process. Dielectric layer 206 may laterally surround gate structure 310 and cover source / drain region 320 to provide protection for components formed on / in semiconductor substrate 202. Some of contact plugs 208 may penetrate dielectric layer 206 to establish electrical connection with source / drain region 320, while other portions of contact plugs 208 may partially penetrate dielectric layer 206 to establish electrical connection with gate of gate structure 310 (e.g., gate 312) to provide multiple terminals for electrical connection with components (e.g., interconnects or interconnect structures) or external components formed laterally.

[0091] The dielectric layer 206 may be referred to as an interlayer dielectric (ILD) layer, and the contact plug 208 may be referred to as a metal contact or a metallized contact. For example, the contact plug 208 electrically connected to the source / drain region 320 is referred to as a source / drain contact, and the contact plug 208 electrically connected to the gate 312 is referred to as a gate contact. In some embodiments, the contact plug 208 may comprise copper (Cu), copper alloys, nickel (Ni), aluminum (Al), manganese (Mn), magnesium (Mg), silver (Ag), gold (Au), tungsten (W), combinations thereof, or similar materials. The contact plug 208 may be formed by processes such as plating, such as electroplating or electroless plating; CVD, such as plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), and physical vapor deposition (PVD); combinations thereof; or similar processes. Throughout this document, the term "copper" is used to include substantially pure elemental copper, copper containing unavoidable impurities, and copper alloys containing small amounts of elements such as tantalum, indium, tin, zinc, manganese, chromium, titanium, germanium, strontium, platinum, magnesium, aluminum, or zirconium.

[0092] In some embodiments, dielectric layer 206 comprises silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, silicon carbonitride, spin-on glass (SOG), phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), fluorinated silica glass (FSG), carbon-doped silicon oxide (e.g., SiCOH), polyimide, and / or combinations thereof. In alternative embodiments, dielectric layer 206 comprises a low-dielectric-constant dielectric material. For example, a low-dielectric-constant dielectric material generally has a dielectric constant below 3.9. Examples of low-dielectric-constant dielectric materials may include... (BLACK (Applied Materials of Santa Clara, California), Xerogel, Aerogel, Amorphous fluorinated carbon, Parylene, Benzocyclobutene (BCB), Flare (Dow Chemical, Midland, Michigan), hydrogen silsesquioxane (HSQ), or fluorinated silicon oxide (SiOF) and / or combinations thereof. It should be understood that dielectric layer 206 may comprise one or more dielectric materials. For example, dielectric layer 206 may comprise a monolayer or multilayer structure. In some embodiments, dielectric layer 206 is formed to a suitable thickness by CVD (e.g., flowable CVD (FCVD), HDP-CVD, and SACVD), spin coating, sputtering, or other suitable methods.

[0093] Seed layers (not shown) may be formed between dielectric layer 206 and contact plugs 208 as needed. That is, for example, the seed layer covers the bottom surface and sidewalls of each of the contact plugs 208. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising multiple sublayers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer on top of the titanium layer. The seed layer is formed using, for example, PVD or a similar process. In one embodiment, the seed layer may be omitted.

[0094] Additionally, an additional barrier layer or adhesive layer (not shown) may be formed between the contact plug 208 and the dielectric layer 206, as needed. This additional barrier layer or adhesive layer prevents the seed layer and / or the contact plug 208 from diffusing into the underlying and / or surrounding layers. The additional barrier layer or adhesive layer may comprise Ti, TiN, Ta, TaN, combinations thereof, multilayers thereof, or similar materials, and may be formed using CVD, ALD, PVD, combinations thereof, or similar processes. In an alternative embodiment that includes a seed layer, the additional barrier layer or adhesive layer is sandwiched between the dielectric layer 206 and the seed layer, and the seed layer is sandwiched between the contact plug 208 and the additional barrier layer or adhesive layer. In one embodiment, the additional barrier layer or adhesive layer may be omitted.

[0095] like Figure 1As shown, for example, substrate 200A further includes a plurality of through vias 1001. In some embodiments, through vias 1001 are formed laterally adjacent to transistor 300 and perpendicularly through dielectric layer 206, extending further into the semiconductor substrate 202. In some embodiments, each through via 1001 includes a liner 110 and a conductive via 120, wherein the bottom and sidewalls of the conductive via 120 are lined by the liner 110. That is, the conductive via 120 of through via 1001 is separated from the semiconductor substrate 202 and dielectric layer 206 through the respective liner 110. In some embodiments, through via 1001 may taper gradually from dielectric layer 206 to semiconductor substrate 202. Alternatively, through via 1001 may have substantially vertical sidewalls. In a cross-sectional view along direction Z, the shape of through via 1001 may depend on requirements and / or product design requirements / layouts, and is not limited to this disclosure. Additionally, in the top view (planar view) on the XY plane, the through-hole 1001 is circular. However, depending on requirements and / or product design requirements / layout, the shape of the through-hole 1001 can be elliptical, rectangular, polygonal, or a combination thereof; this disclosure is not limited thereto. In some embodiments, the through-hole 1001 is not exposed in an accessible manner by the surface S202b of the semiconductor substrate 202, but can be exposed in an accessible manner by the surface S206 of the dielectric layer 206. This disclosure does not limit the number of through-holes 1001, which can be selected and specified according to requirements and / or product design requirements / layout.

[0096] The via 120 may be formed of a conductive material, such as copper, tungsten, aluminum, silver, combinations thereof, or the like. The pad 110 may be formed of a barrier material, such as TiN, Ta, TaN, Ti, or the like. In alternative embodiments, dielectric pads (not shown) (e.g., silicon nitride, oxides, polymers, combinations thereof) may also be selectively formed between the pad 110 and the semiconductor substrate 202, and between the pad 110 and the dielectric layer 206. Alternatively, the pad 110 may be omitted.

[0097] The pad 110, via 120, and optional dielectric pad can be formed, but not limited to, by forming a plurality of recesses in the dielectric layer 206 and the substrate 202; depositing optional dielectric, barrier, and conductive materials into the plurality of recesses; and removing excess material above the plane containing the indicated top opening of the plurality of recesses. For example, the plurality of recesses are lined with optional dielectric pads to laterally separate the semiconductor substrate 202 and the dielectric layer 206 from the pad 110 on the sidewall of the via 120 and the indicated bottom surface. In some embodiments, the via 1001 is formed using a via-first method. In such embodiments, the via 1001 is formed before the interconnect (e.g., 500) is formed. Alternatively, the via 1001 can be formed using a via-last method, which can be used after the interconnect (e.g., 500) is formed.

[0098] In some embodiments, the semiconductor substrate 202 is in wafer or panel form when considered as a top view or plan view (e.g., XY plane) along direction Z. The semiconductor substrate 202 may be in the form of a wafer with a size of about 4 inches or greater. The semiconductor substrate 202 may be in the form of a wafer with a size of about 6 inches or greater. The semiconductor substrate 202 may be in the form of a wafer with a size of about 8 inches or greater. Alternatively, the semiconductor substrate 202 may be in the form of a wafer with a size of about 12 inches or greater. Transistors 300 formed in the substrate 200A may be arranged in an array along directions X and Y. Directions X, Y, and Z may be different from each other. For example, direction X is perpendicular to direction Y, and directions X and Y are independently perpendicular to direction Z, such as... Figure 1 As shown. In this disclosure, direction Z can be referred to as the stacking direction, and the XY plane defined by directions X and Y can be referred to as a plan view or top view.

[0099] continue Figure 1 In some embodiments, a stacked structure is formed over the substrate 200A. For example, the stacked structure includes interconnects 500 (in... Figure 6 The interconnect 500 includes multiple stacked build-up layers (e.g., L1, L2, L3, L4…, L…). N-3 L N-2 L N-1 and L N In this disclosure, for illustrative purposes, interconnect 500 includes a first portion having four building layers (e.g., L1, L2, L3, and L4) and a portion having N-4 building layers (e.g., ..., L...).N-3 L N-2 L N-1 With L N The second part is stacked on top of and electrically connected to the first part. However, this disclosure is not limited thereto. Alternatively, the first part may include one, two, three, four or more building layers, and the second part may include one, two, three, four, ..., or more than N building layers (where N is greater than 1). The number of building layers included in the first part of interconnect 500 and the number of building layers included in the second part of interconnect 500 are selected and designed according to requirements and / or product design requirements / layout. In some embodiments, the first part is referred to as a local interconnect formed in a middle-end-of-line (MEOL) process, and the second part is referred to as a global interconnect formed in a back-end-of-line (BEOL) process.

[0100] In some embodiments, Figure 1 At least one building layer formed in the initial structure includes a building layer (e.g., building layer L1), such as Figure 1 As shown, this is for illustrative purposes; however, in Figure 1 The number of at least one building layer formed in the initial structure can be two, three, or more, depending on requirements and / or design requirements / layout. As shown in the figure, in some embodiments, building layer L1 is disposed (e.g., in physical contact) above and electrically coupled to via 1001 and component (e.g., transistor 300, through contact plug 208) to provide routing functionality to them. Building layer L1 may be referred to as the first building layer L1 of interconnect 500.

[0101] The formation of the building layer L1 via the stacked structure may include, but is not limited to, forming a blanket of dielectric material (not shown) over a dielectric layer 206 on a semiconductor substrate 202 to cover the via 1001 and components (e.g., transistor 300); patterning the dielectric material blanket to form a dielectric layer 5101, wherein a plurality of first openings (not shown) penetrate the dielectric layer 5101; forming a seed layer 5201 in the plurality of first openings; and forming a conductive material on the seed layer 5201 and in the plurality of first openings to form a conductive layer 5301 over the seed layer 5201, thereby forming a metallization layer ML1 (which may be referred to as a redistribution layer) in the plurality of first openings formed in the dielectric layer 5101, thereby forming the building layer L1. For example, as Figure 1 As shown, the metallization layer ML1 of the building layer L1 includes a seed layer 5201 and a conductive layer 5301 standing on top of and electrically connected to it, and the metallization layer ML1 is laterally covered by the dielectric structure DL1 of the building layer L1, wherein the dielectric structure DL1 includes a dielectric layer 5101. Figure 1 As shown, for example, conductive layer 5301 is electrically connected to transistor 300 via seed layer 5201 and conductive plug 208, and is electrically connected to via aperture 1001 via seed layer 5201.

[0102] In some embodiments, the dielectric layer 5101 may be made of polyimide (PI), polybenzoxazole (PBO), benzocyclobutene (BCB), aluminum nitride (AlN), boron nitride (BN), diamond-like carbon, Al₂O₃, BeO, nitrides (e.g., silicon nitride), oxides (e.g., silicon oxide), phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), combinations thereof, or the like, and may be patterned using photolithography and / or etching processes. Etching processes may include dry etching, wet etching, or combinations thereof. After the etching process, a cleaning step may be selectively performed, for example, to clean and remove residues generated from the etching process. In some embodiments, the dielectric material blanket layer is formed using appropriate manufacturing techniques such as spin coating, CVD (e.g., PECVD), etc. For example, the dielectric layer 5101 may be made of silicon oxide. Each of the plurality of first openings formed in dielectric layer 5101 may include a trench hole and a via hole located below the trench hole and spatially communicating with it. In some embodiments, each of the first openings includes a dual damascene structure. The formation of the first openings is not limited to this disclosure. The first opening (with a dual damascene structure) may be formed by any suitable forming process, such as a via-first method or a trench-first method.

[0103] The lateral dimension of a trench hole may be larger than the lateral dimension of a through hole. In some embodiments, the sidewall of each through hole is an inclined sidewall. In an alternative embodiment, the sidewall of each through hole is a vertical sidewall. In some embodiments, the sidewall of each trench hole is an inclined sidewall. In an alternative embodiment, the sidewall of each trench hole is a vertical sidewall. The sidewall of a through hole and the sidewall of a corresponding trench hole may be collectively referred to as the sidewall of a first opening formed in dielectric layer 5101. For illustrative purposes, the number of first openings is not limited by this disclosure and may be specified and selected based on requirements and / or layout design requirements / layout. The portion of the metallization layer ML1 formed in the trench hole may be referred to as a horizontally extending conductive line, conductive trace, or conductive metal line (e.g., extending in the X and / or Y directions), and the portion of the metallization layer ML1 formed in the through hole may be referred to as a vertically extending (e.g., extending in the Z direction) via.

[0104] In other embodiments, the dielectric blanket layer comprises a two-layer structure, wherein the first dielectric layer comprises a silicon carbide (SiC) layer, a silicon nitride (Si3N4) layer, an aluminum oxide layer, or the like, and the second dielectric layer (stacked above the first dielectric layer) comprises a silicon oxide layer (e.g., a silicon-rich oxide (SRO) layer), a silicon nitride layer, a silicon oxynitride layer, a spin-coated dielectric layer, or a low dielectric constant dielectric layer, etc. It should be noted that the low dielectric constant dielectric layer is generally made of a dielectric material having a dielectric constant less than 3.9. In some alternative embodiments, the first and second dielectric layers have different etching selectivity. In this case, the first dielectric layer may be referred to as an etching stop layer (ESL) to prevent damage to the underlying components (e.g., contact plug 208 and dielectric layer 206) due to over-etching, while the second dielectric layer may be referred to as an inter-metallic layer (IML). In this alternative embodiment, the first and second dielectric layers are patterned using a combination of photolithography and etching processes. The etching processes may include dry etching, wet etching, or a combination thereof. A cleaning step may be selectively performed after the etching process, for example, to clean and remove residues generated from the etching process. However, this disclosure is not limited to this, and the etching process may be performed by any other suitable method. The plurality of first openings formed in the first and second dielectric layers each include trench vias and through-holes located below and spatially connected to the trench vias. For example, trench vias are formed in the second dielectric layer and extend from the indicated top surface of the second dielectric layer to a location inside the second dielectric layer. For example, through-holes are formed in both the second and first dielectric layers and extend from the location inside the second dielectric layer to the indicated bottom surface of the first dielectric layer. The location may be at approximately 1 / 2 to approximately 1 / 3 of the thickness of the second dielectric layer; however, this disclosure is not limited to this.

[0105] In some embodiments, a seed layer 5201 and a conductive layer 5301 are sequentially formed in a first opening by, but not limited to, the following operations: conformally forming a blanket layer of metal or metal alloy material on the dielectric structure DL1 and extending the blanket layer into the first opening to line the sidewalls of the first opening; filling the first opening with a conductive material; and removing excess blanket layer of metal or metal alloy material and excess conductive material from the indicated top surface of the dielectric layer 5101, thereby creating a metallization layer ML1 including the seed layer 5201 and the conductive layer 5301. Removal can be performed by planarization processes such as mechanical grinding, chemical mechanical polishing (CMP), and / or etching. A cleaning step can be optionally performed after the planarization process, for example, to clean and remove residues generated from the planarization process. However, this disclosure is not limited to this, and the planarization process can be performed by any other suitable method.

[0106] In some embodiments, the seed layer 5201 is referred to as a metal layer, which may be a single layer or a composite layer comprising multiple sublayers formed of different materials. In some embodiments, the seed layer 5201 comprises titanium, copper, molybdenum, tungsten, titanium nitride, titanium tungstenide, combinations thereof, or similar materials. For example, the seed layer 5201 may comprise a titanium layer and a copper layer situated on top of the titanium layer. The seed layer 5201 may be formed using processes such as sputtering, PVD, or similar methods. The seed layer 5201 may have a thickness of about 1 nanometer (nm) to about 50 nanometers (measured in the Z direction), but other suitable thicknesses may also be used alternatively.

[0107] In some embodiments, the conductive material comprises a suitable conductive material, such as a metal and / or a metal alloy. For example, the conductive material may be Al, aluminum alloy, Cu, copper alloy or a combination thereof (e.g., AlCu), similar materials or combinations thereof. In some embodiments, the conductive material is formed by a plating process or any other suitable method, wherein the plating process may include electroplating or electroless plating or similar plating processes. In alternative embodiments, the conductive material may be formed by deposition. This disclosure is not limited thereto. In this case, the illustrated top surface of the metallization layer ML1 is substantially flush with the illustrated top surface of the dielectric structure DL1. That is, the illustrated top surface of the metallization layer ML1 is substantially coplanar with the illustrated top surface of the dielectric structure DL1.

[0108] refer to Figure 2 In some embodiments, dielectric layer 5101 is patterned to form a plurality of openings OP1 penetrating dielectric layer 5101, wherein the openings OP1 expose dielectric layer 206 in an accessible manner. In some embodiments, the openings OP1 have substantially vertical sidewalls, such as Figure 2As shown. Alternatively, the opening OP1 can taper gradually from the surface S5101 of the dielectric layer 5101 to the substrate 200A. In the cross-sectional view along the Z direction, the shape of the opening OP1 may depend on requirements and / or product design requirements / layout, and is not intended to limit this disclosure. In the top (planar) view on the XY plane, the shape of the opening OP1 is rectangular; please refer to [reference needed]. Figure 37 However, depending on the requirements and / or product design specifications / layout, the shape of the opening OP1 can be elliptical, circular, polygonal, or a combination thereof; this disclosure is not limited thereto. For illustrative purposes, Figure 2 Only twelve openings OP1 are shown; however, this disclosure is not limited to this. The number of openings OP1 may be more or less than twelve, which can be selected and / or specified according to requirements and / or product design requirements / layout.

[0109] Patterning processes can be performed using photolithography and / or etching processes. Etching processes can include dry etching, wet etching, or a combination thereof. After the etching process, a cleaning step can be optionally performed, for example, to clean and remove residues generated from the etching process.

[0110] refer to Figure 3 In some embodiments, a thermal energy storage material 400m is deposited above the first building layer L1, and the thermal energy storage material 400m further extends into the opening OP1. For example, the opening OP1 is completely filled with the thermal energy storage material 400m. Figure 3As shown, the thermal energy storage material 400m can (e.g., physically) contact the dielectric layer 206 exposed through the opening OP1. The thermal energy storage material 400m can be formed by deposition (e.g., PVD or CVD). In a non-limiting example, the thermal energy storage material 400m includes a thermal (energy) storage solid-solid phase change material (PCM) configured to readily undergo a solid-solid martensitic transformation from one crystalline structure to another different crystalline structure during temperature changes. In some embodiments, the solid-solid martensitic transformation from one crystalline structure to another different crystalline structure is reversible. In this configuration, the thermal energy storage material 400m can store thermal energy (e.g., heat generated by hot spots such as transistor 300) through mechanical deformation (e.g., from a first crystalline structure to a different second crystalline structure), and then release the thermal energy (e.g., heat) at a slower rate through mechanical deformation (e.g., from a second crystalline structure to a different first crystalline structure). Due to this mechanism, heat spikes in the semiconductor device disclosed herein can be mitigated. The material of the thermal energy storage material 400m may include germanium (Ge)-antimony (Sb)-tellurium (Te) (GST), vanadium dioxide (VO2), titanium oxide (III), metal alloys, any other suitable metal alloys (e.g., nickel-titanium systems, including NiTi, NiTiHf, NiCuTi, NiCuTiHf, or NiTiV; or similar materials), etc. For example, the thermal energy storage material 400m includes shape memory alloys (SMA) that readily undergo solid-to-solid martensitic transformation. This disclosure is not limited thereto. In some embodiments, the thermal conductivity of the thermal energy storage material 400m is greater than that of the dielectric layer 5101.

[0111] refer to Figure 4In some embodiments, the thermal energy storage material 400m is planarized to form a plurality of thermal control elements 412 in the opening OP1. For example, the thermal energy storage material 400m is planarized to remove excess thermal energy storage material 400m above the surface S5101 of the dielectric layer 5101 to form thermal control elements 412 in the opening OP1 and laterally positioned next to the metallization layer ML1 of the interconnect 500. In some embodiments, the thermal control elements 412 are laterally covered (e.g., in physical contact) by the dielectric structure DL1 of the interconnect 500. The thermal control elements 412 may be embedded in the first building layer L1 of the interconnect 500. In some embodiments, the surface S412 of the thermal control elements 412 is substantially flush with the surface S5101 of the dielectric layer 5101, the surface S5201 of the seed layer 5201, and the surface S5301 of the conductive layer 5301 in the interconnect 500. In other words, the surface S412 of the thermal control component 412 is substantially coplanar with and flush with the surfaces S5101 of the dielectric layer 5101, the seed layer 5201, and the conductive layer 5301 in the interconnect 500. Figure 4 As shown, the thermal control component 412 can completely penetrate the dielectric layer 5101. For example, the thermal control component 412 is in a multi-pillar or multi-cylinder form. In a non-limiting example, the multi-pillar or multi-cylinder thermal control component 412 extends along the Z direction, wherein the thermal control components 412 are separated from each other in the X and Y directions (e.g., in the XY plane), as... Figure 4 As shown. In another non-limiting example, the thermal control assembly 412 in the form of multiple columns or multiple cylinders extends along the direction X or Y (e.g., in the XY plane), wherein the thermal control assemblies 412 are separated from each other in the direction Z, not shown.

[0112] In some embodiments, the thermal control component 412 is referred to as a thermal capacitor, thermal storage capacitor, thermal control member, thermal control module, thermal management component, thermal management member, or thermal management module. The thermal control component 412 is arranged in an array. For example, the thermal control component 412 is arranged in a matrix along directions X and Y, such as a U×V array or a U×V array (U, V>0, U may be equal to or not equal to V), wherein the matrix has openings corresponding to the locations of hot spots (e.g., transistor 300) inside the semiconductor device disclosed herein. Due to the thermal control component 412, heat generated from hot spots (e.g., transistor 300) inside the semiconductor device disclosed herein can be directed to and stored within the thermal control component 412, which mitigates thermal spikes in the hot spots (e.g., transistor 300) inside the semiconductor device disclosed herein, thereby improving the reliability of the semiconductor device disclosed herein. In some embodiments, the thermal control component 412 is electrically isolated from the interconnect 500 and the transistor 300, and the thermal control component 412 is thermally coupled to the interconnect 500 and the transistor 300.

[0113] Planarization processes may include polishing, chemical mechanical polishing, etching, or combinations thereof. During the planarization process, the dielectric layer 5101, seed layer 5201, and / or conductive layer 5301 may also be planarized. After planarization, a cleaning step may be selectively performed, for example, to clean and remove residues generated from the planarization process. However, this disclosure is not limited to this, and the planarization process can be performed by any other suitable method.

[0114] refer to Figure 5 and Figure 6 In some embodiments, the remaining building layers (e.g., L2, L3, L4..., L5) are formed above the first building layer L1 and the thermal control assembly 412, including local and global interconnects of the interconnect 500. N-3 L N-2 L N-1 and L N ).like Figure 5As shown, in the local interconnect of interconnect 500, a building layer L2 (including a dielectric layer 5102, a seed layer 5202, and a conductive layer 5302) is disposed (e.g., physically contacted) above and electrically connected to building layer L1, and thus electrically coupled to vias 1001 and components (e.g., transistors 300) formed in semiconductor substrate 202 through contact plug 208 and building layer L1 to provide routing functionality thereto; a building layer L3 (including a dielectric layer 5103, a seed layer 5203, and a conductive layer 5303) is disposed (e.g., physically contacted) above and electrically connected to building layer L2. Electrically connected, and thus electrically coupled to vias 1001 and components (e.g., transistor 300) formed in semiconductor substrate 202 via contact plugs 208 and building layers L1 to L2, to provide routing functionality thereto; and building layer L4 (including a dielectric layer 5104, a seed layer 5204 and a conductive layer 5304) is disposed (e.g., physically contacted) above and electrically connected to building layer L3, and thus electrically coupled to vias 1001 and components (e.g., transistor 300) formed in semiconductor substrate 202 via contact plugs 208 and building layers L1 to L3, to provide routing functionality thereto.

[0115] In this configuration, the building layer L2 is referred to as the second building layer L2, comprising a metallization layer ML2 and a dielectric structure DL2 laterally covering the metallization layer ML2. The metallization layer ML2 (which may be referred to as the redistribution layer) includes a seed layer 5202 and a conductive layer 5302, and the dielectric structure DL2 includes a dielectric layer 5102. The building layer L3 may be referred to as the third building layer L3, comprising a metallization layer ML3 and a dielectric structure DL3 laterally covering the metallization layer ML3. The metallization layer ML3 (which may be referred to as the redistribution layer) includes a seed layer 5203 and a conductive layer 5303, and the dielectric structure DL3 includes a dielectric layer 5103. The building layer L4 can be referred to as the fourth building layer L4, which includes a metallization layer ML4 and a dielectric structure DL4 that laterally covers the metallization layer ML4. The metallization layer ML4 (which can be referred to as the redistribution layer) includes a seed layer 5204 and a conductive layer 5304, and the dielectric structure DL4 includes a dielectric layer 5104.

[0116] like Figure 6 As shown, in the global interconnect with interconnect 500, layer L is constructed. N-3 (including dielectric layer 510) N-3 Seed layer 520 N-3 Conductive layer 530 N-3The contact plug is disposed on and electrically coupled to the building layer L4 (e.g., through an additional building layer formed therebetween, if present), and thus electrically coupled to the via 1001 and components (e.g., transistor 300) formed in the semiconductor substrate 202 through the contact plug 208, the building layers L1 to L4 and the additional building layer formed therebetween (if present) to provide routing functionality thereto; the building layer L N-2 (including dielectric layer 510) N-2 Seed layer 520 N-2 Conductive layer 530 N-2 ) is set in (e.g., physical contact) building layer L N-3 It is electrically connected above and thus through contact plug 208, building layers L1 to L N-3 Electrically coupled to vias 1001 and components (e.g., transistors 300) formed in the semiconductor substrate 202, and to additional building layers (if any) formed therebetween, to provide routing functionality; building layer L N-1 (including dielectric layer 510) N-1、 Seed layer 520 N-1 Conductive layer 530 N-1 ) is set in (e.g., physical contact) building layer L N-2 It is electrically connected above and thus through contact plug 208, building layers L1 to L N-2 Electrically coupled to vias 1001 and components (e.g., transistors 300) formed in the semiconductor substrate 202, and to additional building layers (if any) formed therebetween, to provide routing functionality thereto; and building layer L N (including dielectric layer 510) N Seed layer 520 N Conductive layer 530 N ) is set in (e.g., physical contact) building layer L N-1 It is electrically connected above and thus through contact plug 208, building layers L1 to L N-1 Electrically coupled to the vias 1001 and components (e.g., transistors 300) formed in the semiconductor substrate 202, with any additional building layers (if present) formed therein, to provide routing functionality thereto.

[0117] In this situation, the building layer L N-3 It can be referred to as the (N-3)th building layer L N-3 Including the metallization layer ML N-3 and laterally covered metallized layer ML N-3 dielectric structure DL N-3 The metallization layer ML N-3 (This can be referred to as the redistribution layer) includes a seed layer 520. N-3and conductive layer 530 N-3 Dielectric structure DL N-3 Including dielectric layer 510 N-3 Construction layer L N-2 It can be referred to as the (N-2)th building layer L N-2 Including the metallization layer ML N-2 and laterally covered metallized layer ML N-2 dielectric structure DL N-2 The metallization layer ML N-2 (This can be referred to as the redistribution layer) includes a seed layer 520. N-2 and conductive layer 530 N-2 Dielectric structure DL N-2 Including dielectric layer 510 N-2 Construction layer L N-1 It can be referred to as the (N-1)th building layer L N-1 Including the metallization layer ML N-1 and laterally covered metallized layer ML N-1 dielectric structure DL N-1 The metallization layer ML N-1 (This can be referred to as the redistribution layer) includes a seed layer 520. N-1 and conductive layer 530 N-1 Dielectric structure DL N-1 Including dielectric layer 510 N-1 Construction layer L N It can be referred to as the Nth building layer L N Including the metallization layer ML N and laterally covered metallized layer ML N dielectric structure DL N The metallization layer ML N (This can be referred to as the redistribution layer) includes a seed layer 520. N and conductive layer 530 N Dielectric structure DL N Including dielectric layer 510 N .

[0118] At this point, the interconnect 500 has been manufactured. In some embodiments, the interconnect 500 is disposed on the substrate 200A and electrically coupled to components formed in the substrate 200A. That is, the interconnect 500 provides routing functionality to the components formed in the substrate 200A. In some embodiments, at least some of the components formed in the substrate 200A are electrically connected to each other through the interconnect 500. Figure 6 As shown, interconnect 500 can cover the substrate 200A. The metallization layers ML1 to ML2 of interconnect 500 are... NThe routing structure can be collectively referred to as the interconnect 500. In some embodiments, the metallization layers ML1 to ML2 of the interconnect 500 are... N The line dimensions (e.g., thickness and width) gradually increase along the direction from substrate 200A to interconnect 500.

[0119] The interconnect 500 can be referred to as an interconnect structure or simply an interconnect. Building layers L2 to L... N The formation and materials Figure 1 The formation process and materials of the building layer L1 described herein are similar or substantially the same, therefore, for simplicity, they will not be repeated here. In one embodiment, dielectric layers 5101 to 510... N The materials are the same for each other. Alternatively, dielectric layers 5101 to 510... N The materials may be partially or entirely different from each other. The top surface S500 of the interconnect 500 (e.g., including dielectric layer 510) is shown. N Surface S510 N Seed layer 520 N Surface S520 N With conductive layer 530 N Surface S530 N ) can be flush and can have a high degree of coplanarity, such as Figure 6 As shown.

[0120] refer to Figure 7 In some embodiments, a dielectric layer 6001 is formed over the interconnect 500. For example, the dielectric layer 6001 is disposed (e.g., in physical contact) on the top surface S500 of the interconnect 500 (e.g., including surface S510). N Surface S520 N and surface S530 N Above the substrate 200A, interconnects 500 are disposed between dielectric layer 6001 and substrate 200A. Dielectric layer 6001 may be referred to as a bonding layer or a bonding dielectric layer. Dielectric layer 6001 may be a single layer or comprise multiple stacked sub-dielectric layers. Dielectric layer 6001 may be transparent (but not limited to) through... Figure 6 The dielectric layer 6001 is formed by conformally forming a blanket layer of material for forming the dielectric layer 6001 on the structure shown. In a non-limiting example, the material of the dielectric layer 6001 may include inorganic materials such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, or silicon carbonitride; other suitable dielectric layers; or combinations thereof. The dielectric layer 6001 can be formed using suitable manufacturing techniques such as spin coating, CVD, ALD, PVD, etc. The illustrated top surface S6001 in the dielectric layer 6001 can be flat and can have a high degree of coplanarity, such as... Figure 7As shown. At this point, the circuit wafer W1 has been manufactured, which includes a substrate 200A (including a semiconductor substrate 202 on which multiple transistors 300 are formed, multiple isolation structures 204, a dielectric layer 206, multiple contact plugs 208, and multiple through holes 1001), interconnects 500 disposed above and electrically coupled to the substrate 200A, multiple thermal control components 412 embedded in the interconnects 500, and a dielectric layer 6001 disposed above the interconnects 500.

[0121] refer to Figure 8 In some embodiments, a circuit chip W2 is provided. For example, the circuit chip W2 includes a substrate 200B (including a semiconductor substrate 202 on which a plurality of transistors 300 are formed, a plurality of isolation structures 204, a dielectric layer 206, and a plurality of contact plugs 208), interconnects 500 disposed above and electrically coupled to the substrate 200B, a plurality of thermal control components 412 embedded in the interconnects 500, and a dielectric layer 6002 disposed above the interconnects 500. The details, composition, and materials of the substrate 200B (including the semiconductor substrate 202, isolation structures 204, dielectric layer 206, and contact plugs 208), thermal control components 412, interconnects 500, and dielectric layer 6002 in the circuit chip W2 are similar to or substantially the same as those in other circuits. Figures 1 to 7 The circuit chip W1 described includes a substrate 200A (including a semiconductor substrate 202, an isolation structure 204, a dielectric layer 206, and contact plugs 208), a thermal control component 412, interconnects 500, and a dielectric layer 6001; therefore, for the sake of brevity, these will not be repeated here. The top surface S6002 of the dielectric layer 6002 can be flat and can have a high degree of coplanarity, such as... Figure 8 As shown. Dielectric layer 6002 can be referred to as a bonding layer or bonding dielectric layer.

[0122] refer to Figure 9In some embodiments, circuit chip W2 is placed above circuit chip W1 and bonded to circuit chip W1 via wafer-on-wafer (WoW) bonding. In some embodiments, circuit chip W2 is placed above circuit chip W1 via a pick-and-place process for bonding. For example, the semiconductor substrate 202 of circuit chip W2 is placed (e.g., in physical contact) above the illustrated top surface S6001 of dielectric layer 6001 of circuit chip W1, and the semiconductor substrate 202 of circuit chip W2 is bonded to the illustrated top surface S6001 of dielectric layer 6001 of circuit chip W1 via a bonding process, said bonding process including dielectric-to-dielectric bonding (e.g., oxide-to-silicon bonding or nitride-to-silicon bonding). In this embodiment, a bonding interface IF1 (e.g., an oxide-to-silicon bonding interface or a nitride-to-silicon bonding interface) exists between circuit wafer W2 and circuit wafer W1, and this bonding interface IF1 is considered the bonding interface between circuit wafer W2 and circuit wafer W1. After this bonding, circuit wafer W1 can be referred to as... Figure 9 The first tier T1 of the stacked structure is shown, and the circuit chip W2 can be referred to as the second tier T2 of the stacked structure.

[0123] refer to Figure 10 In some embodiments, a circuit chip W3 is provided. For example, the circuit chip W3 includes a substrate 200B (including a semiconductor substrate 202 on which a plurality of transistors 300 are formed, a plurality of isolation structures 204, a dielectric layer 206, and a plurality of contact plugs 208), an interconnect 500 disposed above and electrically coupled to the substrate 200B, and a plurality of thermal control components 412 embedded in the interconnect 500. The details, composition, and materials of the substrate 200B (including the semiconductor substrate 202, isolation structures 204, dielectric layer 206, and contact plugs 208), the thermal control components 412, and the interconnect 500 in the circuit chip W3 are similar to or substantially the same as those in other circuits. Figures 1 to 7 The circuit chip W1 described includes a substrate 200A (including a semiconductor substrate 202, an isolation structure 204, a dielectric layer 206, and a contact plug 208), a thermal control component 412, and interconnects 500; therefore, for the sake of brevity, these will not be repeated here.

[0124] refer to Figure 11In some embodiments, circuit chip W3 is placed above circuit chip W2 and bonded to circuit chip W2 via WoW bonding. In some embodiments, circuit chip W3 is placed above circuit chip W2 via a pick-and-place process for bonding. For example, the semiconductor substrate 202 of circuit chip W3 is placed (e.g., in physical contact) above the top surface S6002 of dielectric layer 6002 of circuit chip W2, and the semiconductor substrate 202 of circuit chip W3 is bonded to the top surface S6002 of dielectric layer 6002 of circuit chip W2 via a bonding process including dielectric-to-dielectric bonding (e.g., oxide-to-silicon bonding or nitride-to-silicon bonding). In such embodiments, there is a bonding interface IF2 between circuit chip W3 and circuit chip W2, which is a dielectric-to-dielectric bonding interface (e.g., oxide-to-silicon bonding interface or nitride-to-silicon bonding interface) and is considered to be the bonding interface between circuit chip W3 and circuit chip W2. After bonding, the circuit chip W3 can be referred to as such Figure 11 The third tier T3 of the stacked structure shown.

[0125] refer to Figure 12 In some embodiments, in Figure 11 The stacked structure shown forms at least one through-hole 1002 (including a pad 130 and a through-hole 140) and at least one through-hole 1003 (including a pad 150 and a through-hole 160). For illustrative purposes, as... Figure 12 As shown, at least one perforation 1002 may include one perforation 1002 and at least one perforation 1003 may include one perforation 1003; however, this disclosure is not limited thereto. The number of each of the perforations 1002 and 1003 may be more than one, and they may be selected and / or specified based on requirements and / or product design requirements / layout. The details, formation, and materials of the perforations 1002 and 1003 are related to... Figure 1 The details (e.g., architecture, such as shape), formation, and materials of the perforated 1001 described herein are similar or substantially the same, and therefore will not be repeated here. For example, as Figure 12 As shown, pad 130 exposes the bottom of the through-hole 140 of perforation 1002 in an accessible manner, and pad 150 exposes the bottom of the through-hole 160 of perforation 1003 in an accessible manner. Alternatively, the bottom and sidewalls of the through-hole 140 of perforation 1002 are physically covered by pad 130, and the bottom and sidewalls of the through-hole 160 of perforation 1003 are physically covered by pad 150. In some embodiments, such as Figure 12As shown, the top surface S1002 of the perforation 1002 (e.g., the surface S130 including the pad 130 and the surface S140 of the via 140) and the top surface S1003 of the perforation 1003 (e.g., the surface S150 including the pad 150 and the surface S160 of the via 160) are substantially flush with the top surface S500 of the interconnect 500 (e.g., the surface S510) N S520 N and S530 N In other words, the top surface S1002 of the perforation 1002 (e.g., the surface S130 including the gasket 130 and the surface S140 of the via 140) and the top surface S1003 of the perforation 1003 (e.g., the surface S150 including the gasket 150 and the surface S160 of the via 160) are substantially coplanar with the top surface S500 of the interconnect 500 (e.g., the surface S510) N S520 N and S530 N ).

[0126] In a non-limiting example, through-hole 1002 passes through the second level T2 and the third level T3 of the stacked structure and extends further into the first level T1, thus electrically connecting the first level T1, the second level T2, and the third level T3 to each other through (e.g., physically) contacting through-hole 1002 with metallic features (e.g., the metallization layer of interconnect 500) in the first level T1, the second level T2, and the third level T3. In such a case, through-hole 1003 passes through the third level T3 of the stacked structure and extends further into the second level T2, thereby electrically connecting the second level T2 and the third level T3 to each other through (e.g., physically) contacting through-hole 1003 with metallic features (e.g., the metallization layer of interconnect 500) in the second level T2 and the third level T3.

[0127] In another non-limiting example, through-hole 1002 passes through the second level T2 and the third level T3 of the stacked structure and extends further into the first level T1 to electrically connect the first level T1 and the third level T3 through (e.g., physically) contact between through-hole 1002 and metal features (e.g., the metallization layer of interconnect 500) in the first level T1 and the third level T3. In this alternative case, through-hole 1003 passes through the third level T3 of the stacked structure and extends further into the second level T2, thereby electrically connecting the second level T2 and the third level T3 to each other through (e.g., physically) contact between through-hole 1003 and metal features (e.g., the metallization layer of interconnect 500) in the second level T2 and the third level T3, and electrically connecting the first level T1 and the second level T2 to each other through (e.g., physically) contact between through-hole 1002 and metal features (e.g., the metallization layer of interconnect 500) in the third level T3.

[0128] In embodiments including multiple through-holes 1002, the through-holes 1002 pass through the second level T2 and the third level T3 of the stacked structure and further extend to the first level T1, wherein one or more of the through-holes 1002 electrically connect the first level T1, the second level T2, and the third level T3 to each other through (e.g., physically) contacting metallic features (e.g., metallization layers in interconnects 500) in the first level T1, the second level T2, and the third level T3, and the remaining portions of the through-holes 1002 physically contact the through-holes. The remainder of 1002 electrically connects the first level T1 and the third level T3 to each other via metallic features (e.g., metallization layers in interconnect 500) in the first level T1 and the third level T3, and wherein one or more of the vias 1003 penetrate the third level T3 of the stacked structure and extend further into the second level T2, so as to electrically connect the second level T2 and the third level T3 to each other via (e.g., physically) contacting one or more of the vias 1003 with metallic features (e.g., metallization layers in interconnect 500) in the second level T2 and the third level T3. In some embodiments where the electrical connection between the first level T1, the second level T2, and the third level T3 is properly established by the vias 1002, the vias 1003 may be omitted.

[0129] refer to Figure 12 and Figure 13 In some embodiments, after forming vias 1002 and 1003, a dielectric layer 6003 is conformally formed over the top surface S1002 of via 1002, the top surface S1003 of via 1003, and the top surface S500 of interconnect 500. The details, formation, and material of the dielectric layer 6003 are as follows... Figure 7The dielectric layer 6001 of the circuit chip W1 described herein is similar to or substantially the same; therefore, for the sake of brevity, it will not be repeated here. The top surface S6003 of the dielectric layer 6003 shown may be flat and may have a high degree of coplanarity, such as Figure 13 As shown. Dielectric layer 6003 may be referred to as a bonding layer or bonding dielectric layer. In some embodiments, dielectric layer 6003 may be considered part of circuit wafer W3.

[0130] continue Figure 13 For example, a carrier 50 is provided above the dielectric layer 6003, and the carrier 50 is bonded to the dielectric layer 6003 via a WoW bonding process. Details of the carrier 50 can be found in... Figure 1 The details of the semiconductor substrate 202 described herein are similar or substantially the same, and therefore will not be repeated here for the sake of brevity. For example, the carrier 50 is a silicon substrate without source components. In some embodiments, the carrier 50 is bonded to the dielectric layer 6003 via a bonding process including dielectric-to-dielectric bonding (e.g., oxide-to-silicon bonding or nitride-to-silicon bonding). In such an embodiment, there is a bonding interface IF3 between the circuit wafer W3 and the carrier 50, which is considered to be the bonding interface between the circuit wafer W3 and the carrier 50. After bonding, the carrier 50 can be referred to as a support substrate including a stacked structure of layers T1 to T3. In addition, since the carrier 50 is a silicon substrate, the carrier 50 can also be a heat dissipation component of the semiconductor device 10000A (in Figure 17 middle).

[0131] refer to Figure 13 and Figure 14 In some embodiments, a planarization process is performed on the semiconductor substrate 202 of the circuit wafer W1 (in the first layer T1), thereby thinning the semiconductor substrate 202 of the circuit wafer W1 and exposing the through-hole 1001 in an accessible manner. Figure 14As shown, portions of the semiconductor substrate 202 and the pads 110 can be removed from the stacked circuit wafer W1, thereby exposing the vias 120 from the circuit wafer W1. In some cases, during the removal of portions of the semiconductor substrate 202 and the pads 110 from the circuit wafer W1, portions of the vias 120 of the circuit wafer W1 may also be slightly removed. Then, for example, a patterning process is performed on the semiconductor substrate 202 of the circuit wafer W1, wherein portions of the semiconductor substrate 202 are further removed to form a semiconductor substrate 202 having a patterned bottom surface S202, such that portions of each via 1001 (including portions of each pad 110 and each via 120) protrude from the patterned bottom surface S202 of the semiconductor substrate 202. The patterning process may include etching processes (e.g., wet etching or dry etching) or similar processes. This disclosure is not limited thereto.

[0132] like Figure 14 As shown, the pad 110 may cover the entire sidewall of the via 120 and expose the bottom of the via 120; however, this disclosure is not limited thereto. In one embodiment, the pad 110 may only cover the sidewall of the via 120 embedded in a semiconductor substrate 202 having a patterned bottom surface S202. For example, the portion of the pad 110 that is disposed on the sidewall of the via 120 and protrudes from the patterned bottom surface S202 of the semiconductor substrate 202 after the planarization process is removed during the patterning process. In one embodiment, the pad 110 may cover both the sidewall and the bottom of the via 120. That is, the portion of the pad 110 that is disposed on the sidewall of the via 120 and protrudes from the patterned bottom surface S202 of the semiconductor substrate 202 after the planarization process is retained during the patterning process. The planarization process may include a polishing process, a chemical mechanical polishing process, an etching process, a combination thereof, etc. The etching process may include dry etching, wet etching, or a combination thereof.

[0133] In some embodiments, a dielectric material (not shown) is formed on a patterned bottom surface S202 of the semiconductor substrate 202 of the circuit wafer W1. In some embodiments, the dielectric material is formed directly and conformally over the semiconductor substrate 202 and the via 1001 of the circuit wafer W1, wherein the semiconductor substrate 202 and the via 1001 of the circuit wafer W1 are covered by and in physical contact with the dielectric material. In some embodiments, the dielectric material may be formed as a dielectric material blanket layer. In some embodiments, the dielectric material may be a polymer layer made of PI, PBO, BCB, or any other suitable polymer-based dielectric material. In some embodiments, the dielectric material may be an Ajinomoto Buildup Film (ABF), a Solder Resist Film (SRF), or a similar film. In some embodiments, the dielectric material may be formed by suitable manufacturing techniques, such as spin coating, stacking, deposition, etc. Subsequently, another planarization process is performed on the dielectric material to form a dielectric layer 52 that laterally covers the through-holes 1001 protruding from the semiconductor substrate 202 of the circuit wafer W1, wherein the dielectric layer 52 exposes the surfaces S1001 of the through-holes 1001 (including the surfaces S110 of the pads 110 and S120 of the vias 120) in an accessible manner. In some embodiments, in the other planarization process, a portion of the dielectric material laterally located next to the through-holes 1001 on the patterned bottom surface S202 protruding from the semiconductor substrate 202 is retained, while the remaining dielectric material is removed; the remaining dielectric material constitutes the dielectric layer 52.

[0134] In some embodiments, the other planarization process may include a polishing process, a chemical mechanical polishing process, an etching process, or a combination thereof. The etching process may include dry etching, wet etching, or a combination thereof. For example, such as... Figure 14 As shown, the surface S52 of the dielectric layer 52 is substantially flush with the surface S1001 of the via 1001. That is, the surface S52 of the dielectric layer 52 is substantially coplanar with the surface S1001 of the via 1001. In some embodiments, a cleaning step may be optionally performed after each planarization process, for example to clean and remove residues generated from the planarization process. However, this disclosure is not limited thereto, and each planarization process may be performed by any other suitable method.

[0135] refer to Figure 15 In some embodiments, the redistribution circuit structure 1500 is formed on the circuit chip W1, wherein the redistribution circuit structure 1500 is electrically coupled to the via 1001. Figure 15As shown, for illustrative purposes, the redistribution structure 1500 includes only two building layers (e.g., L1' and L2'), however, this disclosure is not limited thereto. The number of building layers included in the redistribution structure 1500 may be one, two, or more, depending on requirements and / or product design requirements / layout. Building layer L1' may include a dielectric layer 15101, a seed layer 15201, and a conductive layer 15301, and building layer L2' may include a dielectric layer 15102, a seed layer 15202, and a conductive layer 15302, as shown below. Figure 15 As shown. The details, formation, and materials of the dielectric layer 15101, seed layer 15201, and conductive layer 15301 included in the building layer L1', and the details, formation, and materials of the dielectric layer 15102, seed layer 15202, and conductive layer 15302 included in the building layer L2', are similar to or substantially the same as those shown. Figure 1 The details, formation, and materials of the dielectric layer 5101, seed layer 5201, and conductive layer 5301 included in the building layer L1 will not be repeated here.

[0136] The dielectric layer 15101 may be referred to as the dielectric structure DL1' of the building layer L1', and the seed layer 15201 and the conductive layer 15301 may be referred to as the metallization layer ML1' (or redistribution layer) of the building layer L1'. On the other hand, the dielectric layer 15102 may be referred to as the dielectric structure DL2' of the building layer L2', and the seed layer 15202 and the conductive layer 15302 may be referred to as the metallization layer ML2' (or redistribution layer) of the building layer L2'. The metallization layers ML1' and ML2' may be collectively referred to as the routing structure of the redistribution circuit structure 1500. In some embodiments, the line dimensions (e.g., thickness and width) of the metallization layers ML1' and ML2' of the redistribution circuit structure 1500 gradually increase along the direction from the circuit wafer W1 to the metallization layer ML2'.

[0137] For example, a building layer L1' is disposed above the surface S52 of the dielectric layer 52 and electrically connected to the via 1001 through direct contact, thereby electrically coupling to components (e.g., transistor 300) included in the circuit wafers W1, W2, and W3 (e.g., further through interconnects 500 and / or through vias 1002, 1003). In such a case, a building layer L2' is disposed above the building layer L1' and electrically connected to the via 1001 through the building layer L1', thereby electrically coupling to components (e.g., transistor 300) included in the circuit wafers W1, W2, and W3 (e.g., further through interconnects 500 and / or through vias 1002, 1003). That is, the redistribution structure 1500 provides routing functionality to components (e.g., transistor 300) included in the circuit wafers W1, W2, and W3.

[0138] continue Figure 15In some embodiments, after the redistribution structure 1500 is formed, a dielectric layer 1600, a dielectric layer 1700, and a plurality of conductive terminals 1800 are sequentially formed on the redistribution structure 1500, wherein the conductive terminals 1800 are disposed on the redistribution structure 1500 and electrically coupled to the redistribution structure 1500. Figure 15 As shown, a dielectric layer 1600 may be formed over the redistribution structure 1500, and a plurality of second openings (not shown) are formed in the dielectric layer 1600, which penetrate the dielectric layer 1600 and tactically expose a portion of the redistribution structure 1500 (e.g., metallization layer ML2'). The dielectric layer 1600 may be referred to as a passivation layer. In this case, a dielectric layer 1700 is formed over the dielectric layer 1600, and a plurality of third openings (not shown) are formed in the dielectric layer 1700, which penetrate the dielectric layer 1700 and tactically expose a portion of the redistribution structure 1500 (e.g., metallization layer ML2') tactically exposed by the dielectric layer 1600. The dielectric layer 1700 may be referred to as a post-passivation layer. Dielectric layer 1600 may be or include a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a dielectric layer formed of other suitable dielectric materials, and may be formed by deposition, such as CVD (e.g., PECVD). This disclosure is not limited thereto. Dielectric layer 1700 may be or include a PI layer, a PBO layer, or a dielectric layer formed of other suitable polymers, and may be formed by spin coating or deposition.

[0139] In alternative embodiments, dielectric layer 1600 may be omitted. Additionally or alternatively, dielectric layer 1700 may be omitted. This disclosure is not limited thereto.

[0140] In some embodiments, each conductive terminal 1800 may include an under-ball metallurgy (UBM) pattern 1800u and a conductive element 1800c, the conductive element 1800c being disposed on and electrically coupled to the UBM pattern 1800u. For example... Figure 15As shown, for example, the conductive component 1800c of the conductive terminal 1800 is electrically coupled to the redistribution structure 1500 (e.g., the metallization layer ML2' exposed in an accessible manner by dielectric layers 1600 and 1700) through the UBM pattern 1800u of the conductive terminal 1800. In this case, the conductive terminal 1800 is electrically coupled to the redistribution structure 1500 through dielectric layers 1600 and 1700.

[0141] Each of the UBM patterns 1800u is made, for example, of a metal layer comprising a single layer or of a metallized layer comprising a composite layer having multiple sublayers formed of different materials. The materials of the UBM patterns 1800u may include copper, nickel, titanium, molybdenum, tungsten, titanium nitride, tungsten-titanium, alloys thereof, or similar materials, and may be formed, for example, by an electroplating process. For example, each of the UBM patterns 1800u comprises a titanium layer and a copper layer above the titanium layer. In some embodiments, the UBM patterns 1800u may be formed, for example, using sputtering, PVD, or similar processes. This disclosure does not limit the shape or number of the UBM patterns 1800u. Each of the conductive components 1800c includes, for example, microbumps, metal pillars, controlled collapse chip connection (C4) bumps (e.g., which may have a size of about 80 μm, but are not limited to), ball grid array (BGA) bumps (e.g., which may have a size of about 400 μm, but are not limited to), bumps formed by electroless nickel-immersion gold technique (ENIG), bumps formed by electroless nickel-electroless palladium-immersion gold technique (ENEPIG), etc. This disclosure is not limited thereto. This disclosure does not limit the shape and number of conductive terminals 1800.

[0142] refer to Figure 16 In some embodiments, after forming the conductive terminal 1800, a dicing (monomerization) process is performed to cut through the dielectric layer 1600, dielectric layer 1700, stacked structure (including circuit wafers W1 to W3), and carrier 50 to form multiple stacking units 1000. Figure 16For the sake of illustration and simplicity, only one stacking unit 1000 is shown in the image. Each stack unit 1000 may include a carrier 50, a semiconductor die 30 (e.g., a product of cutting through a circuit wafer W3) disposed on and thermally coupled to the carrier 50 and in a third level T3, a semiconductor die 20 (e.g., a product of cutting through a circuit wafer W2) disposed on and electrically coupled to the semiconductor die 30 and in a second level T2, a semiconductor die 10 (e.g., a product of cutting through a circuit wafer W1) disposed on and electrically coupled to the semiconductor die 20 and in a first level T1, a redistribution circuit structure 1500 disposed on and electrically coupled to the semiconductor die 10 in the first level T1, a dielectric layer 1600 disposed on the redistribution circuit structure 1500, a dielectric layer 1700 disposed on the dielectric layer 1600, and a plurality of conductive terminals 1800 disposed on the redistribution circuit structure 1500 and electrically coupled to the redistribution circuit structure 1500 through the dielectric layers 1600 and 1700. For example, in the stacked cell 1000, the sidewalls of the carrier 50, the semiconductor die 30, the semiconductor die 20, the semiconductor die 10, the redistribution structure 1500, the dielectric layer 1600, and the dielectric layer 1700 are aligned with each other. That is, the sidewalls of the carrier 50, the semiconductor die 30, the semiconductor die 20, the semiconductor die 10, the redistribution structure 1500, the dielectric layer 1600, and the dielectric layer 1700 together constitute the sidewalls of the stacked cell 1000, such as... Figure 16 As shown. In one embodiment, the dicing (monodilation) process is a wafer dicing process that includes mechanical blade sawing or laser cutting. This disclosure is not limited thereto.

[0143] In some embodiments, some of the conductive terminals 1800 are electrically coupled to the semiconductor die 10 through the redistribution wiring structure 1500 and the via 1001; some of the conductive terminals 1800 are electrically coupled to the semiconductor die 20 through the redistribution wiring structure 1500, the via 1001, the semiconductor die 10, and the via 1002; and some of the conductive terminals 1800 are electrically coupled to the semiconductor die 30 through the redistribution wiring structure 1500, the via 1001, the semiconductor die 10, and the via 1002. This disclosure is not limited thereto. In an alternative embodiment, some of the conductive terminals 1800 are electrically coupled to the semiconductor die 10 through the redistribution wiring structure 1500 and the via 1001, some of the conductive terminals 1800 are electrically coupled to the semiconductor die 30 through the redistribution wiring structure 1500, the via 1001, the semiconductor die 10, and the via 1002, and some of the conductive terminals 1800 are electrically coupled to the semiconductor die 20 through the redistribution wiring structure 1500, the via 1001, the semiconductor die 10, the via 1002, the semiconductor die 30, and the via 1003.

[0144] refer to Figure 17 In some embodiments, a thermal dissipating module is provided and coupled to a stacking cell 1000 to form a semiconductor device 10000A. In a non-limiting example, the thermal dissipating module includes a lid 800 and a heat sink 900. For example, such as Figure 17 As shown, the cover 800 is disposed (e.g., adhered to) the carrier 50 (e.g., at its surface S50) via a thermally conductive adhesive 710 between the cover 800 and the carrier 50, and the heat sink 900 is disposed (e.g., adhered to) the cover 800 (e.g., at its surface S800) via a thermally conductive adhesive 720 between the heat sink 900 and the cover 800. That is, the cover 800 is thermally coupled to the stacking unit 1000 via the thermally conductive adhesive 710, and the heat sink 900 is thermally coupled to the stacking unit 1000 via the thermally conductive adhesive 720, the cover 800, and the thermally conductive adhesive 710. Due to the heat dissipation modules (e.g., 800 and / or 900), the thermal dissipation of the semiconductor device 10000A is further improved. However, this disclosure is not limited thereto. In another non-limiting example, the heat dissipation module may consist of only a cover 800 or a heat sink 900. In embodiments where the cover 800 is omitted, the heat sink 900 is thermally coupled to the stack unit 1000 via a thermally conductive adhesive 720 or 710. Alternatively, if the heat dissipation of the semiconductor device 10000A can be well controlled by a thermal control component (e.g., 412) embedded therein, the heat dissipation module can be completely omitted from the semiconductor device 10000A.

[0145] For example, thermally conductive adhesives 710 and 720 are independently made of thermally conductive materials or any material capable of heat transfer. Thermally conductive adhesives 710 and 720 can independently be any suitable adhesive, glue, epoxy resin, underfill, die attach film (DAF), thermal interface material (TIM), or the like. For example, cover 800 and radiator 900 are independently made of materials with a high thermal conductivity of about 200 W / (m·K) to about 400 W / (m·K) or higher. Cover 800 and radiator 900 can be independently formed of materials with high thermal conductivity, such as steel, stainless steel, copper, the like, combinations thereof, or any material with good thermal conductivity for heat dissipation mechanisms. In some embodiments, cover 800 and radiator 900 are independently coated with another metal. Cover 800 and radiator 900 can be independently a single continuous material, or can comprise multiple components having the same or different materials. Provided to Figure 17 The heat dissipation module shown is for illustrative purposes only. The cover 800 can be of any suitable form (e.g., plate form), and the heat sink 900 can be of any suitable form (e.g., fin form, etc.). This disclosure is not limited thereto.

[0146] In some embodiments, the semiconductor device 10000A includes a thermal control component (e.g., 412) in the local interconnects (formed in MEOL) of the interconnects (e.g., 500) included in each semiconductor die (e.g., 10, 20, and / or 30), such as Figure 17 As shown. However, this disclosure is not limited thereto. In alternative embodiments, one or more thermal control components (e.g., 414) are further formed in the global interconnects (formed in BEOL) of the interconnects (e.g., 500) included in each semiconductor die (e.g., 10, 20, and / or 30), see [link to documentation]. Figure 18 Semiconductor device 10000B. Formation and material bonding of thermal control component 414. Figure 37 The thermal control component 414 is similar in formation and material to the previously discussed thermal control component 412; therefore, for the sake of brevity, it will not be repeated here. In some embodiments, the thermal control component 414 is electrically isolated from the interconnect 500 and the transistor 300, and is thermally coupled to the interconnect 500 and the transistor 300.

[0147] In some embodiments, the thermal control components (e.g., 412) in the local interconnects (formed in MEOL) of the interconnects (e.g., 500) included in each semiconductor die (e.g., 10, 20, and / or 30) are in a multi-pillar-form or multi-columnar-form, which are further arranged in a matrix, see [reference]. Figures 17 to 18 and Figure 37 However, this disclosure is not limited thereto. In alternative embodiments, multiple thermal control components (e.g., 422) may be incorporated in local interconnects (formed in MEOL) of interconnects (e.g., 500) included in each semiconductor die (e.g., 10, 20, and / or 30), see [link to relevant documentation]. Figure 19 The semiconductor device 10000C. In such a case, the thermal control component 422 is in bulk form or plate form with an opening surrounding the hot spot (e.g., 300), such as Figure 38 As shown. Figure 19 As shown, the semiconductor device 10000C includes a thermal control component (e.g., 422) in the local interconnects (formed in MEOL) of the interconnects (e.g., 500) included in each semiconductor die (e.g., 10, 20, and / or 30). However, this disclosure is not limited thereto. In an alternative embodiment, one or more thermal control components (e.g., 424) are further formed in the global interconnects (formed in BEOL) of the interconnects (e.g., 500) included in each semiconductor die (e.g., 10, 20, and / or 30), see [link to documentation]. Figure 20 The semiconductor device 10000D. The formation and material bonding of each of the thermal control components 422 and 424. Figure 38 The thermal control components 422 and 424 are similar in formation and material to each of the previously discussed thermal control components 412 and 414; therefore, for the sake of brevity, they will not be repeated here. In some embodiments, the thermal control components 422 and 424 are electrically isolated from and thermally coupled to the interconnect 500 and transistor 300.

[0148] In further alternative embodiments, the semiconductor device disclosed herein may employ thermal control components 412 and 422, thermal control components 412 and 424, thermal control components 414 and 422, or thermal control components 414 and 424. This disclosure is not limited thereto.

[0149] In some embodiments, multiple thermal control components 430 are used instead of thermal control components 412, 414, 422, and 424. See [reference needed] Figure 21The semiconductor device 10000E. In this case, after forming dielectric layers 6001, 6002 and 6003, a thermal control component 430 is formed in dielectric layers 6001, 6002 and 6003, wherein the thermal control component 430 is laterally covered by a corresponding one of dielectric layers 6001, 6002 and 6003. Subsequently, a bonding layer 6201 is formed over dielectric layer 6001 and the thermal control component 430 formed in dielectric layer 6001 to bond with the semiconductor substrate 202 of the second layer T2 through bonding interface IF4; a bonding layer 6202 is formed over dielectric layer 6002 and the thermal control component 430 formed in dielectric layer 6002 to bond with the semiconductor substrate 202 of the third layer T3 through bonding interface IF5; and a bonding layer 6203 is formed over dielectric layer 6003 and the thermal control component 430 formed in dielectric layer 6003 to bond with the carrier 50 through bonding interface IF6. Bonding interfaces IF4, IF5, and IF6 independently include dielectric-to-dielectric bonding interfaces (e.g., oxide-to-silicon bonding interfaces or nitride-to-silicon bonding interfaces). The formation and material bonding of the thermal control component 430 are also discussed. Figure 37 The thermal control component 430 is similar in formation and material to the previously discussed thermal control component 412, and the bonding layers 6201 to 6203 are similar in construction and material to the previously discussed dielectric layers 6001 to 6003; therefore, for the sake of brevity, they will not be repeated here. In embodiments implementing the thermal control component 430, the presence of bonding layers 6201 to 6203 provides uniformity at the bonding surfaces, making the bonding process more reliable. In some embodiments, the thermal control component 430 is electrically isolated from the interconnect 500 and the transistor 300, and thermally coupled to the interconnect 500 (e.g., the metallization layer ML). N (Not in contact with thermal control component 430) and transistor 300.

[0150] In a further alternative embodiment, in addition to thermal control component 412, thermal control component 430 (see [link to alternative embodiment]) may also be used. Figure 22 The semiconductor device 10000F; in addition to thermal control components 412 and / or 414, a thermal control component 430 (not shown) may also be used; in addition to thermal control component 422, a thermal control component 430 (see Figure 23 The semiconductor device 10000G; in addition to thermal control components 422 and / or 424, a thermal control component 430 (not shown) may also be used; in addition to thermal control components 412 and 422, a thermal control component 430 (see Figure 24The semiconductor device 10000H; in addition to thermal control components 412 and 424, a thermal control component 430 (not shown) may also be used; in addition to thermal control components 414 and 422, a thermal control component 430 (not shown) may also be used; in addition to thermal control components 414 and 424, a thermal control component 430 (not shown) may also be used; in addition to thermal control components 412, 414 and 422, a thermal control component 430 (not shown) may also be used; in addition to thermal control components 412, 414 and 424, a thermal control component 430 (not shown) may also be used; in addition to thermal control components 412, 422 and 424, a thermal control component 430 (not shown) may also be used; or, in addition to thermal control components 414, 422 and 424, a thermal control component 430 (not shown) may also be used.

[0151] In some embodiments, multiple thermal control components 440 are used instead of thermal control components 412, 414, 422, and 424, see [reference]. Figure 25 The semiconductor device 10000I. In this case, after forming dielectric layers 6001, 6002 and 6003, a thermal control component 440 is formed in dielectric layers 6001, 6002 and 6003, wherein the thermal control component 440 is laterally covered by a corresponding one of dielectric layers 6001, 6002 and 6003. Subsequently, a bonding layer 6201 is formed over dielectric layer 6001 and the thermal control component 440 formed in dielectric layer 6001 to bond with the semiconductor substrate 202 of the second layer T2 through bonding interface IF4; a bonding layer 6202 is formed over dielectric layer 6002 and the thermal control component 440 formed in dielectric layer 6002 to bond with the semiconductor substrate 202 of the third layer T3 through bonding interface IF5; and a bonding layer 6203 is formed over dielectric layer 6003 and the thermal control component 440 formed in dielectric layer 6003 to bond with the carrier 50 through bonding interface IF6. Bonding interfaces IF4, IF5, and IF6 independently include dielectric-to-dielectric bonding interfaces (e.g., oxide-to-silicon bonding interfaces or nitride-to-silicon bonding interfaces). The formation and material bonding of the thermal control component 440 are also discussed. Figure 38 The thermal control component 440 is similar in formation and material to the previously discussed thermal control component 422, and the bonding layers 6201 to 6203 are similar in construction and material to the previously discussed dielectric layers 6001 to 6003; therefore, for the sake of brevity, they will not be repeated here. In embodiments implementing the thermal control component 440, the presence of bonding layers 6201 to 6203 provides uniformity at the bonding surfaces, making the bonding process more reliable. In some embodiments, the thermal control component 440 is electrically isolated from the interconnect 500 and the transistor 300, and thermally coupled to the interconnect 500 (e.g., the metallization layer ML).N (Not in contact with thermal control component 440) and transistor 300.

[0152] In a further alternative embodiment, in addition to thermal control component 412, thermal control component 440 (see [link to alternative embodiment]) can also be used. Figure 26 The semiconductor device 10000J; in addition to thermal control components 412 and / or 414, a thermal control component 440 (not shown) may also be used; in addition to thermal control component 422, a thermal control component 440 (see Figure 27 The semiconductor device (10000K); in addition to thermal control components 422 and / or 424, a thermal control component 440 (not shown) may also be used; in addition to thermal control components 412 and 422, a thermal control component 440 (see Figure 28 The semiconductor device 10000L; in addition to thermal control components 412 and 424, a thermal control component 440 (not shown) may also be used; in addition to thermal control components 414 and 422, a thermal control component 440 (not shown) may also be used; in addition to thermal control components 414 and 424, a thermal control component 440 (not shown) may also be used; in addition to thermal control components 412, 414 and 422, a thermal control component 440 (not shown) may also be used; in addition to thermal control components 412, 414 and 424, a thermal control component 440 (not shown) may also be used; in addition to thermal control components 412, 422 and 424, a thermal control component 440 (not shown) may also be used; or, in addition to thermal control components 414, 422 and 424, a thermal control component 440 (not shown) may also be used.

[0153] In some embodiments, one or more thermal control components 412, 414, 422, and 424 are replaced by one or more thermal control components 450. In embodiments implementing one or more thermal control components 450, the thermal control components 450 are configured to replace one or more dielectric layers 6001 to 6003, respectively. In such cases, the thermal control components 450 are in the form of a continuous plate overlapping the hot spot (e.g., 300). For example, in Figure 29In the semiconductor device 10000M, a thermal control component 450 is disposed above the top surface S500 of the interconnect 500 in the third layer T3, replacing the dielectric layer 6003. In this case, after the thermal control component 450 is formed, a bonding layer 6203 is formed above the thermal control component 450 to facilitate subsequent bonding processes between the third layer T3 (e.g., semiconductor die 30) and the carrier 50 via the bonding interface IF6. However, this disclosure is not limited to this; alternatively, if only one thermal control component 450 is used, any of the dielectric layers 6001, 6002, and / or 6003 can be replaced. The number of thermal control components 450 is not limited to the embodiments disclosed above, and can be selected and specified according to requirements and / or product design requirements / layouts to replace one, some, or all of dielectric layers 6001, 6002, and / or 6003, and form a bonding layer (e.g., 6201, 6202, and / or 620) on top of each to facilitate bonding processes between subsequent different layers (e.g., T1 to T3) or between the carrier (e.g., 50) and the outermost layer (e.g., T3). The formation and materials of thermal control components 450 are similar to or substantially the same as those of thermal control components 412 previously discussed, and the construction and materials of bonding layers (e.g., 6201 to 6203) are similar to or substantially the same as those of dielectric layers 6001 to 6003 previously discussed; therefore, for the sake of brevity, they will not be repeated here. In embodiments implementing the thermal control component 450, the presence of bonding layers 6201 to 6203 enhances the bonding process due to the uniformity at the bonding surfaces. In some embodiments, the thermal control component 450 is electrically isolated from the interconnect 500 and the transistor 300, and thermally coupled to the interconnect 500 (e.g., the metallization layer ML). N (Not in contact with thermal control component 450) and transistor 300.

[0154] In an alternative embodiment, in addition to thermal control components 412, 414, 422 and / or 424, the semiconductor device disclosed herein further employs at least one thermal control component 450. In another alternative embodiment, in addition to thermal control component 430, at least one thermal control component 450 may be employed, and at least one of thermal control components 412, 414, 422 and / or 424 may not be present (see [link to alternative embodiment]). Figure 30 The semiconductor device 10000N or having at least one of thermal control components 412, 414, 422 and / or 424 (not shown); in addition to thermal control component 440, at least one thermal control component 450 may be used, and at least one of thermal control components 412, 414, 422 and / or 424 may not be present (see Figure 31The semiconductor device 10000O or having at least one of thermal control components 412, 414, 422 and / or 424 (not shown); or, in addition to thermal control components 430 and 440, at least one thermal control component 450 may be used, and at least one of thermal control components 412, 414, 422 and / or 424 may not be present (see Figure 32 The semiconductor device 10000P or having at least one of thermal control components 412, 414, 422 and / or 424 (not shown).

[0155] The semiconductor device disclosed herein may employ multiple thermal control components 470, which may or may not have thermal control components 412, 414, 422, 424, 430, 440, and / or 450. In some embodiments, the thermal control component 470 is formed in the global interconnect (formed in BEOL) of the interconnect (e.g., 500) included in at least one semiconductor die (e.g., 10, 20, and / or 30) and penetrates at least two dielectric layers (e.g., dielectric layer 6001 and dielectric layers 5101 to 510 in the first level T1). N At least one of the dielectric layers 6002 and 5101 to 510 in the second layer T2 N At least one of the following, and / or the 6003 in the third layer T3 and dielectric layers 5101 to 510 N (at least one of them). The thermal control assembly 470 is in the form of a multi-column or multi-cylinder structure, which is further arranged in a matrix, see [reference]. Figures 33 to 34 and Figure 37 After forming one of dielectric layers 6001, 6002, and 6003, a thermal control component 470 is formed within one of dielectric layers 6001, 6002, and 6003 and at least one underlying dielectric layer. The thermal control component 470 is laterally covered by one of dielectric layers 6001, 6002, and 6003 and the at least one underlying dielectric layer. Subsequently, a bonding layer (e.g., 6201, 6202, and / or 6203) is formed over one of dielectric layers 6001, 6002, and 6003 and the thermal control component 470 to bond to the overlying semiconductor substrate 202 or the overlying carrier 50 via bonding interfaces (e.g., IF4, IF5, and / or IF6). The formation and material bonding of the thermal control component 470... Figure 37The thermal control component 470 is similar in formation and material to the previously discussed thermal control component 412, and the bonding layers 6201 to 6203 are similar in construction and material to the previously discussed dielectric layers 6001 to 6003; therefore, for the sake of brevity, they will not be repeated here. In embodiments implementing the thermal control component 470, the presence of bonding layers 6201 to 6203 results in a more reliable bonding process due to the uniformity at the bonding surfaces. In some embodiments, the thermal control component 470 is electrically isolated from and thermally coupled to the interconnect 500 and transistor 300.

[0156] In a non-limiting example, thermal control assembly 470 is formed together with thermal control assembly 412 in the first level T1, see [reference needed]. Figure 33 The semiconductor device 10000Q. In another non-limiting example, thermal control component 470 is formed together with thermal control component 412 in the first level T1 and the third level T3, see [reference]. Figure 34The semiconductor device 10000R. However, this disclosure is not limited thereto. Alternatively, in addition to thermal control components 412 and 414, thermal control component 470 may be formed in the first layer T1, the second layer T2, and / or the third layer T3; in addition to thermal control components 412 and 422, thermal control component 470 may be formed in the first layer T1, the second layer T2, and / or the third layer T3; in addition to thermal control components 412 and 424, thermal control component 470 may be formed in the first layer T1, the second layer T2, and / or the third layer T3; in addition to thermal control components 412, 414, and 422, thermal control component 470 can also be formed in the first level T1, the second level T2, and / or the third level T3; in addition to thermal control components 412, 414, and 424, thermal control component 470 can also be formed in the first level T1, the second level T2, and / or the third level T3; in addition to thermal control components 412, 414, 422, and 424, thermal control component 470 can also be formed in the first level T1, the second level T2, and / or the third level T3; in addition to thermal control component 414, The thermal control component 470 can be further formed in the first level T1, the second level T2, and / or the third level T3; in addition to thermal control components 414 and 422, the thermal control component 470 can be further formed in the first level T1, the second level T2, and / or the third level T3; in addition to thermal control components 414 and 424, the thermal control component 470 can be further formed in the first level T1, the second level T2, and / or the third level T3; in addition to thermal control components 414, 422, and 424, the thermal control component 470 can be further formed in... In the first level T1, the second level T2, and / or the third level T3; in addition to thermal control component 422, thermal control component 470 may also be formed in the first level T1, the second level T2, and / or the third level T3; in addition to thermal control components 422 and 424, thermal control component 470 may also be formed in the first level T1, the second level T2, and / or the third level T3; or, in addition to thermal control component 424, thermal control component 470 may also be formed in the first level T1, the second level T2, and / or the third level T3. Alternatively, thermal control component 470 may be formed in the first level T1, the second level T2, and / or the third level T3, without thermal control components 412, 414, 422, and 424.

[0157] The semiconductor device disclosed herein may employ multiple thermal control components 480, which may or may not have thermal control components 412, 414, 422, 424, 430, 440, and / or 450. In some embodiments, the thermal control component 480 is formed in the global interconnect (formed in BEOL) of an interconnect (e.g., 500) included in at least one semiconductor die (e.g., 10, 20, and / or 30) and penetrates at least two dielectric layers (e.g., dielectric layer 6001 and dielectric layers 5101 to 510 in the first level T1). N At least one of the dielectric layers 6002 and 5101 to 510 in the second layer T2 N At least one of the dielectric layers 6003 and 5101 to 510 in the third layer T3 N (at least one of them). For example, the thermal control component 480 is in the form of a continuous sheet overlapping the hot spot (e.g., 300), such as Figures 35 to 36 and Figure 38 As shown. After forming one of dielectric layers 6001, 6002, and 6003, a thermal control component 480 is formed within one of the dielectric layers 6001, 6002, and 6003 and at least one underlying dielectric layer. The thermal control component 480 is laterally covered by one of the dielectric layers 6001, 6002, and 6003 and the at least one underlying dielectric layer. Subsequently, a bonding layer (e.g., 6201, 6202, and / or 6203) is formed over one of the dielectric layers 6001, 6002, and 6003 and the thermal control component 480 to bond to the overlying semiconductor substrate 202 or the overlying carrier 50 via bonding interfaces (e.g., IF4, IF5, and / or IF6). The formation and material bonding of the thermal control component 480... Figure 38 The thermal control component 422 is similar in formation and material to, and substantially the same as, the bonding layers 6201 to 6203 are similar in construction and material to, the dielectric layers 6001 to 6003 discussed previously; therefore, for the sake of brevity, they will not be repeated here. In embodiments implementing the thermal control component 480, the presence of bonding layers 6201 to 6203 results in a more reliable bonding process due to the uniformity at the bonding surfaces. In some embodiments, the thermal control component 480 is electrically isolated from, and thermally coupled to, the interconnect 500 and the transistor 300.

[0158] In alternative embodiments, some of the thermal control components 470 may be replaced by thermal control component 480, or vice versa; therefore, thermal control components 470 and 480 may coexist in a single semiconductor device disclosed herein. In the above embodiments, for illustrative purposes and simplicity, for semiconductor dies 10, 20, and 30, each interconnect (e.g., 500) includes only one building layer (e.g., L1) with embedded thermal control components 412 / 424 and / or each interconnect (e.g., 500) includes only one building layer (e.g., L1). N-3 The interconnects may have internally embedded thermal control components 414 / 424, but this disclosure is not limited thereto. Alternatively, for semiconductor dies 10, 20, and 30, one, more, or all of the building layers of local interconnects included in the interconnects (e.g., 500) may have internally embedded thermal control components 412 / 422; and / or one, more, or all of the building layers of global interconnects included in the interconnects (e.g., 500) may have internally embedded thermal control components 414 / 424. In alternative embodiments, thermal control component 430 may be formed only in one or some of dielectric layers 6001, 6002, and 6003, and this disclosure is not limited thereto. In alternative embodiments, thermal control component 440 may be formed only in one or some of dielectric layers 6001, 6002, and 6003, and this disclosure is not limited thereto.

[0159] Figures 39 to 42 Schematic cross-sectional views are shown of various stages in a method of manufacturing a semiconductor device (e.g., 20000) according to some embodiments of this disclosure. Figures 43 to 46 Schematic cross-sectional views of semiconductor devices (e.g., 30000, 40000, 50000, or 60000) according to alternative embodiments of this disclosure are shown respectively. Components similar to or substantially the same as those previously described will use the same reference numerals, and certain details or descriptions of the same components (e.g., materials, forming processes, positioning configurations, electrical connections, etc.) will not be repeated.

[0160] refer to Figure 39 In some embodiments, continuing from Figure 12 After the described process, for Figure 12 The structure shown undergoes a cutting (monodilation) process to form multiple stacking units 40A. Figure 39For illustrative purposes and simplicity, only one stacking cell 40A is shown. Each stacking cell 40A may include a semiconductor die 30 (e.g., a product of cutting through circuit wafer W3) in a third layer T3, a semiconductor die 20 (e.g., a product of cutting through circuit wafer W2) disposed on and electrically coupled to the semiconductor die 30 in the third layer T3, and a semiconductor die 10 (e.g., a product of cutting through circuit wafer W1) disposed on and electrically coupled to the semiconductor die 20 in a first layer T1. For example, in the stacking cell 40A, the sidewalls of the semiconductor die 30, the semiconductor die 20, and the semiconductor die 10 are aligned with each other. That is, the sidewalls of the semiconductor die 30, the semiconductor die 20, and the semiconductor die 10 together constitute the sidewalls of the stacking cell 40A, as shown below. Figure 39 As shown. In one embodiment, the dicing (monodilation) process is a wafer dicing process that includes mechanical blade sawing or laser cutting. This disclosure is not limited thereto.

[0161] refer to Figure 40 In some embodiments, a carrier substrate 54 is provided, and a release layer 56 is formed over the carrier substrate 54. The carrier substrate 54 may be a glass carrier substrate, a ceramic carrier substrate, or the like. The carrier substrate 54 may be a wafer, allowing multiple packages to be formed simultaneously over the carrier substrate 54. The release layer 56 may be formed of a polymer-based material that can be removed along with the carrier substrate 54 from the overlay structure to be formed in subsequent steps. In some embodiments, the release layer 56 is an epoxy-based heat-releasing material that loses its adhesive properties when heated, such as a light-to-heat conversion (LTHC) release coating. In other embodiments, the release layer 56 may be a UV adhesive that loses its adhesive properties when exposed to ultraviolet (UV) light. The release layer 56 may be dispensed and cured as a liquid, may be a laminate film stacked onto the carrier substrate 54, or may be formed on the carrier substrate 54 by any suitable method. The top surface of release layer 56 can be smoothed.

[0162] In some embodiments, at least one stacking unit 40A is picked up and placed above the release layer 56 and on the carrier substrate 54. Figure 40As shown, for illustrative purposes, only one stacking unit 40A is presented as at least one stacking unit 40A, but it is worth noting that the number of at least one stacking unit 40A can be one, two, three, or more, and this disclosure is not limited thereto. For example, the top surface S500 of the interconnect 500 included in the third level T3 is placed above the release layer 56 (e.g., in physical contact). Figure 40 As shown, the surface S202b of the semiconductor substrate 202 included in the first layer T1 can be facing upwards.

[0163] refer to Figure 41 In some embodiments, the stacked cells 40A are encapsulated in an insulating material. In some embodiments, an insulating encapsulation material (not shown) is formed over the stacked cells 40A and the release layer 56 on the carrier substrate 54, wherein the stacked cells 40A and the release layer 56 exposed by the stacked cells 40A are completely covered by the insulating encapsulation material. The insulating encapsulation material may be made of a dielectric material (e.g., oxides (e.g., silicon oxide), nitrides (e.g., silicon nitride), tetraethyl orthosilicate (TEOS) oxide, or the like) or any insulating material suitable for gap filling, and may be formed by deposition (e.g., CVD process). Alternatively, the insulating encapsulation material may be a molding compound, a molding underfill adhesive, a resin (e.g., an epoxy-based resin), or the like, which may be formed by a molding process. The molding process may include a compression molding process or a transfer molding process. The insulating encapsulation material may include polymers (e.g., epoxy resins, phenolic resins, silicone resins, or other suitable resins) or other suitable materials. Alternatively, the insulating encapsulation material may comprise an acceptable insulating encapsulation material. In some embodiments, the insulating encapsulation material further comprises inorganic fillers or inorganic compounds (e.g., silica, clay, etc.) that can be added to the insulating encapsulation material to optimize the coefficient of thermal expansion (CTE) of the insulating encapsulation material. This disclosure is not limited thereto.

[0164] After forming the insulating encapsulation material, a planarization process is performed on the insulating encapsulation material to form an insulating encapsulation 1900 that exposes the stacked cell 40A. For example, a portion of the insulating encapsulation material is removed to form an insulating encapsulation 1900 having the shown top surface S1900, wherein the shown top surface S1900 of the insulating encapsulation 1900 can be tactilely exposed to the first layer T1 (e.g., the surface S1 of the semiconductor substrate 202 included in the first layer T1 of the semiconductor die 10 and the surface S1001 of the via 1001 exposed by the surface S1). For example, the shown top surface S1900 of the insulating encapsulation 1900 is substantially flush with the surface S1 of the semiconductor substrate 202 included in the first layer T1 of the semiconductor die 10 and the surface S1001 of the via 1001. In other words, the top surface S1900 of the insulating encapsulation 1900 is substantially coplanar with the surface S1 of the semiconductor substrate 202 included in the first layer T1 of the semiconductor die 10 and the surface S1001 of the through hole 1001.

[0165] In some embodiments, a cleaning step may be optionally performed after the planarization process, for example to clean and remove residues generated from the planarization process. However, this disclosure is not limited to this, and the planarization process can be performed by any other suitable method. Additionally, during the planarization process, a portion of the semiconductor substrate 202 and the via 1001 of the first layer T1 scraped in the stacked cell 40A may be slightly removed. This disclosure is not limited to this. Figure 41 As shown, the stacking unit 40A may be laterally encapsulated in an insulating enclosure 1900.

[0166] Continue to refer to Figure 41 In some embodiments, after forming the insulating enclosure 1900, interconnects 1500, dielectric layers 1600 and 1700, and a plurality of conductive terminals 1800 are formed over the insulating enclosure 1900 and the stacked units 40A laterally encapsulated within the insulating enclosure 1900. Details, formation, and materials of the interconnects 1500, dielectric layers 1600, dielectric layers 1700, and the plurality of conductive terminals 1800 have been described in [details omitted]. Figure 15 This has been discussed before, so for the sake of brevity, it will not be repeated here.

[0167] refer to Figure 42In some embodiments, the carrier substrate 54 is removed. The carrier substrate 54 can be detached (or "peeled off") from the insulating enclosure 1900 and the stacked units 40A laterally encapsulated within the insulating enclosure 1900. In some embodiments, the peeling includes irradiating the release layer 56 with light (e.g., laser light or UV light), causing the release layer 56 to decompose under the heat of the light, and the carrier substrate 54 can be removed. For example, the peeling exposes the insulating enclosure 1900 and the stacked units 40A laterally encapsulated within the insulating enclosure 1900 (e.g., the surface S500 of the interconnect 500 included in the third level T3) in an accessible manner.

[0168] In some embodiments, after removing the carrier substrate 54 and the release layer 56, a dielectric layer 6003 and a carrier 50 are sequentially formed on the insulating encapsulation 1900 and the stacked units 40A laterally encapsulated within the insulating encapsulation 1900. The dielectric layer 6003 extends continuously from the stacked units 40A onto the insulating encapsulation 1900, for example, and the carrier 50 completely covers the dielectric layer 6003. Figure 42 As shown, the carrier 50 can be bonded to the top surface S6003 of the dielectric layer 6003 via the bonding interface IF3. Details, formation, and materials of the dielectric layer 6003 and the carrier 50 have been described in [the diagram / illustration]. Figure 13 This has been discussed before, so for the sake of brevity, it will not be repeated here.

[0169] Continue to refer to Figure 42 The process involves a cutting (monomeric) process to cut through the carrier 50, dielectric layer 6003, insulating encapsulation 1900, rearranged circuit structure 1500, dielectric layer 1600, and dielectric layer 1700 to form multiple stacked units 2000. Figure 42For illustrative purposes and for simplicity, only one stacking unit 2000 is shown. Each stacking unit 2000 may include a carrier 50, a stacking unit 40A (a semiconductor die 30 disposed on and thermally coupled to the carrier 50 and in a third level T3, a semiconductor die 20 disposed on and electrically coupled to the semiconductor die 30 and in a second level T2, and a semiconductor die 10 disposed on and electrically coupled to the semiconductor die 20 and in a first level T1), a redistribution circuit structure 1500 disposed on and electrically coupled to the semiconductor die 10 in the first level T1, a dielectric layer 1600 disposed on the redistribution circuit structure 1500, a dielectric layer 1700 disposed on the dielectric layer 1600, and a plurality of conductive terminals 1800 disposed on the redistribution circuit structure 1500 and electrically coupled to the redistribution circuit structure 1500 through the dielectric layers 1600 and 1700. For example, in stacking cell 2000, the sidewalls of carrier 50, dielectric layer 6003, insulating encapsulation 1900, redistribution structure 1500, dielectric layer 1600, and dielectric layer 1700 are aligned with each other. That is, the sidewalls of carrier 50, dielectric layer 6003, insulating encapsulation 1900, redistribution structure 1500, dielectric layer 1600, and dielectric layer 1700 together constitute the sidewalls 2000 of the stacking cell, such as... Figure 42 As shown. In one embodiment, the dicing (monodilation) process is a wafer dicing process that includes mechanical blade sawing or laser cutting. This disclosure is not limited thereto.

[0170] Next, heat dissipation modules can be sequentially formed on the carrier 50. For example, the cover 800 is disposed (e.g., adhered to) the carrier 50 through a thermally conductive adhesive 710 between the cover 800 and the carrier 50, and the heat sink 900 is disposed (e.g., adhered to) the cover 800 through a thermally conductive adhesive 720 between the heat sink 900 and the cover 800. The details, formation, and materials of the thermally conductive adhesive 710, cover 800, thermally conductive adhesive 720, and heat sink 900 sequentially formed on the insulating encapsulation 1900 are described in [the original text]. Figure 16 This will not be discussed further here for the sake of brevity. At this point, the semiconductor device 20000 is complete. For example, in the semiconductor device 20000, the sidewalls of the heat sink 900, the thermally conductive adhesive 720, the cover 800, the thermally conductive adhesive 710, and the stacking unit 2000 are aligned with each other. That is, the sidewalls of the heat sink 900, the thermally conductive adhesive 720, the cover 800, the thermally conductive adhesive 710, and the stacking unit 2000 together constitute the sidewalls of the semiconductor device 20000, as shown below. Figure 42As shown. In one embodiment, the dicing (monodilation) process is a wafer dicing process that includes mechanical blade sawing or laser cutting. This disclosure is not limited thereto. However, this disclosure is not limited thereto, and in alternative embodiments, the sidewalls of the heat sink 900, the sidewalls of the thermally conductive adhesive 720, the sidewalls of the cover 800, and / or the sidewalls of the thermally conductive adhesive 710 are not aligned with the sidewalls of the stacking unit 2000.

[0171] In some embodiments, Figure 43 Semiconductor device 30000 and Figure 42 The semiconductor device 20000 is similar, except that stacking cell 40A is replaced by stacking cell 40B. For example... Figure 43 As shown, the stacking unit 40B may include a semiconductor die 30 in a third layer T3, a semiconductor die 20 disposed on and electrically coupled to the semiconductor die 30 in a second layer T2, a semiconductor die 10 disposed on and electrically coupled to the semiconductor die 30 in a first layer T1, and an insulating encapsulation 1910 that laterally encapsulates the semiconductor dies 10 and 20. For example, in the stacking unit 40B, the sidewalls of the insulating encapsulation 1910 are aligned with the sidewalls of the semiconductor die 30. That is, the sidewalls of the insulating encapsulation 1910 and the sidewalls of the semiconductor die 30 together constitute the sidewalls of the stacking unit 40B. In a non-limiting example, at least one through-hole 1002 penetrates semiconductor dies 20 and 30 to contact semiconductor dies 10, 20 and 30 to provide a suitable electrical connection between semiconductor dies 10, 20 and 30, and at least one through-hole 1003 penetrates semiconductor die 30 to contact semiconductor die 20 to provide a suitable electrical connection between semiconductor dies 20 and 30, as shown. Figure 43 As shown.

[0172] Stacked cell 40B can be formed by, but is not limited to, providing circuit chip W1 and circuit chip W2 (respectively similar). Figures 1 to 7 and Figure 8 (The process); through WoW bonding, circuit chip W1 and circuit chip W2 are bonded (similar to...) Figure 9 The process involves performing a dicing process on the bonded structure having circuit wafers W1 and W2 to form multiple separate and individual bonded structures having semiconductor dies 10 and 20 (similar to the process described above). Figure 16 or Figure 39 (process); provides circuit chip W3 (similar) Figure 10 (The process); through chip-on-wafer (CoW) technology, the bonded structure having semiconductor dies 10 and 20 is bonded to the circuit chip W3; the bonded structure having semiconductor dies 10 and 20 is laterally encapsulated in an insulating encapsulator 1910 (similar to...). Figure 41 (process); forming at least one perforation 1002 and at least one perforation 1003 (similar) Figure 12 The process involves: (1) a dicing process on the circuit chip W3 and the insulating encapsulation 1910 to form multiple separate and individual stacked units 40B (similar to...). Figure 16 or Figure 39 (The process).

[0173] In some embodiments, Figure 44 Semiconductor device 40000 and Figure 42 The semiconductor device 20000 is similar, except that stacking cell 40A is replaced with stacking cell 40C. For example... Figure 44 As shown, the stacking unit 40C may include a semiconductor die 30 in a third layer T3, a semiconductor die 20 disposed on and electrically coupled to the semiconductor die 30 in a second layer T2, a semiconductor die 10 disposed on and electrically coupled to the semiconductor die 30 in a first layer T1, an insulating encapsulation 1910 laterally encapsulating the semiconductor die 10, and an insulating encapsulation 1920 laterally encapsulating the semiconductor die 20 and the insulating encapsulation 1910. For example, in the stacking unit 40C, the sidewalls of the insulating encapsulation 1920 are aligned with the sidewalls of the semiconductor die 30. That is, the sidewalls of the insulating encapsulation 1920 and the sidewalls of the semiconductor die 30 together constitute the sidewalls of the stacking unit 40C, such as... Figure 44 As shown. In a non-limiting example, at least one through-hole 1002 penetrates semiconductor dies 20 and 30 to contact semiconductor dies 10, 20 and 30 to provide a suitable electrical connection between semiconductor dies 10, 20 and 30, and at least one through-hole 1003 penetrates semiconductor die 30 to contact semiconductor die 20 to provide a suitable electrical connection between semiconductor dies 20 and 30, as shown. Figure 44 As shown.

[0174] The stacked cell 40C can be formed by, but is not limited to, providing a circuit chip W1 (similar to) Figures 1 to 7 The process involves dicing the circuit wafer W1 to form multiple separate and individual semiconductor dies 10 (similar to the process described above). Figure 16 or Figure 39 (process); at least one semiconductor die 10 is bonded to the circuit wafer W2 via CoW bonding; at least one semiconductor die 10 is laterally encapsulated in an insulating encapsulation 1910 (similar to...) Figure 41(The process); a dicing process is performed on the bonded structure having at least one semiconductor die 10 and a circuit wafer W2 to cut through the insulating encapsulation 1910 and the circuit wafer W2, thereby forming a plurality of separate and individual bonded structures having semiconductor dies 10 and 20 (similar to...). Figure 16 or Figure 39 (process); provides circuit chip W3 (similar) Figure 10 (The process); through the CoW process, the bonded structure having semiconductor dies 10 and 20 is bonded to the circuit chip W3; the bonded structure having semiconductor dies 10 and 20 is laterally encapsulated in an insulating encapsulation 1920 (similar to...). Figure 41 (process); forming at least one perforation 1002 and at least one perforation 1003 (similar) Figure 12 The process involves dicing the circuit wafer W3 and the insulating encapsulation 1920 to form multiple separate and individual stacked cells 40C. The formation and materials of the insulating encapsulation 1920 are similar to or substantially the same as those of the insulating encapsulation 1910 discussed above, and therefore will not be repeated here.

[0175] In some embodiments, Figure 45 Semiconductor device 50000 and Figure 42 The semiconductor device 20000 is similar, except that stacking cell 40A is replaced by stacking cell 40D. For example... Figure 45 As shown, the stacking unit 40D may include a semiconductor die 30 in a third layer T3, a semiconductor die 20 disposed on and electrically coupled to the semiconductor die 30 in a second layer T2, a semiconductor die 10 disposed on and electrically coupled to the semiconductor die 30 in a first layer T1, an insulating encapsulator 1910 laterally encapsulating the semiconductor die 10, and an insulating encapsulator 1930 laterally encapsulating the semiconductor die 30. For example, in the stacking unit 40D, the sidewalls of the insulating encapsulator 1930 and the sidewalls of the insulating encapsulator 1910 are aligned with the sidewalls of the semiconductor die 20. That is, the sidewalls of the insulating encapsulator 1930 and the sidewalls of the insulating encapsulator 1910 together with the sidewalls of the semiconductor die 20 constitute the sidewalls of the stacking unit 40D, such as... Figure 45 As shown. In a non-limiting example, at least one through-hole 1002 penetrates semiconductor dies 20 and 30 to contact semiconductor dies 10, 20 and 30 to provide a suitable electrical connection between semiconductor dies 10, 20 and 30, and at least one through-hole 1003 penetrates semiconductor die 30 to contact semiconductor die 20 to provide a suitable electrical connection between semiconductor dies 20 and 30, as shown. Figure 45As shown. In another non-limiting example, at least one through-hole 1002 penetrates the insulating encapsulation 1930 and the semiconductor die 20 to contact the semiconductor dies 10 and 20 to provide a suitable electrical connection between the semiconductor dies 10 and 20, and at least one through-hole 1003 penetrates the semiconductor die 30 to contact the semiconductor die 20 to provide a suitable electrical connection between the semiconductor dies 20 and 30.

[0176] The stacked cell 40D can be formed by, but is not limited to, providing a circuit chip W1 (similar to) Figures 1 to 7 The process involves dicing the circuit wafer W1 to form multiple separate and individual semiconductor dies 10 (similar to the process described above). Figure 16 or Figure 39 (process); at least one semiconductor die 10 is bonded to the circuit wafer W2 via CoW bonding; at least one semiconductor die 10 is laterally encapsulated in an insulating encapsulation 1910 (similar to...) Figure 41 (process); provides circuit chip W3 (similar) Figure 10 The process involves dicing the circuit wafer W3 to form multiple separate and individual semiconductor dies 30 (similar to the process described above). Figure 16 or Figure 39 (process); at least one semiconductor die 30 is bonded to the circuit chip W2 via CoW bonding; at least one semiconductor die 30 is laterally encapsulated in an insulating encapsulation 1930 (similar to...) Figure 41 (process); forming at least one perforation 1002 and at least one perforation 1003 (similar) Figure 12 The process involves performing a dicing process on the insulating enclosure 1930, the circuit wafer W2, and the insulating enclosure 1910 to form multiple separate and individual stacked cells 40D (similar to the process described above). Figure 16 or Figure 39 (The process). The formation and materials of the insulating encapsulation 1930 are similar to or substantially the same as those of the insulating encapsulation 1910 discussed above, and therefore will not be repeated here.

[0177] In some embodiments, Figure 46 Semiconductor device 60000 and Figure 42 The semiconductor device 20000 is similar, except that stacking cell 40A is replaced with stacking cell 40E. For example... Figure 46As shown, the stacking unit 40E may include an insulating encapsulation 1930 that laterally encapsulates the semiconductor die 30 in the third layer T3, a semiconductor die 20 disposed on and electrically coupled to the semiconductor die 30 in the second layer T2, a semiconductor die 10 disposed on and electrically coupled to the semiconductor die 30 in the first layer T1, and an insulating encapsulation 1930 that laterally encapsulates the semiconductor die 30. For example, in the stacking unit 40E, the sidewalls of the insulating encapsulation 1930, the sidewalls of the semiconductor die 20, and the sidewalls of the semiconductor die 10 are aligned with each other. That is, the sidewalls of the insulating encapsulation 1930, the sidewalls of the semiconductor die 20, and the sidewalls of the semiconductor die 10 together constitute the sidewalls of the stacking unit 40E, such as... Figure 46 As shown.

[0178] In a non-limiting example, at least one through-hole 1002 penetrates the insulating enclosure 1930 and the semiconductor die 20 to contact semiconductor dies 10 and 20 to provide a suitable electrical connection between semiconductor dies 10 and 20, and at least one through-hole 1003 penetrates the semiconductor die 30 to contact semiconductor die 20 to provide a suitable electrical connection between semiconductor dies 20 and 30, such as Figure 46 As shown. In another non-limiting example, at least one through-hole 1002 penetrates semiconductor dies 20 and 30 to contact semiconductor dies 10, 20 and 30 to provide a suitable electrical connection between semiconductor dies 10, 20 and 30, and at least one through-hole 1003 penetrates semiconductor die 30 to contact semiconductor die 20 to provide a suitable electrical connection between semiconductor dies 20 and 30.

[0179] The stacked cell 40E can be formed by, but is not limited to, providing circuit chip W1 and circuit chip W2 (respectively similar). Figures 1 to 7 and Figure 8 (The process); through WoW bonding, circuit chip W1 and circuit chip W2 are bonded (similar to...) Figure 9 (process); provides circuit chip W3 (similar) Figure 10 The process involves dicing the circuit wafer W3 to form multiple separate and individual semiconductor dies 30 (similar to the process described above). Figure 16 or Figure 39 (process); by CoW bonding, at least one semiconductor die 30 is bonded to a bonded structure having circuit wafers W1 and W2; at least one semiconductor die 30 is laterally encapsulated in an insulating encapsulation 1930 (similar to...). Figure 41 (process); forming at least one perforation 1002 and at least one perforation 1003 (similar) Figure 12The process involves: (1) performing a process to cut the insulating encapsulation 1930 and the bonded structure having circuit wafers W1 and W2 to form multiple separate and individual stacked units 40E (similar to...). Figure 16 or Figure 39 (The process).

[0180] Semiconductor devices 10000A, 10000B, 10000C, 10000D, 10000E, 10000F, 10000G, 10000H, 10000I, 10000J, 10000K, 10000L, 10000M, 10000N, 10000O, 10000P, 10000Q, 10000R, 10000S, 10000T, 20000, 30000, 40000, 50000, 60000, and / or variations thereof can each be die-form or chip-form. Although each semiconductor device disclosed herein includes only three levels in the above embodiments, the number of levels included in each semiconductor device disclosed herein may be two or more, depending on requirements and / or product design requirements / layout.

[0181] In some embodiments, the semiconductor dies (10, 20, and 30) included in the semiconductor devices 10000A, 10000B, 10000C, 10000D, 10000E, 10000F, 10000G, 10000H, 10000I, 10000J, 10000K, 10000L, 10000M, 10000N, 10000O, 10000P, 10000Q, 10000R, 10000S, 10000T, 20000, 30000, 40000, 50000, 60000, and / or variations thereof are referred to as semiconductor chips or integrated circuits, which independently include digital chips, analog chips, or mixed-signal chips.In some embodiments, the semiconductor dies (10, 20, and 30) included in the semiconductor devices 10000A, 10000B, 10000C, 10000D, 10000E, 10000F, 10000G, 10000H, 10000I, 10000J, 10000K, 10000L, 10000M, 10000N, 10000O, 10000P, 10000Q, 10000R, 10000S, 10000T, 20000, 30000, 40000, 50000, 60000, and / or variations thereof may independently be: logic dies, such as central processing units (CPUs), graphics processing units (GPUs), neural network processing units (NPUs), and deep learning processing units (DPUs). Units such as DPU, tensor processing unit (TPU), system-on-a-chip (SoC), system-on-integrated circuit (SoIC), application processor (AP), and microcontrollers; power management dies, such as power management integrated circuit (PMIC) dies; radio frequency (RF) dies; baseband (BB) dies; sensor dies, such as photo / image sensor chips; micro-electro-mechanical system (MEMS) dies; signal processing dies, such as digital signal processing (DSP) dies; front-end dies, such as analog front-end (AFE) dies; application-specific dies, such as application-specific integrated circuit (ASIC) and field-programmable gate array (FPGA); combinations thereof; or similar components.In alternative embodiments, the semiconductor dies (10, 20, and 30) included in semiconductor devices 10000A, 10000B, 10000C, 10000D, 10000E, 10000F, 10000G, 10000H, 10000I, 10000J, 10000K, 10000L, 10000M, 10000N, 10000O, 10000P, 10000Q, 10000R, 10000S, 10000T, 20000, 30000, 40000, 50000, 60000, and / or variations thereof may independently be: memory dies with or without controllers, wherein the memory dies include: single-form dies, such as dynamic random access memory (DRAM). DRAM (DRAM) die, static random access memory (SRAM) die, resistive random-access memory (RRAM), magnetoresistive random-access memory (MRAM), NAND flash memory, wide I / O memory (WIO); pre-stacked memory cubes, such as hybrid memory cube (HMC) modules, high bandwidth memory (HBM) modules; combinations thereof; or similar components.In further alternative embodiments, the semiconductor dies (10, 20, and 30) included in semiconductor devices 10000A, 10000B, 10000C, 10000D, 10000E, 10000F, 10000G, 10000H, 10000I, 10000J, 10000K, 10000L, 10000M, 10000N, 10000O, 10000P, 10000Q, 10000R, 10000S, 10000T, 20000, 30000, 40000, 50000, 60000, and / or variations thereof can independently be: artificial intelligence (AI) engines, such as AI accelerators; computing systems, such as AI servers, high-performance computing... High-power computing (HPC) systems, high-power computing devices, cloud computing systems, networking systems, edge computing systems, immersive memory computing systems (ImMC), SoIC systems, etc.; combinations thereof; or similar components. In some other embodiments, the semiconductor dies (10, 20, and 30) included in the semiconductor devices 10000A, 10000B, 10000C, 10000D, 10000E, 10000F, 10000G, 10000H, 10000I, 10000J, 10000K, 10000L, 10000M, 10000N, 10000O, 10000P, 10000Q, 10000R, 10000S, 10000T, 20000, 30000, 40000, 50000, 60000, and / or variations thereof may independently be: electrical and / or optical input / output (I / O) interface dies, integrated passive dies (IPDs), or voltage regulator dies. Local silicon interconnect die (LSI) with or without deep trench capacitor (DTC) features; local silicon interconnect die (LSI) with multi-tier functions such as electrical and / or optical network circuit interfaces, IPD, VR, DTC or similar functions; or similar components.

[0182] The types of semiconductor dies (10, 20, and 30) included in semiconductor devices 10000A, 10000B, 10000C, 10000D, 10000E, 10000F, 10000G, 10000H, 10000I, 10000J, 10000K, 10000L, 10000M, 10000N, 10000O, 10000P, 10000Q, 10000R, 10000S, 10000T, 20000, 30000, 40000, 50000, 60000, and / or variations thereof may be selected and specified based on requirements and / or product design requirements / layouts, and are therefore not specifically limited in this disclosure. In this disclosure, thermal spikes in the semiconductor device can be mitigated, thereby improving the reliability of the semiconductor device, provided that the hot spot of the semiconductor device is thermally coupled to (e.g., physically close to) a thermal control component (e.g., 412, 414, 422, 424, 430, 440, 450, 470, and / or 480). For example, in Figure 29 In the semiconductor device 10000M, semiconductor dies 10 and 20 are or include memory dies or low-power logic dies, and semiconductor die 30 is or includes high-power logic dies; therefore, the first level T1 and the second level T2 may not contain thermal control components. In another example, in Figure 33 10000Q semiconductor device neutralization Figure 35 In the semiconductor device 10000S, semiconductor dies 20 and 30 are or include memory dies or low-power logic dies, and semiconductor die 10 is or includes high-power logic dies; therefore, the second level T2 and the third level T3 may not contain thermal control components. In other examples, in Figure 34 Semiconductor device 10000R neutralization Figure 36 In the semiconductor device 10000T, semiconductor die 20 is or includes a memory die or a low-power logic die, and semiconductor dies 10 and 30 are or include high-power logic dies, so the second level T2 may not contain thermal control components.

[0183] This disclosure is not limited thereto. In this disclosure, thermal control components (e.g., 412, 414, 422, 424, 430, 440, 450, 470 and / or 480) may be employed in any combination or individually to mitigate thermal spikes in the semiconductor device of this disclosure, thereby improving the reliability of the semiconductor device of this disclosure.

[0184] Semiconductor devices 10000A, 10000B, 10000C, 10000D, 10000E, 10000F, 10000G, 10000H, 10000I, 10000J, 10000K, 10000L, 10000M, 10000N, 10000O, 10000P, 10000Q, 10000R, 10000S, 10000T, 20000, 30000, 40000, 50000, 60000 and / or variations thereof may be further mounted individually onto another electronic device component or circuit structure, such as a motherboard, packaging substrate, printed circuit board (PCB), printed wiring board, and / or other carrier capable of carrying integrated circuits. Alternatively, semiconductor devices 10000A, 10000B, 10000C, 10000D, 10000E, 10000F, 10000G, 10000H, 10000I, 10000J, 10000K, 10000L, 10000M, 10000N, 10000O, 10000P, 10000Q, 10000R, 10000S, 10000T, 20000, 30000, 40000, 50000, 60000, and / or their variations may be integrated fan-out type. Fan-Out (InFO) packages, InFO packages with a Package-on-Package (PoP) structure, chip-on-wafer-on-substrate (CoWoS) packages, flip chip packages with InFO packages, or the like, or may be part of an InFO package, an InFO package with a PoP structure, a CoWoS package, a flip chip package with InFO packages, or the like. This disclosure is not limited thereto. The conductive terminal 1800 may be referred to as a connector or terminal for semiconductor devices 10000A, 10000B, 10000C, 10000D, 10000E, 10000F, 10000G, 10000H, 10000I, 10000J, 10000K, 10000L, 10000M, 10000N, 10000O, 10000P, 10000Q, 10000R, 10000S, 10000T, 20000, 30000, 40000, 50000, 60000 and / or their variations.

[0185] Figure 46These are schematic cross-sectional views illustrating applications of semiconductor devices (e.g., semiconductor devices 10000A, 10000B, 10000C, 10000D, 10000E, 10000F, 10000G, 10000H, 10000I, 10000J, 1000K, 10000H, 10000I, 10000J, 1000K, 10010100P, 10000Q, 10000R according to some embodiments disclosed herein, (e.g., 10000S, 10000T, 20000, 30000, 40000, 50000, 60000 and / or modifications thereof). Components similar to or substantially identical to those previously described will use the same reference numerals, and certain details or descriptions of the same components (e.g., materials, forming processes, positioning configurations, electrical connections, etc.) will not be repeated.

[0186] refer to Figure 46In some embodiments, a component assembly SC is provided, comprising a first component C1 and a second component C2 disposed above the first component C1. The first component C1 may be or may include a circuit structure, such as a motherboard, a package substrate, another printed circuit board (PCB), a printed wiring board, and / or other carriers capable of carrying integrated circuits. In some embodiments, the second component C2 mounted on the first component C1 may be similar to one of the connectors or terminals of the semiconductor devices 10000A, 10000B, 10000C, 10000D, 10000E, 10000F, 10000G, 10000H, 10000I, 10000J, 10000K, 10000L, 10000M, 10000N, 10000O, 10000P, 10000Q, 10000R, 10000S, 10000T, 20000, 30000, 40000, 50000, 60000 and / or their variations. For example, one or more second components C2 (e.g., semiconductor devices 10000A, 10000B, 10000C, 10000D, 10000E, 10000F, 10000G, 10000H, 10000I, 10000J, 10000K, 10000L, 10000M, 10000N, 10000O, 10000P, 10000Q, 10000R, 10000S, 10000T, 20000, 30000, 40000, 50000, 60000, and / or variations thereof) may be electrically coupled to the first component C1 via a plurality of terminals CT. The terminals CT may be conductive terminals 1800. In some embodiments, an underfill adhesive UF is formed between the first component C1 and the second component C2 to cover the terminals CT at least laterally. Alternatively, the underfill adhesive UF can be omitted. The underfill adhesive UF can be any acceptable material, such as polymers, epoxy resins, molded underfill, or the like. In one embodiment, the underfill adhesive UF can be formed by underfill dispensing, capillary flow processes, or any other suitable method. The presence of the underfill adhesive UF enhances the bond strength between the first member C1 and the second member C2.

[0187] According to some embodiments, a semiconductor device includes a semiconductor die. The semiconductor die includes a substrate including at least one active component, an interconnect disposed on and electrically coupled to the at least one active component, and at least one first thermal control component disposed within the interconnect and thermally coupled to the at least one active component. In a vertical projection along the stacking direction of the substrate and the interconnect, the at least one active component is surrounded by the at least one first thermal control component.

[0188] In some embodiments, in the semiconductor device, the at least one first thermal control component includes a plurality of first thermal control components arranged in a matrix, the matrix having an opening, wherein in the vertical projection, the at least one active component is surrounded by the plurality of first thermal control components arranged in the matrix, and the opening overlaps with the at least one active component. In some embodiments, in the semiconductor device, the at least one first thermal control component includes a first thermal control component in the form of a block material with an internal opening or a first thermal control component in the form of a plate material with an internal opening, wherein in the vertical projection, the at least one active component is surrounded by the first thermal control component, and the opening overlaps with the at least one active component. In some embodiments, in the semiconductor device, the semiconductor die further includes a second thermal control component in the form of a continuous plate material, and the interconnect is disposed between the second thermal control component and the substrate, wherein in the vertical projection, the at least one active component overlaps with the second thermal control component. In some embodiments, in the semiconductor device, the at least one active component is separated from the at least one first thermal control component through the dielectric layer of the interconnect, and the thermal conductivity of the at least one first thermal control component is greater than the thermal conductivity of the dielectric layer of the interconnect, wherein the at least one first thermal control component comprises a solid-solid phase change material.

[0189] According to some embodiments, a semiconductor device includes a redistribution structure, a first die, a second die, and at least one through-hole. The first die is disposed on and electrically coupled to the redistribution structure. The first die includes a first substrate, the first substrate including at least one first active component, a first interconnect disposed on and electrically coupled to the at least one first active component, and at least one first thermal control component disposed inside the first interconnect and thermally coupled to the at least one first active component, wherein the at least one first active component is surrounded by the at least one first thermal control component in a vertical projection. The second die is disposed on and electrically coupled to the redistribution structure. The second die includes a second substrate, the second substrate including at least one second active component and a second interconnect disposed on and electrically coupled to the at least one second active component. The at least one through-hole is disposed on and electrically coupled to the redistribution structure, and electrically coupled to both the first die and the second die.

[0190] In some embodiments, in the semiconductor device, the first die is disposed between the second die and the redistribution structure, and the at least one through-hole penetrates the second die to electrically couple the first die and the second die. In some embodiments, in the semiconductor device, the second die is disposed between the first die and the redistribution structure, and the at least one through-hole penetrates the first die to electrically couple the first die and the second die. In some embodiments, in the semiconductor device, the second die further includes: at least one second thermal control component disposed inside the second interconnect and thermally coupled to the at least one second active component, wherein the at least one second active component is surrounded by the at least one second thermal control component in the vertical projection. In some embodiments, the semiconductor device further includes: a carrier disposed on the redistributed circuit structure, wherein the first die, the second die, and the at least one via are disposed between the carrier and the redistributed circuit structure; a heat dissipation module disposed on the carrier and thermally coupled to the carrier, wherein the carrier is disposed between the heat dissipation module and the redistributed circuit structure; and a plurality of conductive terminals disposed on the redistributed circuit structure and electrically coupled to the redistributed circuit structure, wherein the redistributed circuit structure is disposed between the carrier and the plurality of conductive terminals. In some embodiments, the semiconductor device further includes: a third die disposed on the redistributed circuit structure and electrically coupled to the redistributed circuit structure, and includes: a third substrate including at least one third active component; and a third interconnect disposed on the at least one third active component and electrically coupled to the at least one third active component, wherein the at least one via further penetrates the third die. In some embodiments, in the semiconductor device, the third die further includes: at least one third thermal control component disposed inside the third interconnect and thermally coupled to the at least one third active component, wherein the at least one third active component is surrounded by the at least one third thermal control component in the vertical projection. In some embodiments, the semiconductor device further includes: at least one additional via disposed on the redistribution structure, wherein the at least one additional via penetrates the third die to electrically couple the third die and the second die or to electrically couple the third die and the first die.

[0191] According to some embodiments, a method of manufacturing a semiconductor device includes the following steps: providing a first wafer substrate including at least one first active component; forming a building layer of a first interconnect on the first wafer substrate for electrical coupling to the at least one first active component, the building layer including a dielectric layer and a metallization layer laterally covered by the dielectric layer; patterning the dielectric layer to form at least one first opening adjacent to the metallization layer; forming a first thermal energy storage material over the dielectric layer, the first thermal energy storage material extending into the at least one first opening; performing a planarization process to remove a portion of the first thermal energy storage material over the dielectric layer to form at least one first thermal control component in the at least one first opening, the at least one first thermal control component being thermally coupled to the at least one first active component, wherein the at least one first active component is surrounded by the at least one first thermal control component in a vertical projection along the stacking direction of the first wafer substrate and the first interconnect; forming a redistribution circuit structure on the first wafer substrate; disposing a plurality of conductive terminals on the redistribution circuit structure; and performing a dicing process to form the semiconductor device including a first semiconductor die.

[0192] In some embodiments, in the method, prior to forming the redistributed circuit structure on the first wafer substrate, the method further includes: forming a first bonding layer on the first interconnect; providing a circuit wafer including a second wafer substrate having at least one second active component and a second interconnect disposed on the second wafer substrate; bonding the second wafer substrate to the first bonding layer via wafer-on-wafer bonding; forming a second bonding layer on the second interconnect; providing an additional circuit wafer including a third wafer substrate having at least one third active component and a third interconnect disposed on the third wafer substrate; bonding the third wafer substrate to the second bonding layer via wafer-on-wafer bonding; and providing at least one A via, the at least one via penetrating the additional circuit wafer and the circuit wafer; a third bonding layer formed over the third interconnect and the at least one via; and a carrier bonded to the third bonding layer via wafer-on-wafer bonding, wherein performing the dicing process includes performing a first dicing process to cut through the first wafer substrate, the first interconnect, the first bonding layer, the second wafer substrate, the second interconnect, the second bonding layer, the third wafer substrate, the third interconnect, the third bonding layer, the carrier, and the redistribution circuitry to form a semiconductor device having a stacked structure including the first semiconductor die, the second semiconductor die, the third semiconductor die, the redistribution circuitry, the plurality of conductive terminals, and the carrier.In some embodiments, in the method, prior to forming the redistributed circuit structure on the first wafer substrate, the method further includes: forming a first bonding layer on the first interconnect; providing a circuit wafer including a second wafer substrate having at least one second active component and a second interconnect disposed on the second wafer substrate; bonding the second wafer substrate to the first bonding layer via wafer-on-wafer bonding; forming a second bonding layer on the second interconnect; providing an additional circuit wafer including a third wafer substrate having at least one third active component and a third interconnect disposed on the third wafer substrate; bonding the third wafer substrate to the second bonding layer via wafer-on-wafer bonding; providing at least one through-hole penetrating the additional circuit wafer and the circuit wafer; performing a first dicing process to cut through the first wafer substrate, the first interconnect, the first bonding layer, the second wafer substrate, the second interconnect, the second bonding layer, and the third wafer substrate. The method comprises: forming a first stacked structure having a first semiconductor die, a second semiconductor die, and a third semiconductor die, and encapsulating the first stacked structure in an insulating encapsulation, wherein forming the redistribution structure on the first wafer substrate includes forming the redistribution structure on the insulating encapsulation and the first semiconductor die exposed by the insulating encapsulation, wherein before performing the dicing process and after setting the plurality of conductive terminals, the method further comprises: forming a third bonding layer on the insulating encapsulation, the third semiconductor die exposed by the insulating encapsulation, and the at least one via; and bonding the carrier to the third bonding layer through wafer-on-wafer bonding, wherein performing the dicing process includes performing a second dicing process to cut through the carrier, the third bonding layer, the insulating encapsulation, and the redistribution structure to form a semiconductor device having a second stacked structure including the first stacked structure, the insulating encapsulation, the redistribution structure, the plurality of conductive terminals, and the carrier.In some embodiments, in the method, prior to forming the redistributed circuit structure on the first wafer substrate, the method further includes: forming a first bonding layer on the first interconnect; providing a circuit wafer including a second wafer substrate having at least one second active component and a second interconnect disposed on the second wafer substrate; bonding the second wafer substrate to the first bonding layer via wafer-to-die bonding; forming a second bonding layer on the second interconnect; performing a first dicing process to cut through the first wafer substrate, the first interconnect, the first bonding layer, the second wafer substrate, the second interconnect, and the second bonding layer to form a first stacked structure having a first semiconductor die and a second semiconductor die; providing an additional circuit wafer including a third wafer substrate having at least one third active component and a third interconnect disposed on the third wafer substrate; bonding the second bonding layer of the first stacked structure to the third wafer substrate via chip-to-die bonding; encapsulating the first stacked structure in a first insulating encapsulation; providing at least one through-hole penetrating the additional circuit wafer and the first interconnect. The method includes: performing a second dicing process to cut through the first insulating encapsulation, the third wafer substrate, and the third interconnect to form a second stacked structure having the first stacked structure, the first insulating encapsulation, and the third semiconductor die; and encapsulating the second stacked structure within the second insulating encapsulation, wherein forming the redistribution structure on the first wafer substrate includes forming the redistribution structure on the second insulating encapsulation and the first semiconductor die exposed by the second insulating encapsulation, wherein before performing the dicing process and after setting the plurality of conductive terminals, the method further includes: forming a third bonding layer on the second insulating encapsulation, the third semiconductor die exposed by the second insulating encapsulation, and the at least one via; and bonding a carrier to the third bonding layer through wafer-on-wafer bonding, wherein performing the dicing process includes performing a third dicing process to cut through the carrier, the third bonding layer, the second insulating encapsulation, and the redistribution structure to form the semiconductor device having a third stacked structure including the second stacked structure, the second insulating encapsulation, the redistribution structure, the plurality of conductive terminals, and the carrier.In some embodiments, in the method, prior to forming the redistribution structure on the first wafer substrate, the method further includes: forming a first bonding layer on the first interconnect; performing a first dicing process to cut through the first wafer substrate, the first interconnect, and the first bonding layer to form a first stacked structure having the first semiconductor die; providing a circuit wafer including a second wafer substrate having at least one second active component and a second interconnect disposed on the second wafer substrate; bonding the first bonding layer of the first stacked structure to the second wafer substrate via chip-on-die bonding; encapsulating the first stacked structure in a first insulating encapsulation; forming a second bonding layer on the second interconnect; performing a second dicing process to cut through the first insulating encapsulation, the second wafer substrate, the second interconnect, and the second bonding layer to form a second stacked structure having the first stacked structure, the first insulating encapsulation, and the second semiconductor die; providing an additional circuit wafer including a third wafer substrate having at least one third active component and a third interconnect disposed on the third wafer substrate; bonding the second bonding layer of the second stacked structure to the third wafer substrate via chip-on-die bonding; encapsulating the second stacked structure in a first insulating encapsulation; forming a second bonding layer on the second interconnect; performing a second dicing process to cut through the first insulating encapsulation, the second wafer substrate, the second interconnect, and the second bonding layer to form a second stacked structure having the first stacked structure, the first insulating encapsulation, and the second semiconductor die; providing an additional circuit wafer including a third wafer substrate having at least one third active component and a third interconnect disposed on the third wafer substrate; bonding the second bonding layer of the second stacked structure to the third wafer substrate via chip-on-die bonding; encapsulating the second stacked structure in a first insulating encapsulation; forming a second bonding layer on the second interconnect; performing a second bonding layer on the second interconnect; performing a second bonding layer on the second stacked structure to the third wafer substrate; performing a second bonding layer on the second stacked structure... Encapsulated in a second insulating enclosure; at least one through-hole is provided, the at least one through-hole penetrating the additional circuit wafer and the second semiconductor die; a third dicing process is performed to cut through the second insulating enclosure, the third wafer substrate, and the third interconnect, thereby forming a third stacked structure having the second stacked structure, the second insulating enclosure, and the third semiconductor die; and the third stacked structure is encapsulated in the third insulating enclosure, wherein forming the redistributed circuit structure on the first wafer substrate includes forming the redistributed circuit structure on the third insulating enclosure and the first semiconductor die exposed by the third insulating enclosure, wherein during the execution Before the dicing process and after the plurality of conductive terminals are formed, the method further includes: forming a third bonding layer over the third insulating encapsulation, the third semiconductor die exposed by the third insulating encapsulation, and the at least one via; and bonding a carrier to the third bonding layer through wafer-on-wafer bonding, wherein performing the dicing process includes performing a fourth dicing process to cut through the carrier, the third bonding layer, the third insulating encapsulation, and the redistribution structure to form the semiconductor device having a fourth stacked structure including the third stacked structure, the third insulating encapsulation, the redistribution structure, the plurality of conductive terminals, and the carrier.In some embodiments, in the method, prior to forming the redistributed circuit structure on the first wafer substrate, the method further includes: forming a first bonding layer on the first interconnect; performing a first dicing process to cut through the first wafer substrate, the first interconnect, and the first bonding layer to form a first stacked structure having the first semiconductor die; providing a circuit wafer including a second wafer substrate having at least one second active component and a second interconnect disposed on the second wafer substrate; bonding the first bonding layer of the first stacked structure to the second wafer substrate via on-chip die bonding; and bonding the first interconnect of the first stacked structure to the second wafer substrate via on-chip die bonding. A stacked structure is encapsulated in a first insulating enclosure; a second bonding layer is formed on the second interconnect; an additional circuit die is provided, the additional circuit die including a third wafer substrate having at least one third active component and a third interconnect disposed on the third wafer substrate; a second dicing process is performed to cut through the third wafer substrate, the third interconnect, and the third bonding layer to form a second stacked structure having a third semiconductor die; the third wafer substrate is bonded to the second bonding layer through on-chip die bonding; the second stacked structure is encapsulated in a second insulating enclosure; at least one through-hole is provided, the at least one through-hole penetrating the third... A semiconductor die; performing a third dicing process to cut through the second insulating encapsulation, the second wafer substrate, the second interconnect, the second bonding layer, and the first insulating encapsulation to form a third stacked structure having a second stacked structure, the second insulating encapsulation, the second semiconductor die, the first stacked structure, and the first insulating encapsulation; and encapsulating the third stacked structure within the third insulating encapsulation, wherein forming the redistributed circuit structure on the first wafer substrate includes forming the redistributed circuit structure on the third insulating encapsulation and on the first semiconductor die exposed by the third insulating encapsulation, wherein during the dicing process... Before the dicing process and after the plurality of conductive terminals are formed, the method further includes: forming a third bonding layer over the third insulating encapsulation, the third semiconductor die exposed by the third insulating encapsulation, and the at least one through-hole; and bonding a carrier to the third bonding layer through wafer-on-wafer bonding, wherein performing the dicing process includes performing a fourth dicing process to cut through the carrier, the third bonding layer, the third insulating encapsulation, and the redistribution structure to form the semiconductor device having a fourth stacked structure including the third stacked structure, the third insulating encapsulation, the redistribution structure, the plurality of conductive terminals, and the carrier.In some embodiments, in the method, prior to forming the redistributed circuit structure on the first wafer substrate, the method further includes: forming a first bonding layer on the first interconnect; providing a circuit wafer including a second wafer substrate having at least one second active component and a second interconnect disposed on the second wafer substrate; bonding the second wafer substrate to the first bonding layer via wafer-on-die bonding; forming a second bonding layer on the second interconnect; providing an additional circuit wafer including a third wafer substrate having at least one third active component and a third interconnect disposed on the third wafer substrate; performing a first dicing process to cut through the third wafer substrate, the third interconnect, and the third bonding layer to form a first stacked structure having a third semiconductor die; bonding the third wafer substrate to the second bonding layer via chip-on-die bonding; encapsulating the first stacked structure in a first insulating encapsulation; providing at least one through-hole penetrating the third semiconductor die; performing a second dicing process to cut through the first insulating encapsulation, the second wafer substrate, the second interconnect, and the second interconnect. The method comprises: a bonding layer, a first wafer substrate, a first interconnect, and the first bonding layer, to form a second stacked structure having a first stacked structure, a first insulating encapsulation, a second semiconductor die, and the first semiconductor die; and encapsulating the second stacked structure within a second insulating encapsulation, wherein forming the redistribution structure on the first wafer substrate includes forming the redistribution structure on the second insulating encapsulation and the first semiconductor die exposed by the second insulating encapsulation, wherein before performing the dicing process and after setting the plurality of conductive terminals, the method further comprises: forming a third bonding layer on the second insulating encapsulation, the third semiconductor die exposed by the second insulating encapsulation, and the at least one via; and bonding a carrier to the third bonding layer through wafer-on-wafer bonding, wherein performing the dicing process includes performing a third dicing process to cut through the carrier, the third bonding layer, the second insulating encapsulation, and the redistribution structure to form a semiconductor device having a third stacked structure having the second stacked structure, the second insulating encapsulation, the redistribution structure, the plurality of conductive terminals, and the carrier.

[0193] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this utility model, and are not intended to limit it. Although the utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this utility model.

Claims

1. A semiconductor device, characterized in that, include: Semiconductor dies, including: The substrate includes at least one active component; Internal interconnects are disposed on the at least one active component and electrically coupled to the at least one active component; and At least one first thermal control component is disposed inside the interconnect and thermally coupled to the at least one active component, wherein the at least one active component is surrounded by the at least one first thermal control component in a vertical projection along the stacking direction of the substrate and the interconnect.

2. The semiconductor device according to claim 1, characterized in that, The at least one first thermal control component comprises a plurality of first thermal control components arranged in a matrix, the matrix having openings. In the vertical projection, the at least one active component is surrounded by the plurality of first thermal control components arranged in the matrix, and the opening overlaps with the at least one active component.

3. The semiconductor device according to claim 1, characterized in that, The at least one first thermal control component comprises a first thermal control component in the form of a block material with an internal opening or a first thermal control component in the form of a plate material with an internal opening. In the vertical projection, the at least one active component is surrounded by the first thermal control component, and the opening overlaps with the at least one active component.

4. The semiconductor device according to claim 1, characterized in that, The semiconductor die further includes a second thermal control assembly in the form of a continuous substrate, and the interconnect is disposed between the second thermal control assembly and the substrate. In the vertical projection, the at least one active component overlaps with the second thermal control component.

5. The semiconductor device according to claim 1, characterized in that, The at least one active component is separated from the at least one first thermal control component through the dielectric layer of the interconnect, and the thermal conductivity of the at least one first thermal control component is greater than the thermal conductivity of the dielectric layer of the interconnect. The at least one first thermal control component comprises a solid-solid phase change material.

6. A semiconductor device, characterized in that, include: Re-layout of the wiring structure; A first die, disposed on and electrically coupled to the redistribution structure, and comprising: A first substrate includes at least one first active component; A first internal interconnect is disposed on and electrically coupled to the at least one first active component; and At least one first thermal control component is disposed inside the first interconnect and thermally coupled to the at least one first active component, wherein the at least one first active component is surrounded by the at least one first thermal control component in a vertical projection. The second die, disposed on the redistribution structure and electrically coupled to the redistribution structure, includes: The second substrate includes at least one second active component; and A second internal connection is disposed on the at least one second active component and electrically coupled to the at least one second active component; and At least one perforation is disposed on the redistribution structure and electrically coupled to the redistribution structure, and electrically coupled to the first die and the second die.

7. The semiconductor device according to claim 6, characterized in that, The second die further includes: At least one second thermal control component is disposed inside the second interconnect and thermally coupled to the at least one second active component, wherein the at least one second active component is surrounded by the at least one second thermal control component in the vertical projection.

8. The semiconductor device according to claim 6, characterized in that, Including: A carrier is disposed on the redistribution structure, wherein the first core, the second core and the at least one perforation are disposed between the carrier and the redistribution structure; A heat dissipation module is disposed on the carrier and thermally coupled to the carrier, wherein the carrier is disposed between the heat dissipation module and the redistribution circuit structure; as well as Multiple conductive terminals are disposed on the redistribution circuit structure and electrically coupled to the redistribution circuit structure, wherein the redistribution circuit structure is disposed between the carrier and the multiple conductive terminals.

9. The semiconductor device according to claim 6, characterized in that, Including: The third die, disposed on the redistribution structure and electrically coupled to the redistribution structure, includes: A third substrate, including at least one third active component; and A third internal connection is disposed on the at least one third active component and electrically coupled to the at least one third active component. The at least one of the perforations further penetrates the third die.

10. The semiconductor device according to claim 9, characterized in that, The third die further includes: At least one third thermal control component is disposed inside the third interconnect and thermally coupled to the at least one third active component, wherein the at least one third active component is surrounded by the at least one third thermal control component in the vertical projection.

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