Computing device

Abstract

The utility model relates to the technical field of computers, in particular to a computing device which comprises a memory slot, a controller and a BMC, the memory slot is used for inserting a memory bank, the controller is provided with a connecting port, and the connecting port is correspondingly connected with a target pin of the memory slot; the controller is used for determining first internal existence bit information according to a level signal of the connection port; and the BMC is used for reading the first memory bit information from the controller. According to the computing equipment, after a memory bank is correctly inserted into a memory slot, a level signal of a connection port connected with a target pin of the memory slot is changed; and then, according to a level signal of the connection port, obtaining first memory bit information, so that the BMC can realize memory bit identification detection without using a basic input / output system (BIOS).

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer, and particularly relates to a computing device. BACKGROUND

[0002] Memory is a storage medium for temporarily storing data and programs in a computing device, allowing the computing device to quickly read and write data, and is a key part of ensuring efficient operation of the computing device. Memory is usually taken as a physical carrier in the form of a memory stick and is installed in a memory slot of a mainboard of the computing device. However, during daily use of the computing device, abnormal insertion and reading of the memory stick may occur.

[0003] At present, memory reading is usually reported to a baseboard management controller (BMC) by a basic input / output system (BIOS) after initialization of the BIOS is completed. If the BIOS fails to correctly complete initialization due to abnormal startup, the BMC cannot obtain memory slot in-place information. CONTENT OF THE UTILITY MODEL

[0004] To solve the above problem, the embodiments of the present application provide a computing device, and the BMC does not need to depend on the BIOS and can directly obtain memory slot in-place information through a programmable logic device.

[0005] The computing device provided by the embodiments of the present application comprises a memory slot, a controller and a baseboard management controller (BMC), the memory slot is used for inserting a memory stick, and the controller and the BMC are used for obtaining memory slot in-place information.

[0006] A connection port is arranged on the controller, the connection port is connected with a target pin of the memory slot in correspondence, and the controller is used for determining first memory slot in-place information according to a level signal of the connection port.

[0007] The BMC is used for reading the first memory slot in-place information from the controller.

[0008] In the computing device, a target pin of a memory slot is electrically connected with a connection port of the controller; after a corresponding memory stick is correctly inserted into a memory slot, a level signal of the connection port electrically connected with the target pin of the memory slot changes. That is, whether a memory stick is correctly inserted into a memory slot will directly cause the connection port electrically connected with the target pin of the memory slot to have different level signals, so the level signal of a connection port can be used to assist in determining whether a memory stick is correctly inserted into the memory slot connected by the connection port. Based on this, the controller can know whether a memory stick is correctly inserted or not correctly inserted in one or more memory slots connected by one or more connection ports of the controller according to the level signals of the one or more connection ports, that is, obtain the memory bit information of the one or more memory slots; and then, the BMC can obtain the memory bit information from the controller, and whether the BIOS completes initialization will no longer affect whether the BMC can obtain the memory bit information.

[0009] In a possible implementation, the target pin is a ground pin (gnd pin), and the level signal of the connection port indicates that the memory stick is correctly inserted into the memory slot connected by the connection port when the level signal of the connection port is in a low level state. In this implementation, the target pin of the memory slot is a ground pin; after the memory stick is correctly inserted into the memory slot, a current channel is formed between the target pin of the memory slot and the connection port connected with the target pin. Since the ground pin of the memory slot is connected to a ground wire, the ground wire provides a path with a low level signal for the connection port, so that the level at the connection port tends to be consistent with the ground potential, thereby the level at the connection port decreases, and the level signal of the connection port indicates that the memory stick is correctly inserted into the memory slot connected by the connection port.

[0010] In a possible implementation, the computing device includes a plurality of memory slots for inserting a plurality of memory sticks; wherein the controller is further configured to determine a first number of memory sticks correctly inserted into the memory slots according to the first memory bit information of the plurality of memory slots; and the BMC is further configured to read the first number from the controller. In this implementation, the controller can obtain the number of memory sticks correctly inserted into the memory slots by the number of connection ports with changed level signals; and thus, the BMC can read the number of memory sticks correctly inserted into the memory slots from the controller.

[0011] In a possible implementation, the computing device includes a plurality of memory slots for inserting a plurality of memory sticks; wherein the controller is further configured to determine, according to the first memory bit information of each of the plurality of memory slots, a first quantity of memory sticks that are not correctly inserted into the memory slots; and the BMC is further configured to read the first quantity from the controller. In this implementation, the controller can obtain the quantity of memory sticks that are not correctly inserted into the memory slots by the number of connection ports in which the level signal does not change, and thus the BMC can read the quantity of memory sticks that are not correctly inserted into the memory slots from the controller.

[0012] In a possible implementation, the BMC is further configured to compare the first memory bit information with second memory bit information obtained in advance, and provide first alarm information indicating that the memory sticks are not correctly inserted when a comparison result does not satisfy a first preset condition.

[0013] In this implementation, the second memory bit information may, for example, indicate that the memory sticks should be correctly inserted into the memory slots in theory, or indicate that the memory sticks are not correctly inserted into the memory slots, and thus the BMC can determine whether there is a memory stick that should be correctly inserted into the memory slots but is not correctly inserted into the memory slots by judging whether the comparison result satisfies the first preset condition, and if not, the first alarm information can be reported to a system administrator or an operation and maintenance personnel in a system log, an email notification or the like, so as to facilitate maintenance or adjustment.

[0014] In a possible implementation, the computing device further includes a BIOS chip electrically connected to the BMC; wherein the BIOS chip is electrically connected to the one or more memory slots and configured to obtain third memory bit information; and the BMC is further configured to obtain the third memory bit information from the BIOS chip.

[0015] In this implementation, the BMC obtains the third memory bit information from the BIOS chip, which can be used to compare the first memory bit information with the third memory bit information; when the first memory bit information is the same as the third memory bit information, the first memory bit information and the third memory bit information can verify each other, thereby increasing the reliability of the third memory bit information.

[0016] In a more specific implementation, the BMC is further configured to compare the first memory bit information with the third memory bit information, and provide second alarm information indicating that the memory recognition of the BIOS chip is incorrect when a comparison result does not satisfy a second preset condition.

[0017] In a possible implementation, the BMC is connected with the BIOS chip through an Intelligent Platform Management Interface (IPMI), and obtains the third memory bit information from the BIOS.

[0018] In this implementation, the BMC can perform reliability verification on the third memory bit information according to the first memory bit information based on the third memory bit information obtained from the BIOS. When the third memory information fails to pass the reliability verification, that is, when the comparison result of the first memory information and the third memory information does not satisfy the second preset condition, second alarm information indicating a memory recognition error of the BIOS chip can be reported to a system administrator or an operation and maintenance personnel in a manner such as a system log, an email notification, or an SNMP, so as to facilitate maintenance or adjustment.

[0019] In this implementation, the IPMI connection is a standard management interface, and among a plurality of connection manners, the IPMI has a higher specification. In addition, the BMC and the BIOS chip are connected through the IPMI, so that the BMC can be free from the influence of an operating system, and stability and reliability of management and monitoring functions are ensured.

[0020] In a possible implementation, the BMC is further configured to obtain memory information from the memory bar after obtaining the first memory bit information.

[0021] In this implementation, after the BMC confirms that the memory bar is correctly inserted in the memory slot, the BMC can directly obtain the memory information from the memory bar that is correctly inserted in the memory slot, and whether the BIOS completes initialization no longer affects whether the BMC can obtain the memory information.

[0022] In a possible implementation, the memory information includes Serial Presence Detect (SPD) information, and the BMC is specifically configured to read the SPD information from an Electrically Erasable Programmable Read-Only Memory (EEPROM) included in the memory bar.

[0023] In this embodiment, the BMC can read the SPD information written in the EEPROM by the manufacturer, can help the system to identify and verify the memory bar installed in the system, so that the mainboard can correctly identify and automatically configure the timing parameters, frequency and voltage settings of the memory at startup, ensure the correct operation of the memory bar in the system and maximize the performance, and timely find the problems of the memory bar and take corresponding measures, improve the stability and reliability of the system. In a possible implementation, the BMC specifically connects with the programmable logic device through a serial bidirectional bus (Inter-Integrated Circuit, I2C), and reads the first memory bit information from the programmable logic device.

[0024] In this embodiment, the I2C hardware connection structure is simple, only two lines are needed, and the communication between the BMC and the programmable logic device can be realized; and the power consumption of I2C is low, and the communication between the BMC and the programmable logic device can be maintained for a long time, so that the detection of the memory bit information for a long time can be realized when the BIOS is not started. BRIEF DESCRIPTION OF DRAWINGS

[0025] Figure 1 The first schematic diagram of the computing device provided by the embodiment of the present application. DETAILED DESCRIPTION

[0026] The technical solutions in the embodiments of the present application will be described below with reference to the drawings. Obviously, the described embodiments are only part of the embodiments of the present application, not all the embodiments.

[0027] The memory is a storage medium for temporarily storing data and programs in the computing device, and is usually taken as a physical carrier by a memory bar. The memory bar is an important component of the computing device, and is an internal storage that can directly exchange data with the CPU. In the daily use of the computing device, the insertion and reading of the memory bar may be abnormal.

[0028] The embodiment of the present application provides a kind of computing device, in the computing device, the target pin of one memory slot is electrically connected with the connection port of a controller;After the corresponding memory stick is correctly inserted in one memory slot, the level signal of the connection port electrically connected with the target pin of the memory slot changes.That is to say, whether the memory stick is correctly inserted in one memory slot, it will directly lead to the connection port electrically connected with the target pin of the memory slot has different level signals, so the level signal of one connection port can be used to assist in determining whether the memory stick is correctly inserted in the memory slot connected with the connection port, and the level signal of one connection port can be used to assist in determining whether the memory stick is correctly inserted in the memory slot connected with the connection port.Based on this, the controller can determine the bit information of the memory of one or more memory slots connected by the corresponding memory slot according to the level signal of one or more connection ports included in the controller;Subsequently, BMC can obtain the bit information of the memory from the controller, and whether BIOS is completed initialization will no longer affect whether BMC can obtain the bit information of the memory.

[0029] In order to better understand the embodiments of the present application, some key terms are explained below.

[0030] Mainboard: The mainboard is a kind of circuit board in computing device, including substrate and CPU, memory slot, controller, BIOS chip etc. on the substrate. As the core component of computing device, the mainboard is connected with other components of computing device through the interface on the mainboard, such as adapter plate, backplane, fan and power supply, so that the computing device can effectively run and complete various tasks.

[0031] BMC: BMC is a kind of embedded system control chip, usually integrated in computing device, such as integrated in server or network device, used for monitoring, controlling, managing and maintaining the hardware and software of the whole computing device. BMC usually includes processor, memory, network interface, clock, I / O interface and other components, and runs an independent operating system. Through mutual cooperation with CPU and other components in computing device, BMC can realize diagnosis, performance monitoring, firmware update, power management, security management and other functions. BMC can also be used to support administrator to remotely manage computing device, so as to improve the reliability, availability and maintainability of computing device.

[0032] Controller: Controller is a kind of main hardware platform, which is configured and programmed by users through software to complete a certain specific function and can be repeatedly erased and written. When modifying and upgrading the controller, users do not need to change the printed circuit board additionally, but only need to modify and update the program on the computing device. The controller is usually composed of logic units, input / output pins (or called connection ports, I / O ports), clock management units and programming interfaces. The controller can realize various logic functions for control and processing in digital circuit design, such as logic gates, flip-flops, counters, etc.; it can also realize the timing control logic for processing timing-related signals and data; in addition, the controller can also realize the interface control between different devices, such as the communication interface between peripheral devices and the main processor. The controller can include but is not limited to programmable logic device (PLD), CPLD or FPGA, such as application-specific integrated circuit (ASIC) or microcontroller unit (MCU).

[0033] BIOS: BIOS is integrated in the BIOS chip on the motherboard of the computing device, and is the first software layer of the operating system startup in the computing device; when the operating system of the computing device is started, BIOS is responsible for initializing part of the hardware devices in the computing device, such as memory, hard disk, graphics card, network card, etc., to ensure that they can work normally. In addition, BIOS can perform self-checking to ensure that the computing device has no fault by checking the status and connectivity of the relevant hardware devices; and load the boot program on the computing device to start the loading process of the operating system.

[0034] Among them, the BIOS chip is a specific ROM chip used to store the BIOS program. The ROM chip is an entity chip, which is essentially a storage device, a small rectangular or square chip in the flash EEPROM memory strip on the motherboard, which can store the BIOS program. In addition, the ROM chip can also store other programs and codes.

[0035] Ground pin: Ground pin is also expressed as gnd pin, which is a pin connected to ground in hardware, used to provide a reference level for the circuit or as a path for the current loop. On the motherboard, the ground pin is usually used to connect to the ground wire or the ground layer of the motherboard to provide a stable ground connection; the level connected to the ground wire or the ground layer is usually defined as zero level, which is the reference point of voltage in the circuit, used to ensure the potential consistency between parts in the circuit.

[0036] Memory module: A memory module is a modular storage device composed of multiple memory chips with a specific total capacity and working frequency, used to store and provide data for fast access by the CPU. In use, the memory module is directly inserted into the memory slot on the motherboard of the computing device.

[0037] Memory chip: A memory chip is the core component of a memory module, serving as the basic unit for storing data. Memory chips are composed of transistors and capacitors and are used to store temporary data and programs. Memory chips include Double Data Rate Generation Synchronous Dynamic Random Access Memory (DDR), such as DDR4 or DDR5.

[0038] SPD information: SPD information includes metadata and parameter information about memory chips, such as the model, speed, capacity, timing, and other information specific to the memory controller. SPD information is usually pre-programmed by the manufacturer of the memory chip and stored on a small EEPROM, which is then assembled on the memory module. When the operating system starts, the BMC reads the SPD information of the memory chip from the EEPROM in various ways, allowing the computing device to configure the memory controller based on this information.

[0039] Next, the scheme of the computing device provided by the embodiments of the present application will be specifically introduced.

[0040] Figure 1 A schematic diagram of a computing device provided by an embodiment of the present application.

[0041] As Figure 1 shown, the computing device includes a controller for detecting bit information of the first memory, in addition to a BMC and one or more memory slots. The controller is provided with one or more connection ports, which are electrically connected to the target pins of the one or more memory slots. The CPLD disperses the logic module into multiple logic units, has high reconfigurability, low power consumption, stable performance, and other characteristics, and the controller can preferably use a CPLD.

[0042] In the embodiments of the present application, the main example is the electrical connection of different connection ports to different target pins of memory slots, and in this example, one connection port corresponds to one memory slot.

[0043] When a memory slot is not correctly inserted with a memory stick, the connection port connected with the target pin of the memory slot has a different level signal compared with the case that the memory slot is correctly inserted with a memory stick. Correspondingly, for a connection port in the controller, when it is electrically connected with the target port of a memory slot, the connection port can receive the level signal of the target port of the memory slot. When the memory slot is correctly inserted with a memory stick, the level signal received by the connection port can receive the level signal of the target port of the memory slot, so that the level signal of the connection port itself changes.

[0044] Taking the target pin of the memory slot as a ground pin as an example, when the memory slot is not correctly inserted with a memory stick, the connection port is in a high level state by default. When the memory slot is correctly inserted with a memory stick, a current channel is formed between the target pin of the memory slot and the connection port connected with the target pin. Since the ground pin of the memory slot is connected to the ground, the ground provides a path with a low level signal for the connection port, so that the level at the connection port tends to be consistent with the ground potential, thereby the level at the connection port is lowered, and the level signal at the connection port indicates that it is in a low level state.

[0045] In the above, the memory slot correctly inserted with a memory stick means that the pin of the memory stick is completely inserted into the memory slot, and the pin of the memory stick is electrically connected with the corresponding contact point in the memory slot.

[0046] It should be particularly noted that the target pin can also be a specific pin other than the ground pin, and it is only necessary to ensure whether the memory slot is correctly inserted with a memory stick, so that the connection port in the controller connected with the target pin of the memory slot has different level signals.

[0047] When the controller obtains the level signals of one or more connection ports included in the controller, the first memory presence bit information corresponding to each of the one or more memory slots can be determined. The first memory presence bit information corresponding to a single memory slot is used to indicate whether the memory slot is correctly inserted with a memory stick.

[0048] Taking the target pin of the memory slot as a ground pin as an example, when the level signal of the connection port connected with the memory slot is represented by a logic value, “0” is usually used to represent that the connection port is in a low level state, and “1” is used to represent that the connection port is in a high level state. When the controller finds that the level signal of a connection port is lowered, i.e., the connection port changes from a high level state to a low level state, the controller can determine that the memory slot corresponding to the connection port is correctly inserted with a memory stick. Furthermore, the first memory presence bit information obtained by the controller for the memory slot can also use the logic value “0” to represent that the memory slot is not correctly inserted with a memory stick, and use the logic value “1” to represent that the memory slot is correctly inserted with a memory stick.

[0049] When the computing device includes a plurality of memory slots for inserting a plurality of memory sticks, the controller can obtain the first memory bit information according to the plurality of level signals corresponding to the plurality of connection ports, and establish a memory bit mapping table for the plurality of memory slots according to the plurality of first memory bit information, and record the first memory bit information corresponding to the plurality of memory slots respectively.

[0050] According to the specific design needs, the controller can further determine the first number of memory slots in the plurality of memory slots that have correctly inserted or incorrectly inserted memory sticks according to the first memory bit information corresponding to the plurality of memory slots respectively, that is, determine the first number of memory slots that have correctly inserted or incorrectly inserted memory sticks. Specifically, the controller can calculate the number of memory slots that have incorrectly inserted memory sticks according to the total number of the plurality of memory slots and the number of one or more memory slots that have correctly inserted memory sticks.

[0051] Further, the BMC can read the first memory bit information from the controller. When the controller records the first memory bit information corresponding to the plurality of memory sticks respectively through the memory bit mapping table, the BMC can directly read the memory bit mapping table established by the controller from the controller.

[0052] When the BMC is in communication connection with the controller through the bus, the BMC can read the first memory bit information obtained by the controller through the bus. The bus usually includes a Controller Area Network (CAN), a Serial Peripheral Interface (SPI), an I2C, a Universal Asynchronous Receiver / Transmitter (UART) interface bus, etc. As the I2C hardware connection is simple, only two lines are needed for communication, and supports multiple slave devices, up to dozens of devices can be connected through address allocation, the power consumption of I2C is low, as a preferred mode, the BMC can be in communication connection with the controller through I2C, and read the first memory bit information obtained by the controller through I2C.

[0053] After reading the first memory bit information obtained by the controller, the BMC can cooperate with the management software in the computing device to report the first memory bit information or the memory bit mapping table from the controller to the system administrator or the operation and maintenance personnel through system log, email notification, Simple Network Management Protocol (SNMP) and the like.

[0054] In some embodiments, the BMC is further configured to compare the first memory presence bit information with pre-obtained second memory presence bit information, and provide first alarm information indicating that the memory bank is not correctly inserted when a comparison result does not satisfy a first preset condition. For example, the first alarm information indicating that the memory bank is not correctly inserted can be reported to a system administrator or an operation and maintenance personnel in a manner of system log, email notification, SNMP, etc., so as to facilitate maintenance or adjustment.

[0055] Similar to the expression manner of the first memory presence bit information, the second memory presence bit information can be used to indicate whether a memory bank corresponding to the memory slot is expected to be correctly inserted. In other words, when a memory bank corresponding to a memory slot is expected to be correctly inserted, a logical value "1" can be used to represent the second memory presence bit information corresponding to the memory slot; when a memory bank corresponding to a memory slot is not expected to be correctly inserted, a logical value "0" can be used to represent the second memory presence bit information corresponding to the memory slot.

[0056] The pre-obtained second memory presence bit information can be configured by a worker when assembling the computing device, or can be the memory presence bit information read by the BMC from the BIOS or the controller in the last round of startup of the computing device.

[0057] In a more specific example, the first preset condition can be, for example, that the first memory presence bit information and the second memory presence bit information corresponding to the same memory slot are the same. In this case, the BMC can compare, for example, the logical values representing the first memory presence bit information and the second memory presence bit information in the same memory slot in the memory presence bit mapping table including the first memory presence bit information and the memory presence bit mapping table including the second memory presence bit information, and provide the first alarm information indicating that the memory bank is not correctly inserted if the first memory presence bit information and the second memory presence bit information corresponding to any memory slot are different.

[0058] In another more specific example, the first preset condition can be, for example, that a first number of memory slots in which the memory bank is correctly inserted is the same as a second number of memory slots in which the memory bank is expected to be correctly inserted; or can be that a first number of memory slots in which the memory bank is not correctly inserted is the same as a second number of memory slots in which the memory bank is expected to be not correctly inserted.

[0059] Further, in some embodiments, the BMC can also directly compare the first number of memory slots in which the memory modules are correctly inserted, determined according to the first on-die information, with a second number of memory slots in which the memory modules are expected to be correctly inserted, determined according to the pre-obtained second on-die information, and provide the first warning information indicating that the memory modules are not correctly inserted when the first number is different from the second number. Alternatively, in other embodiments, the BMC can also directly compare the first number of memory slots in which the memory modules are not correctly inserted, determined according to the first on-die information, with a second number of memory slots in which the memory modules are expected to be not correctly inserted, determined according to the pre-obtained second on-die information, and provide the first warning information indicating that the memory modules are not correctly inserted when the first number is different from the second number.

[0060] Further, in some embodiments, the first warning information can further specifically indicate the first number of memory modules that are correctly or not correctly inserted into the one or more memory slots.

[0061] In some embodiments, the computing device further includes a BIOS chip electrically connected with the BMC and the one or more memory slots integrated on the motherboard, for obtaining third on-die information of the one or more memory slots. Correspondingly, the BMC is further configured to obtain the third on-die information from the BIOS chip.

[0062] After the BIOS is started, the BIOS performs memory detection, scans the memory slots in the computing device, and obtains the third on-die information. When the computing device includes a plurality of memory slots for inserting a plurality of memory modules, the BIOS can further determine a third number of memory slots in which the memory modules are correctly or not correctly inserted according to the third on-die information. Further, after the BIOS confirms that the memory modules have been correctly inserted into the memory slots according to the third on-die information, the BIOS can further read the SPD information of the memory chips on the memory modules from the memory modules, where the SPD information stores detailed information about the memory chips, such as capacity, speed, timing, etc. The BIOS can establish a memory mapping table according to the detected memory modules and the SPD information of the memory chips on the memory modules, record the condition of each memory slot and the parameter information of each memory module in the computing device, and enable the computing device to configure the memory controller according to the information.

[0063] The BMC can obtain the third memory presence bit information from the BIOS chip through a server management interface. After the BMC establishes a communication connection with the operating system of the computing device, the BMC sends a command to the operating system to obtain the third memory presence bit information. After the operating system of the computing device receives the command request, the BIOS returns the third memory presence bit information to the BMC. After the BMC receives the third memory presence bit information, the BMC analyzes and processes the third memory presence bit information for subsequent management and monitoring.

[0064] The server management interface can be a data center management interface (DCMI), a system management architecture for server hardware (SMASH), a web services for management (WS-MAN), an IPMI, or the like. The IPMI is a standard hardware management interface based on UDP and IP protocols, and is a set of hardware, firmware, and software specifications that can provide remote management and monitoring functions for computer system hardware, such as remote monitoring, rebooting, power management, and the like. In the present embodiment, the BIOS chip and the BMC can be connected using the IPMI because the IPMI has a high standardization specification.

[0065] In addition to the server management interface, the connection between the BMC and the BIOS chip can also be achieved through a bus similar to an intelligent platform management bus (IPMB) or a bus similar to a peripheral component interconnect (PCI) or a peripheral component interconnect express (PCIe), to achieve remote management, monitoring, and control functions.

[0066] In some more specific embodiments, the BMC is further configured to compare the first memory presence bit information with the third memory presence bit information, and when the comparison result does not satisfy the second preset condition, provide second alarm information indicating a memory recognition error of the BIOS chip. For example, the second alarm information indicating that the BIOS has not recognized a correctly inserted memory bank can be reported to a system administrator or an operation and maintenance personnel through a system log, an email notification, an SNMP, or the like, to facilitate maintenance or adjustment.

[0067] In a possible embodiment, the second preset condition can be that, for the same memory slot: the corresponding first memory slot bit information and the third memory slot bit information are the same. In this case, the BMC, for example, compares the logical values representing the first memory slot bit information and the third memory information in the two memory slot bit mapping tables for the same memory slot according to the memory slot bit mapping table including the first memory slot bit information and the memory slot bit mapping table including the third memory slot bit information. If the first memory slot bit information and the third memory slot bit information of any one memory slot are different, the second alarm information is provided.

[0068] In another more specific example, the second preset condition can be, for example, that the first number of memory slots with correctly inserted memory modules is the same as the third number of memory slots with correctly inserted memory modules; or can be that the first number of memory slots with incorrectly inserted memory modules is the same as the third number of memory slots with incorrectly inserted memory modules.

[0069] Further, in some embodiments, the BMC can also directly compare the first number of memory slots with correctly inserted memory modules determined according to the first memory slot bit information and the third number of memory slots with correctly inserted memory modules determined according to the third memory slot bit information. When the first number and the third number are different, the second alarm information is provided. Or, in other embodiments, the BMC can also directly compare the first number of memory slots with incorrectly inserted memory modules determined according to the first memory slot bit information and the third number of memory slots with incorrectly inserted memory modules determined according to the third memory slot bit information. When the first number and the third number are different, the second alarm information is provided.

[0070] In some possible embodiments, to avoid BIOS startup failure and thus the inability to obtain the memory information of the memory module, the BMC can also be used to, after confirming that the corresponding memory slot has correctly inserted the memory module according to the first memory slot bit information, connect to the memory module in the memory slot through the bus and obtain the memory information of the memory module from the memory module, the memory information including the manufacturing information, capacity, speed, type, usage, SPD information, etc. of the memory module; in addition, in some more specific embodiments, the BMC is specifically used to read the SPD information from the EEPROM included in the memory module.

[0071] The BMC establishes a connection with the EEPROM of the memory module through a hardware bus such as I2C; then, the BMC locates the specific address range of the EEPROM storing the SPD information, reads the SPD information in the EEPROM, and then parses these data to extract the detailed information of the memory module; the raw data read by the BMC is in binary format, and the data needs to be parsed according to the SPD specification to be converted into a readable form.

[0072] In addition, it should be noted that the BMC can also set an access interface to provide a management interface or API to allow a system administrator to remotely access the SPD information. The administrator can use the management software or command line tools of the BMC to view the detailed information of the memory stick.

[0073] In some more specific embodiments, the BMC is further configured to compare the first SPD information and the second SPD information, the first SPD information comprising the SPD information obtained by the BMC from the EEPROM via the bus; and the second SPD information comprising the SPD information obtained by the BMC from the BIOS chip. When the comparison result does not satisfy a third preset condition, the BMC provides third alarm information indicating a memory recognition error of the BIOS chip or a memory recognition error of the BMC. Similar to the above, the BMC can report the third alarm information to the system administrator or the operation and maintenance personnel through system logs, email notifications, SNMP, etc.

[0074] In some embodiments, the BMC can obtain a first total memory information of the plurality of memory sticks according to the first number and the first SPD information, and a second total memory information of the plurality of memory sticks according to the third number and the second SPD information. Then, the BMC can compare the first total memory information and the second total memory information, and when the comparison result does not satisfy a third preset condition, the BMC provides second alarm information indicating that a memory stick is not correctly inserted.

[0075] In the above example, the third preset condition can be that the first total memory capacity of the plurality of memory sticks is equal to the second total memory capacity. Specifically, in the first number obtained by the BMC, the number of memory sticks correctly inserted into the memory slot is 4, and the first SPD information indicates that the memory capacity of each memory stick is 8G, so the first total memory capacity is 32GB of memory; and in the third number obtained by the BIOS, the number of memory sticks correctly inserted into the memory slot is 3, and the second SPD information indicates that the memory capacity of each memory stick is 8G, so the second total memory capacity is 24GB; the BMC compares the memory capacities 32GB and 24GB, and then obtains the third alarm information, which is used to indicate that the BIOS chip recognizes one less memory stick or the BMC memory recognizes one more memory stick.

[0076] The foregoing mainly takes one memory slot supporting correct insertion of one memory stick as an example for exemplary description. In some technical scenarios, it is not excluded that one memory slot supports correct insertion of multiple memory sticks. In this case, the first memory status information can not correctly determine the number of memory sticks that are correctly inserted or not correctly inserted into one or more memory slots. However, because the level signal change of the connection port of the controller and the target pin of the corresponding connected memory slot is consistent, the first memory status information can still be used to determine the number of memory slots that correctly or incorrectly insert memory sticks. In this case, the status of the memory in one or more memory slots can also be reflected to some extent. For example, the number of one or more memory slots is A, the first memory status information can determine the number of memory slots that correctly insert memory sticks is B, and if B is less than A, it indicates that there is a memory slot that does not correctly insert a memory stick.

[0077] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the protection scope of the technical solutions of the embodiments of the present application.

Claims

1. A computing device, comprising: The memory slot is used for inserting a memory stick, and the BMC is electrically connected to the controller. The controller is provided with a connection port corresponding to a target pin of the memory slot; the target pin is a ground pin; when the potential signal of the connection port is low, it indicates that the memory stick has been correctly inserted into the memory slot corresponding to the connection port; The controller is configured to determine first memory presence information of the memory slot according to the level signal of the connection port; and the BMC is configured to read the first memory presence information from the controller.

2. The computing device of claim 1, wherein, The computing device includes a plurality of memory slots for inserting a plurality of memory sticks; wherein the controller is further configured to determine a first number of memory sticks that are correctly inserted or not correctly inserted into the memory slots according to the first memory presence information of each of the plurality of memory slots. The BMC is further configured to read the first number from the controller.

3. The apparatus of claim 1, wherein, The BMC is further configured to compare the first memory presence information with second memory presence information obtained in advance, and provide first alarm information indicating that the memory stick is not correctly inserted when the comparison result does not satisfy a first preset condition.

4. The apparatus of claim 1, wherein, The computing device further includes a basic input / output system (BIOS) chip electrically connected to the BMC and the memory slot, and configured to obtain third memory presence information. The BMC is further configured to obtain the third memory presence information from the BIOS chip.

5. The apparatus of claim 4, wherein, The BMC is further configured to compare the first memory presence information with the third memory presence information, and provide second alarm information indicating that the memory recognition of the BIOS chip is incorrect when the comparison result does not satisfy a second preset condition.

6. The apparatus of claim 4 wherein, The BMC is specifically connected to the BIOS chip through an intelligent platform management interface (IPMI).

7. The apparatus of claim 1, wherein The BMC is further configured to obtain memory information from the memory stick after confirming that the memory stick has been correctly inserted into the memory slot according to the first memory presence information.

8. The apparatus of claim 7, wherein, The memory information includes serial presence detect (SPD) information; and the BMC is specifically configured to read the SPD information from an electrically erasable programmable read-only memory (EEPROM) included in the memory stick.

9. The apparatus of any one of claims 1-8, wherein, The BMC is connected to the controller through a serial bidirectional bus.

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