Memory device and chip

Abstract

The utility model discloses a storage device and a chip, the storage device comprises a storage packaging module and a test logic module corresponding to the storage packaging module, the storage packaging module comprises a plurality of memory modules corresponding to a target memory, the test logic module is respectively connected with a plurality of memory modules in the storage packaging module through a group of test buses; the test logic module is also connected with the storage packaging module through at least one extended address line, and the at least one extended address line is used for selecting a memory module in the storage packaging module; wherein one group of test buses comprises at least one test address line and at least one test data line, the number of the test address lines is equal to the address bit width of the memory module, and the number of the test data lines is equal to the data bit width of the memory module. Therefore, the waste of logic resources of the large-bit-width memory can be avoided, and meanwhile, the winding pressure in a layout and wiring stage can be reduced.

Description

TECHNICAL FIELD

[0001] The utility model relates to chip design technical field especially, relates to a kind of storage device and chip. BACKGROUND

[0002] With the improvement of chip design performance, parallel data bus of large bit width is more and more common in chip design, which also means that large bit width memory is needed to cache bus data.However, due to the physical production size specification of memory, it is difficult for a general memory compiler to generate a complete large bit width memory.Therefore, designers usually need to generate multiple independent small bit width modules to splice bit width, so as to splice a large bit width memory required.

[0003] In the related art, the larger the bit width of the target memory, the more the number of splicing required. Thus, for the logical design scheme of splitting a large bit width memory into multiple small bit width modules participating in splicing, not only does it lead to an increase in the number of logical interface buses, causing a waste of logical resources, but also makes the design of layout and routing complex, increasing the wire routing pressure. SUMMARY

[0004] The utility model provides a kind of storage device and chip, can solve the resource waste problem of large bit width memory formed by the bit width splicing of multiple small bit width memories in the testable circuit design of large bit width memory, and the wire routing difficult problem introduced in the layout and routing stage of back-end physical design in the test logic of large bit width memory too much, to improve the feasibility of the testable circuit physical implementation of large bit width memory.

[0005] The technical solution of the utility model is as follows:

[0006] In a first aspect, the utility model embodiment provides a kind of storage device, the storage device includes storage package module and the test logic module corresponding with storage package module, wherein:

[0007] The storage package module includes multiple memory modules corresponding to the target memory, and the test logic module is connected with the multiple memory modules in the storage package module by a group of test buses respectively;

[0008] The test logic module is also connected with the storage package module by at least one extension address line, and at least one extension address line is used to select memory module in the storage package module;

[0009] Wherein, a group of test buses includes at least one test address line and at least one test data line, and the number of test address lines is equal to the address bit width of memory module, and the number of test data lines is equal to the data bit width of memory module.

[0010] In some embodiments, the test address bit width of the storage package module is equal to the sum of the address bit width of the memory module and the extension bit width corresponding to the at least one extension address line; the test data bit width of the storage package module is equal to the data bit width of the memory module; wherein the address bit width of the memory module is equal to the logarithm value of the depth of the memory module with base 2, and the depth of the memory module is equal to the depth of the target memory, and the data bit width of the memory module is equal to 1 / N times the width of the target memory, N representing the number of the plurality of memory modules.

[0011] In some embodiments, the storage device further comprises a plurality of timing registers, wherein: the timing registers are correspondingly arranged between each interface of the test logic module and the storage package module, and the number of the timing registers is equal to the sum of 2, the test address bit width of the storage package module, and the test data bit width of the storage package module.

[0012] In some embodiments, the storage package module further comprises a first decoding module, wherein: the enable end of the first decoding module is used to receive a chip selection enable signal; the input end of the first decoding module is connected with the at least one extension address line, the output end of the first decoding module is used to output a plurality of read-write control signals, and the plurality of read-write control signals have a one-to-one correspondence relationship with the plurality of memory modules.

[0013] In some embodiments, the storage package module further comprises a plurality of first selection modules, and the output end of the first selection module is correspondingly connected with the read-write enable port of the memory module; wherein: the first input end of the first selection module is used to receive a read-write control signal, the second input end of the first selection module is used to receive a first read-write enable signal, and the output end of the first selection module is used to output a second read-write enable signal to the memory module.

[0014] In some embodiments, the test data line comprises a read test data line, and the storage package module further comprises a second decoding module, wherein: the enable end of the second decoding module is used to receive a chip selection enable signal; the plurality of input ends of the second decoding module are one-to-one correspondingly connected with the read ports of the plurality of memory modules, and are used to receive the respective read data signals of the plurality of memory modules; the output end of the second decoding module is connected with the read port of the test logic module through the at least one read test data line, and is used to transmit the respective read data signals of the plurality of memory modules to the test logic module.

[0015] In some embodiments, the test data lines further include write test data lines, the memory package module further includes a plurality of second selection modules and a plurality of third selection modules, and the output ends of the second selection modules are connected to the write ports of the memory modules in correspondence, and the output ends of the third selection modules are connected to the address ports of the memory modules in correspondence; wherein: the enable ends of the second selection modules are configured to receive a test enable signal; the first input ends of the second selection modules are connected to the write ports of the test logic module through at least one write test data line, and are configured to receive a write data test signal; the second input ends of the second selection modules are configured to receive a write data function signal, and the output ends of the second selection modules are configured to output a target write data signal to the memory modules; the enable ends of the third selection modules are configured to receive the test enable signal; the first input ends of the third selection modules are connected to the address ports of the test logic module through at least one test address line, and are configured to receive a test address signal; the second input ends of the third selection modules are configured to receive a function address signal, and the output ends of the third selection modules are configured to output a target address signal to the memory modules.

[0016] In some embodiments, the memory module includes a plurality of memory blocks; in the case where the depth of the memory module is not equal to an integer power of 2, the size of the memory blocks satisfies the following two conditions: the size of the memory blocks is equal to an integer power of 2; and the size of the memory blocks is divisible by the depth of the memory module.

[0017] In some embodiments, the number of bits of the at least one extension address line is mapped between the xth bit and the x+yth bit corresponding to the at least one test address line; wherein x represents a logarithmic value of the size of the memory block with base 2, and y represents a value of the number of extension address lines minus 1.

[0018] In the second aspect, the embodiments of the utility model provide a chip, the chip includes the storage device as described in the first aspect.

[0019] The storage device and the chip provided by the embodiment of the utility model can split a target memory with large bit width into multiple memory modules for packaging design. BRIEF DESCRIPTION OF DRAWINGS

[0020] Figure 1 The component structure of the storage device provided by the embodiment of the utility model is shown Figure 1 ;

[0021] Figure 2 The component structure of the storage device provided by the embodiment of the utility model is shown Figure 1 ;

[0022] Figure 3 The component structure of the storage device provided by the embodiment of the utility model is shown Figure 2 ;

[0023] Figure 4 The component structure of the storage device provided by the embodiment of the utility model is shown Figure 3 ;

[0024] Figure 4 The component structure of the storage device provided by the embodiment of the utility model is shown Figure 6 ;

[0025] Figure 7 The logic address increment access sequence of the storage packaging module provided by the embodiment of the utility model is shown

[0026] Figure 8 A storage encapsulation module adjustment address sequence after logical address increment access order schematic diagram provided by the utility model embodiment;

[0027] Figure 2 A component structure diagram of a storage device provided by the related art Figure 9 ;

[0028] Figure 1 A component structure diagram of a chip provided by the utility model embodiment. DETAILED DESCRIPTION

[0029] In order to be able to more detailedly understand the characteristics and technical contents of the utility model embodiments, the implementation of the utility model embodiments is described in detail below in conjunction with the drawings, the drawings are only used for reference description, and are not used to limit the utility model embodiments.

[0030] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the utility model belongs. The terms used herein are only for the purpose of describing the utility model embodiments, and are not intended to limit the utility model.

[0031] In the following description, "some embodiments" are described, which describe a subset of all possible embodiments, but it can be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments, and can be combined with each other without conflict.

[0032] It should also be noted that the terms "first, second, third" involved in the utility model embodiments are only used to distinguish similar objects, and do not represent the specific order of the objects. Understandably, "first, second, third" can be interchanged with specific order or sequence as allowed, so that the utility model embodiments described here can be implemented in an order other than that illustrated or described here.

[0033] In order to facilitate the understanding of the technical scheme of the utility model embodiments, the related terms and related technologies of the utility model embodiments are described below. The following related technologies can be combined with the technical scheme of the utility model embodiments as optional schemes, and all belong to the protection scope of the utility model embodiments.

[0034] Design for Test (DFT), which is a key technology in the field of integrated circuits by implanting scan chains, boundary scan cells and other special structures in the chip design stage to improve the control and observation ability of internal signals. With the increasing complexity of chips, three methods of scan chain, built-in self-test, and boundary scan have gradually formed. The current DFT architecture can support multiple modes such as chip self-test and factory test, and can achieve high test coverage in the field of sensor chips and computing chips.

[0035] Memory Build-in Self-Test (MBIST), which is a testability design technology for integrated circuits, by implanting special test circuits in the chip, it realizes the self-detection function of the device, without the need for external test equipment to complete the memory function verification.

[0036] Static Random-Access Memory (SRAM), which is a type of random access memory. The so-called "static" means that as long as the power is kept on, the data stored in it can be constantly maintained. However, SRAM does not need to be refreshed, and the data stored in it will disappear in the case of shutdown or power failure.

[0037] Bank, which corresponds to a continuous SRAM storage space, by dividing independent addressing range to expand limited address space.

[0038] Function, unlike MBIST's testability design, it defines system functions as a series of sub-functions, and achieves the design goal through function splitting and integration. It belongs to a methodology for system development and design, aiming to ensure that the system can meet user needs and have high efficiency, reliability, scalability and other characteristics.

[0039] Memory compiler, which corresponds to the generation tool of different specifications of SRAM. By inputting specific parameters, the required generation file can be obtained.

[0040] Wrapper, which refers to a layer of custom logic encapsulation on the SRAM generated by the tool. Specifically, in chip design, it refers to adding a custom logic layer based on the SRAM generated by the tool, mainly used to realize specific functions (such as data verification, timing optimization, etc.), and hide the internal SRAM structure details.

[0041] With the performance of chip design improving, parallel data bus with large bit width is more and more common in chip design, which means that SRAM with large bit width is needed to cache bus data. However, due to the physical production size specification of SRAM, it is difficult for a general Memory compiler to generate a complete SRAM with large bit width. Therefore, designers usually need to generate N independent SRAMs with small bit width to splice the bit width, so as to splice a required SRAM with large bit width.

[0042] In the current general DFT design flow, the insertion of MBIST logic of SRAM is based on the single SRAM block generated by the Memory compiler. Among them, the MBIST logic design of a large bit width SRAM usually needs to be split into N independent small SRAM MBIST logic designs participating in splicing, which often causes waste of logic and interface resources, and increases the wire wrap pressure of the back-end layout and routing design.

[0043] That is, the current general process MBIST insertion logic of SRAM is generally automatically generated by an Electronic Design Automation (EDA) tool according to the output file of the Memory compiler, so in the current general design process, the corresponding number of SRAM MBISTWrappers is generated according to the number of spliced SRAMs. Each Wrapper needs to have independent MBIST control logic, and the back-end often needs to insert registers for timing patting of the interface signals of each Wrapper, thereby causing waste of logic resources and increasing the convergence difficulty of the back-end layout and routing.

[0044] Based on this, the utility model discloses a kind of storage device and chip, for the target memory with large bit width, it can be split into multiple memory modules to carry out packaging design. Among them, storage packaging module includes multiple memory modules, test logic module is connected with the multiple memory modules in storage packaging module respectively by a group of test buses;The group of test buses includes at least one test address line and at least one test data line;And test logic module is also connected with storage packaging module by at least one extension address line, and at least one extension address line is used to select memory module in storage packaging module. In this way, in the packaging design process to the multiple memory modules, these memory modules are selected by increasing extension address line, and these memory modules reuse same group of test buses, to realize that the data bit width of multiple memory modules is spliced and converted into depth splicing, so solve the resource waste problem when the testability circuit design of large bit width memory formed by multiple small bit width memories is spliced in bit width, and the winding difficulty problem of back-end physical design layout and wiring stage introduced by the test logic wiring of large bit width memory too much;In short, it can optimize the use of MBIST logic resource and greatly reduce the number of logic interface buses, while also can reduce the winding pressure of layout and wiring stage, and further improve the overall performance of the storage device.

[0045] The embodiments of the utility model will be described in detail below with reference to the drawings.

[0046] In an embodiment of the utility model, Figure 1 The composition structure of a storage device provided by the embodiments of the utility model is shown Figure 1 . As Figure 1 shown, the storage device 10 can include storage packaging module 101 and test logic module 102 corresponding to storage packaging module 101, wherein:

[0047] Storage packaging module 101 can include multiple memory modules (such as RM_1, RM_2, … RM_N), and test logic module 102 is connected with the multiple memory modules in storage packaging module 101 respectively by a group of test buses;Test logic module 102 is also connected with storage packaging module 101 by at least one extension address line, and at least one extension address line is used to select memory module in storage packaging module 101.

[0048] In the embodiments of the utility model, a group of test buses can include at least one test address line and at least one test data line, and the number of test address lines is related to the address bit width of the memory module, and the number of test data lines is related to the data bit width of the memory module.

[0049] It should be noted that the memory module in the embodiments of the present application can be a static random access memory, or simply referred to as "SRAM". When a small bit width SRAM cannot meet the design requirements (for example, a wider bit width is required to improve the data throughput rate), a target memory with a large bit width (i.e. a large bit width SRAM) is required at this time. However, for a large bit width SRAM, it is usually not possible to directly use Memory compiler to generate, so designers need to split it into multiple generatable memory modules for bit width splicing before use. Exemplarily, assuming that a target memory with a size of DEPTH*WIDTH needs to be obtained by bit width splicing of multiple memory modules with a size of DEPTH*SUB_WIDTH, then in the logic test process, the multiple memory modules can reuse the same set of test buses.

[0050] It should also be noted that the set of test buses can include at least one test address line and at least one test data line. As shown in Figure 1 m_addr represents a test address line, and the test data line can include a read test data line and a write test data line, wherein the read test data line can be represented by m_rdata, and the write test data line can be represented by m_wdata. It should be noted that for m_addr, m_rdata and m_wdata, Figure 1 one line is shown for illustrative purposes, but it does not mean that m_addr, m_rdata and m_wdata each have only one line. Here, the number of test address lines represented by m_addr can be multiple; similarly, the number of read test data lines represented by m_rdata can also be multiple, and the number of write test data lines represented by m_wdata can also be multiple.

[0051] In the embodiments of the present application, the number of test address lines is related to the address bit width of the memory module, and the address bit width of the memory module is related to the depth of the memory module, and the depth of the memory module is equal to the depth (DEPTH) of the target memory. Generally, the value of DEPTH is a power of 2, such as 2, 4, 8, 16, etc., which is convenient for hardware logic adaptation.

[0052] In a specific implementation, the number of test address lines is equal to the address bit width of the memory module, and the address bit width of the memory module is equal to the logarithmic value of the depth of the memory module with base 2. Exemplarily, the address bit width of the memory module is equal to log2(DEPTH), and correspondingly, the number of test address lines is log2(DEPTH) lines.

[0053] In the embodiment of the utility model, for the number of test data lines, it is related to the data bit width of the memory module, and the data bit width of the memory module is related to the width of the memory module, and the width of the memory module is equal to 1 / N times the width (WIDTH) of the target memory. Wherein, N represents the number of the plurality of memory modules, that is, the target memory can be split into N memory modules (such as RM_1, RM_2, … RM_N), and N is a positive integer. That is, WIDTH=N*SUB_WIDTH.

[0054] In the embodiment of the utility model, considering that bit width splicing is not needed when N is equal to 1, the value of N is usually a positive integer greater than 1. In addition, in some embodiments, the value of N is an integer power of 2, such as 2, 4, 8, 16, etc., which is convenient for hardware logic adaptation.

[0055] In a specific implementation, the number of test data lines is equal to the data bit width of the memory module, and the data bit width of the memory module is equal to the width of the memory module. Exemplarily, the data bit width of the memory module is equal to SUB_WIDTH, and correspondingly, the number of test data lines is SUB_WIDTH. In this way, by splicing the bit width of the plurality of memory modules, the data throughput rate can be improved.

[0056] That is, in the embodiment of the utility model, for the depth and width of the memory module, the depth represents the column direction capacity of the memory module, that is, the addressing range of the address line. The width represents the row direction data bit width of the memory module, that is, the number of data lines.

[0057] Exemplarily, if the depth is 512, 9-bit address lines (that is, 2 9 =512) are needed to define each column. For example, in a 512x1024 memory module, each column contains 512 storage units. If the width is 1024, it means that 1024 bits of data can be transmitted simultaneously in each read / write operation.

[0058] It can be understood that in the embodiment of the utility model, the extension address line here can be one or more. As Figure 2 shown, the extension address line can be represented by m_addr_ext. Wherein, Figure 1 only one extension address line is schematically shown, but it does not mean that m_addr_ext has only one line. Here, the number of extension address lines represented by m_addr_ext can be multiple.

[0059] In some embodiments, the number of extension address lines is related to the number of the plurality of memory modules.

[0060] In the embodiment of the utility model, the depth splicing can be through expanding address space, the storage depth is expanded from DEPTH to DEPTH*N, N represents the number of memory modules, namely the total number of addressable storage units is increased, and is applicable to the scene of increasing storage capacity.

[0061] In a possible implementation, the number of the extended address lines is log2(N), or in other words, the extended bit width corresponding to the extended address lines is log2(N).

[0062] Exemplarily, assuming that the depth of the memory module is 512 (corresponding to 9 bits of address lines), if N=2, namely two such memory modules are depth-spliced, the address lines are expanded to 10 bits, which can be used to distinguish 1024 storage units, and the increased extended address line is 1 bit. Or, if N=4, namely four such memory modules are depth-spliced, the address lines are expanded to 11 bits, which can be used to distinguish 2048 storage units, and the increased extended address line is 2 bits.

[0063] It should be noted that the increased extended address line is located at the highest bit of the address. In this way, different memory modules are distinguished through the extended address lines or the high bits of the address. Exemplarily, assuming that N=2, when the bit value of the extended address line is 0, the first memory module is selected, and when the bit value of the extended address line is 1, the second memory module is selected, so as to ensure that each memory module can be accessed individually during testing.

[0064] In this way, in the embodiment of the utility model, the storage capacity can be efficiently expanded through the increased extended address line, and the data bit width is not sacrificed, and the expanded address line can be used to select different memory modules, so that the address decoding logic is simpler, the design complexity is reduced, and the feasibility of physically implementing the testable circuit of the target memory with a large bit width can be improved.

[0065] In some embodiments, the test address bit width of the storage package module is equal to the sum of the address bit width of the memory module and the extended bit width corresponding to the at least one extended address line; and the test data bit width of the storage package module is equal to the data bit width of the memory module.

[0066] In the embodiment of the utility model, the address bit width of the memory module is equal to the address bit width of the target memory, namely the address bit width of the memory module is log2(DEPTH); and the data bit width of the memory module is equal to 1 / N times the width of the target memory, namely the data bit width of the memory module is SUB_WIDTH=WIDTH*1 / N.

[0067] In order to save resource overhead, in the packaging design, for the storage packaging module 101, the information can include: the test address bit width is log2(DEPTH)+log2(N), the test data bit width is SUB_WIDTH, and the corresponding interface bus is the same group of test buses.

[0068] In the current general design process, a corresponding number of storage packaging modules is generally generated according to the number of spliced memory modules, and each storage packaging module needs an independent test logic module. As shown in Figure 3 For the memory module RM_1, a first storage packaging module and a corresponding first test logic module are generated; for the memory module RM_2, a second storage packaging module and a corresponding second test logic module are generated; and for the memory module RM_N, an Nth storage packaging module and a corresponding Nth test logic module are generated. In this way, since each storage packaging module needs an independent test logic module, logic resource waste is caused, and the layout and routing design of the back end is increased.

[0069] It should be noted that in the storage chip design, the storage packaging (SRAM Wrapper) is an important part of the hardware structure, and the core function is to complete the signal adaptation and protection between the SRAM storage array and the external interface. Among them, Wrapper is the "shell" of the storage array, and its layout needs to match its depth (such as 512 columns) and width (such as 1024 bits), and is electrically connected through a metal wiring layer.

[0070] It should be further noted that in the SRAM Wrapper design, the test logic module 102 can refer to the MBIST test module, which is the core hardware structure for implementing memory self-checking, and its design needs to consider both functional integrity and chip area / power consumption optimization. Among them, the MBIST test logic can interact with the outside through the special pins of Wrapper, and it needs to be physically aligned with the address line and data line of the memory module.

[0071] Therefore, the embodiment of the present application can virtually regard a plurality of memory modules as a whole, adapt by modifying a corresponding configuration file, generate a storage packaging module 101 and a corresponding intermediate file, use the intermediate file as an input of test logic, and further generate a corresponding test logic module 102. In this way, a target memory with a large bit width spliced by N memory modules can use the storage packaging module designed by the embodiment of the present application to perform MBIST logic design, so that the logic resource usage is about 1 / N of a general design process, and the number of MBIST logic interface buses is also reduced by about 1 / N, thereby greatly saving logic resources and reducing the wiring pressure in the layout and wiring stage.

[0072] In some embodiments, in Figure 1 Based on the storage device 10 shown in the figure, referring to Figure 4 The storage device 10 can further include a timing module 103 disposed between the test logic module 102 and the storage packaging module 101.

[0073] In the embodiment of the present application, the timing module 103 includes a plurality of timing registers. Among them, the timing registers are correspondingly arranged between each interface of the test logic module 102 and the storage packaging module, and the number of timing registers is equal to the sum of the test address bit width of the storage packaging module, the test data bit width of the storage packaging module and 2.

[0074] That is, in order to control the delay between the test logic module 102 and the storage packaging module 101, the timing module 103 can be inserted here to make the path delay of each data reaching the storage packaging module 101 meet the delay requirement. Exemplarily, a timing register is inserted at each interface of the test logic module 102 for timing control, so as to meet the delay requirement.

[0075] In the embodiment of the present application, for the storage packaging module with a test address bit width of log2(DEPTH)+log2(N) and a test data bit width of SUB_WIDTH, the number of timing registers required to be inserted in the corresponding back-end interface signal is log2(DEPTH)+log2(N)+SUB_WIDTH+2, wherein 2 represents 2 bits of read and write enable signals (including 1 bit of read enable signal and 1 bit of write enable signal). In other words, a timing register needs to be inserted for each interface signal for timing control to realize synchronous delay of the signal.

[0076] In this way, by inserting registers into long paths for timing control, the original single timing path is split into multiple short paths. The delay of each path is limited to a single clock cycle, thus ensuring that the signal can reach the next-level register within a specified time and meet timing constraints. In addition, the delay duration of the timing register timing is equal to "number of register stages × clock cycle", which makes the delay accuracy high and controllable, avoiding timing errors during signal transmission.

[0077] In some embodiments, Figure 4 Based on the storage device 10 shown, see... Figure 4 The storage encapsulation module 101 may further include a first decoding module a1, wherein:

[0078] The enable pin of the first decoding module a1 is used to receive the chip select enable signal;

[0079] The input terminal of the first decoding module a1 is connected to at least one extended address line, and the output terminal of the first decoding module a1 is used to output multiple read and write control signals, and there is a one-to-one correspondence between the multiple read and write control signals and multiple memory modules.

[0080] In this embodiment of the invention, the first decoding module is typically abbreviated as "dec". The first decoding module a1 converts the input encoded signal into a specific output signal, such as a set of mutually exclusive control signals or status signals. For example, in the instruction decoding circuit, the input is a binary instruction code, and the output is the corresponding control signal, used to trigger operations such as computation, storage, or data transmission within the memory module.

[0081] In this embodiment of the invention, the enable terminal of the first decoding module a1 ( Figure 4 (Not shown) is used to receive the chip select enable signal to control the working state of the decoding module, ensuring that the read / write control signal is effective under normal conditions and avoiding invalid decoding or triggering. Among the multiple read / write control signals output at the same time, only one read / write control signal is effective; for example, this read / write control signal is in the first level state, while other invalid read / write control signals are in the second level state. Therefore, this read / write control signal can also be called the "chip select signal".

[0082] In other words, the first decoding module a1 can be an address decoding module, which can perform chip selection on different memory modules based on these extended address lines. For example, by inputting these extended address lines into the first decoding module a1, multiple read / write control signals can be output from its output terminal, with different read / write control signals corresponding to different memory modules. Based on these read / write control signals, the selected memory module can be determined.

[0083] Exemplarily, if the number of memory modules N=2, 1 extended address line is needed for chip selection, i.e. 2 read-write control signals can be obtained according to the 1 extended address line; if the number of memory modules N=8, 3 extended address lines are needed for chip selection, i.e. 8 read-write control signals can be obtained according to the 3 extended address lines. Wherein, the read-write control signal corresponding to the unselected memory module is in the second level state, and the read-write control signal corresponding to the selected memory module is in the first level state.

[0084] Exemplarily, the first level state is a low level state, and the second level state is a high level state; or, the first level state is a high level state, and the second level state is a low level state. In the embodiment of the utility model, the first level state can be selected as a low level state, and the second level state can be selected as a high level state.

[0085] In this way, in the embodiment of the utility model, the read-write control signal is generated by the address decoding module to select the different memory modules, without the need to separately control the enablement of each memory module, so that the access logic is simplified; moreover, only the selected memory module will respond to the read-write operation, and the unselected module is in an idle state (i.e. does not participate in data transmission), so that the multiple memory modules are prevented from being mistakenly triggered at the same time, and the accuracy of data reading and writing and the stability of data transmission are improved.

[0086] In some embodiments, continuing to refer to Figure 5 , the storage packaging module 101 can further include a plurality of first selection modules (b1, b2, … bN), and the output end of each first selection module is connected with the read-write enable port of the memory module. Wherein, the first input end of the first selection module is used for receiving the read-write control signal, the second input end of the first selection module is used for receiving the first read-write enable signal f_mem_en, and the output end of the first selection module is used for outputting the second read-write enable signal, such as mem1_en, mem2_en, … memN_en, to the memory module.

[0087] Exemplarily, taking the first selection module b1 as an example, the first input end of the first selection module b1 is connected with the first output end of the first decoding module a1, and is used for receiving the corresponding read-write control signal; the second input end of the first selection module b1 is used for receiving the first read-write enable signal f_mem_en provided externally, and the output end of the first selection module b1 is connected with the enable end of the memory module RM_1, and is used for outputting the second read-write enable signal mem1_en to the memory module RM_1.

[0088] In a possible implementation, still taking the first selection module b1 as an example, the second read-write enable signal mem1_en can be 2 bits, for example, including a second read enable signal mem1_ren and a second write enable signal mem1_wen. Wherein, if the second write enable signal mem1_wen takes the second level state, it means that the memory module RM_1 is selected and the write test operation is performed; if the second read enable signal mem1_ren takes the first level state, it means that the memory module RM_1 is selected and the read test operation is performed. Exemplarily, the first level state is a high level state.

[0089] Thus, in the embodiment of the utility model, the second read-write enable signal of each memory module can be obtained according to the first selection module corresponding to each memory module, which can control whether the read operation test or the write operation test is performed on the memory module, so as to realize the read-write test of each memory module in the memory packaging module 101 by the test logic module 102.

[0090] It can be understood that the test data line includes a read test data line. Correspondingly, in some embodiments, in the read test operation, the read test data line is used to transmit the read data signal of the selected memory module to the test logic module. Figure 5 Based on the storage device 10 shown, referring to Figure 4 The memory packaging module 101 can further include a second decoding module a2, wherein:

[0091] The enable end of the second decoding module a2 is used to receive the chip selection enable signal;

[0092] The plurality of input ends of the second decoding module a2 are connected with the read ports of the plurality of memory modules one by one, and are used to receive the read data signals of the plurality of memory modules respectively;

[0093] The output end of the second decoding module a2 is connected with the read port of the test logic module through at least one read test data line, and is used to transmit the read data signals of the plurality of memory modules to the test logic module.

[0094] In the embodiment of the utility model, the chip selection enable signal received by the second decoding module a2 and the chip selection enable signal received by the first decoding module a1 are the same signal, which can ensure that the read data operation is performed on the same selected memory module.

[0095] It should be noted that the enable end of the second decoding module a2 Figure 5The read data signal of the selected memory module is sent to the test logic module 102 through the corresponding read test data line. For example, if the selected memory module is RM_1, the read data signal rdata1 of the memory module RM_1 is sent to the test logic module 102 as the read data test signal m_rdata through the second decoding module a2; if the selected memory module is RM_2, the read data signal rdata2 of the memory module RM_2 is sent to the test logic module 102 as the read data test signal m_rdata through the second decoding module a2. In this way, the read data signals in the memory modules are sent to the test logic module 102 in turn according to a certain order, so that the read test operation can be performed in the test logic module 102.

[0096] It should be further noted that, in the embodiment of the utility model, in the case of reading out data, whether the read data signal is sent to the test logic module 102 for read test or sent to the function design (Function) side is not limited here. That is to say, when reading data, the selection module (Mux) for bifurcation processing of the function design side and the MBIST test side does not need to be added here.

[0097] For example, for the N memory modules, the obtained read data on the function design side can be f_rdata={rdataN,…,rdata2,rdata1}.

[0098] In this way, in the embodiment of the utility model, the second decoding module can send the read data signals of different memory modules to the test logic module 102 according to the validity of the read-write control signal, without the need to separately control the enablement of each memory module, so that the access logic is simplified; moreover, only the selected memory module will respond to the read operation, and the unselected module does not participate in data transmission, so that the multiple memory modules are prevented from being mistakenly triggered at the same time, and the accuracy of read data and the stability of data transmission are improved.

[0099] It can also be understood that the test data line further includes a write test data line. Accordingly, in some embodiments, in the case of writing data, the write data signal of the selected memory module is sent to the test logic module 102 through the corresponding write test data line. Figure 6 Based on the storage device 10 shown in the figure, continuing to refer to Figure 6 The storage package module 101 can further include a plurality of second selection modules (c1, c2, … cN) and a plurality of third selection modules (d1, d2, … dN).

[0100] In the embodiment of the utility model, the output end of each second selection module is connected with the write port of the memory module correspondingly. Specifically, the enable end of the second selection module is used for receiving a test enable signal; the first input end of the second selection module is connected with the write port of the test logic module through at least one write test data line, and is used for receiving a write data test signal; the second input end of the second selection module is used for receiving a write data function signal, and the output end of the second selection module is used for outputting a target write data signal to the memory module.

[0101] It should be noted that the second selection module is used for branching processing of write data of each memory module under a test branch (for example, an MBIST mode) and a function design branch (for example, a Function mode) through a test enable signal. The test enable signal can be represented by mbist_en.

[0102] It should be further noted that for the test enable signal mbist_en, if the test enable signal mbist_en is in a first level state, the data corresponding to the function branch can be written into the corresponding memory module at this time; if the test enable signal mbist_en is in a second level state, the data corresponding to the test branch can be written into the corresponding memory module at this time.

[0103] Exemplarily, taking the second selection module c1 as an example, the enable end of the second selection module c1 is used for receiving the test enable signal mbist_en; the first input end of the second selection module c1 is used for receiving the write data test signal m_wdata sent by the test logic module 102; the second input end of the second selection module c1 is used for receiving the write data function signal f_wdata, and the output end of the second selection module c1 is used for outputting the target write data signal wdata1 to the memory module RM_1. Similarly, taking the second selection module cN as an example, the enable end of the second selection module cN is used for receiving the test enable signal mbist_en; the first input end of the second selection module cN is used for receiving the write data test signal m_wdata sent by the test logic module 102; the second input end of the second selection module cN is used for receiving the write data function signal f_wdata, and the output end of the second selection module cN is used for outputting the target write data signal wdataN to the memory module RM_N.

[0104] Exemplarily, for the N memory modules, on the function design side, the obtained write data can be f_wdata={f_wdataN,...,f_wdata2,f_wdata1}.

[0105] Thus, taking the second selection module c1 as an example, assuming that the memory module RM_1 is selected, if the test enable signal mbist_en is in the first level state, the data f_wdata1 corresponding to the function branch can be selected as the target write data signal wdata1 and written into the memory module RM_1; if the test enable signal mbist_en is in the second level state, the data m_wdata corresponding to the test branch can be selected as the target write data signal wdata1 and written into the memory module RM_1.

[0106] Similarly, taking the second selection module cN as an example, assuming that the memory module RM_N is selected, if the test enable signal mbist_en is in the first level state, the data f_wdataN corresponding to the function branch can be selected as the target write data signal wdataN and written into the memory module RM_N; if the test enable signal mbist_en is in the second level state, the data m_wdata corresponding to the test branch can be selected as the target write data signal wdataN and written into the memory module RM_N.

[0107] Thus, in the embodiment of the utility model, the second selection module distinguishes the test branch and the function design branch according to the level state of the test enable signal mbist_en, can avoid the interference of the test logic and the function logic, and can also avoid that the normal read and write in the function mode may "pollute" the test environment of the MBIST, thereby improving the accuracy of the MBIST test and the reliability of the function mode, and reducing the design complexity.

[0108] In the embodiment of the utility model, the output end of each third selection module is connected with the address port of the memory module. Specifically, the enable end of the third selection module is used for receiving the test enable signal; the first input end of the third selection module is connected with the address port of the test logic module through at least one test address line, and is used for receiving the test address signal; the second input end of the third selection module is used for receiving the function address signal, and the output end of the third selection module is used for outputting the target address signal to the memory module.

[0109] It should be noted that the third selection module can be used for diverging the address access of each memory module under the test branch (for example, the MBIST mode) and the function design branch (for example, the Function mode) through the test enable signal mbist_en.

[0110] Exemplarily, taking the third selection module d1 as an example, the enable end of the third selection module d1 is used for receiving a test enable signal mbist_en; the first input end of the third selection module d1 is used for receiving a test address signal m_addr sent by the test logic module 102, the second input end of the third selection module d1 is used for receiving a function address signal f_addr, and the output end of the third selection module d1 is used for outputting a target address signal addr0 to the memory module RM_1. Similarly, taking the third selection module dN as an example, the enable end of the third selection module dN is used for receiving the test enable signal mbist_en; the first input end of the third selection module dN is used for receiving the test address signal m_addr sent by the test logic module 102, the second input end of the third selection module dN is used for receiving the function address signal f_addr, and the output end of the third selection module dN is used for outputting a target address signal addrN to the memory module RM_N.

[0111] In the embodiment of the utility model, still taking the third selection module d1 as an example, suppose that the selected is the memory module RM_1, if the test enable signal mbist_en is in the first level state, then can select the function address signal f_addr corresponding to the function branch as the target address signal addr0 of the memory module RM_1;If the test enable signal mbist_en is in the second level state, then can select the test address signal m_addr corresponding to the test branch as the target address signal addrN of the memory module RM_1. Exemplarily, the first level state is low level state, and the second level state is high level state.

[0112] In addition, for the read data test and the write data test can be a group of test address lines independent of each other;Or also can be sharing the same group of test address lines, namely multiplexing address line to reduce hardware resource consumption. Exemplarily, if the read data test and the write data test share the same group of test address lines, then in the case that the second write enable signal mem1_wen is used for indicating that the memory module RM_1 is selected and carries out the write test operation, then can according to the test address line in succession access the storage unit corresponding to the corresponding address, and write data to the storage unit;In the case that the second read enable signal mem1_ren is used for indicating that the memory module RM_1 is selected and carries out the read test operation, then also can according to the test address line in succession access the storage unit corresponding to the corresponding address, and read out data from the storage unit.

[0113] Therefore, in the embodiment of the utility model, read data test and write data test share the same set of test address lines, which can reduce the number of test address lines by half, especially in the scene of chip pin resource shortage (such as embedded chip, small memory device), which can significantly reduce the packaging cost and wiring complexity; Moreover, it is suitable for single-port memory device, which only has one set of address decoding module in the hardware structure, thereby saving hardware resources and reducing the wiring pressure in the layout and wiring stage.

[0114] In addition, in the embodiment of the utility model, the fork processing under the test branch (such as MBIST mode) and the function design branch (such as Function mode) can make the function and MBIST design have different bus interfaces respectively. Exemplarily, during the function design, the data path, address decoding, control signal (such as chip selection, read-write enablement, etc.) of the memory module during normal reading and writing should fully comply with the design specification; During the MBIST test, it is necessary to ensure that the test sequence can cover all target faults, and the judgment logic of the test result is accurate. In this way, the two branches can be independently carried out, for example, the function design branch mainly focuses on the simulation and debugging of normal access scenarios, and the MBIST test branch does not need to consider the interference of the function mode, which is convenient for positioning the defects of the test logic and reduces the complexity.

[0115] In another embodiment of the utility model, for the depth DEPTH of the memory module, DEPTH can be equal to an integer power of 2, or can not be equal to an integer power of 2, based on the storage device 10 described in the foregoing embodiment. If DEPTH is equal to an integer power of 2, the storage packaging module 101 can cope with the full address scan read-write test issued by the test logic module 102, but when DEPTH is not equal to an integer power of 2, the full address scan read-write test will encounter problems.

[0116] Exemplarily, Figure 6 The utility model provides a kind of logical address incremental access sequence schematic diagram of storage packaging module for embodiment of the utility model. As Figure 7 As shown, since the depth of a single memory module is not aligned to an integer power of 2, the test logic module 102 (such as MBIST control logic) will access the hollow address interval beyond the physical address boundary of the actual memory module when issuing incremental logical addresses, such as sram1_rsv, sram2_rsv,..., sramN_rsv, etc., thereby causing the MBIST test of the memory module to fail. Wherein, each memory module can be split into multiple storage units or multiple storage blocks (Bank). In Figure 7In the figure, the arrow direction represents the address increment order, which is the address increment from bottom to top in the vertical direction (or column manner); N represents the number of memory modules participating in splicing, M or m represents the number of Banks that each memory module can be split into, d represents the address bit width corresponding to the depth of a single memory module, and b represents the address bit width corresponding to the depth of a single memory block.

[0117] Exemplarily, if the depth of a single memory module is equal to 6, there are three test address lines at this time, that is, the maximum accessed test address is 8, and when the test address 7 and the test address 8 are accessed, it belongs to the hole address interval of the physical address boundary, causing the MBIST test to fail. The reason is that in the general design process, the MBIST test logic is automatically generated according to the output file of the Memory compiler, and at this time, the test address issued is logically continuously incremented.

[0118] In the embodiment of the present application, when the depth of the memory module is not equal to an integer power of 2, the MBIST interface test address line corresponding to the foregoing storage packaging module can be remapped to achieve the purpose of converting discontinuous addresses to address continuous addresses.

[0119] In some embodiments, for each memory module, the memory module can include a plurality of memory blocks. In the case where the depth of the memory module is not equal to an integer power of 2, the size of the memory block needs to satisfy the following two conditions:

[0120] The size of the memory block is equal to an integer power of 2;

[0121] The size of the memory block can be evenly divided by the depth of the memory module.

[0122] In the embodiment of the present application, the size of the memory block can also be referred to as "data access Bank granularity", so it can be represented by sub_size. That is, here it is necessary to determine the data access Bank granularity sub_size that the spliced storage packaging module 101 can support, and sub_size needs to satisfy 2 conditions: (a) an integer power of 2, that is, sub_size=2 k(k is a non-negative integer); (b) the depth DEPTH of the memory module can be evenly divided by the sub_size, i.e. DEPTH%sub_size=0 (the remainder is 0). Wherein, the former is because the address line in the digital circuit adopts binary coding, and the integer power of 2 can ensure that the address offset (low k bits) in the Bank is naturally aligned with the binary address, avoiding the complexity of address decoding logic (such as no additional remainder calculation); the latter is to ensure that the depth of the memory module can be evenly divided into multiple Banks, and the size of each Bank is sub_size. In this way, after meeting the two conditions, the largest value can be selected as the access Bank granularity of the storage packaging module 101.

[0123] Exemplarily, assuming that the depth DEPTH of the memory module is 1024 (2 10 ), the corresponding "integer power of 2" factors can include: 1 (2 0 ), 2 (2 1 ), 4 (2 2 ), …, 512 (2 9 ), 1024 (2 10 ). Among them, considering the adjustment of the number (N) of spliced memory modules in the actual design, if N=4, the too large sub_size may cause the Bank division to be too coarse, and the subsequent address adjustment effect is not good; usually, the largest candidate value less than DEPTH is selected as the final sub_size, for example, 256 or 512.

[0124] In this way, in the embodiment of the utility model, by determining the reasonable access Bank granularity (sub_size), the uniform distribution between multiple spliced memory modules can be realized when the continuous address is accessed, and the problem that the MBIST test fails due to the existence of the hollow address interval of the physical address boundary can also be avoided.

[0125] In some embodiments, the bit number of at least one extension address line is mapped between the xth bit and the x+yth bit corresponding to the at least one test address line; wherein x represents the logarithmic value of the size of the storage block with 2 as the base, and y represents the value of the number of extension address lines minus one.

[0126] In the embodiment of the utility model, the newly added log2(N) bit address line originally in the highest bit can be exchanged between the log2(sub_size)th bit and the log2(sub_size)+log2(N)-1th bit of the original address line, wherein y represents the value of (log2(N)-1).

[0127] Exemplarily, Figure 7 A schematic diagram of the logical address incremental access sequence after the address sequence of the storage packaging module provided in the embodiment of the utility model is shown in FIG. 4. As shown in FIG. 4, the address line of the storage packaging module is divided into two parts: the original address line and the extension address line.Figure 8 As shown, at this time, the storage encapsulation module corresponds to the full space Bank access order, the minimum access Bank is Bank0, and the maximum access Bank is Bank(M*N-1). Specifically, when the address is continuously increased, after the Bank0 address interval of the memory module SRAM1 is accessed, the next access address jumps to the first Bank of SRAM1. In this way, the purpose of continuously accessing the address in the 0 address and the maximum address interval by the MBIST control logic is achieved, and at this time, the MBIST control logic will ensure that the access address exceeding the maximum Bank (M*N-1) is not issued. In Figure 8 In the figure, the arrow direction represents the address increasing order, which is the address increasing from left to right in the horizontal direction (or in the row manner); N represents the number of memory modules participating in splicing, M or m represents the number of Banks that can be split by each memory module, d represents the address bit width corresponding to the depth of a single memory module, and b represents the address bit width corresponding to the depth of a single memory block.

[0128] Exemplarily, it is assumed that the original test address line (A_orig) has log2(DEPTH) bits, which is functionally divided into two parts: (i) low k bits (A_low): k=log2(sub_size), representing the offset address in a single Bank (covering 0~sub_size-1); (ii) high m bits (A_mid): m=log2(DEPTH)-k, representing the Bank number in a single memory module SRAM (covering 0~(DEPTH / sub_size)-1). In addition, a new address line (A_high) is added: log2(N) bits, representing the SRAM number participating in splicing (covering 0~N-1).

[0129] Before the address line mapping adjustment, the arrangement of the total address (A_total) is: [A_high][A_mid][A_low] (from the highest bit to the lowest bit). At this time, when the address is continuously increased, A_low overflows first (from sub_size-1 to 0), triggering A_mid to increase, and continuing to access the next Bank in the same SRAM; until A_mid overflows, A_high is triggered to increase, and the next SRAM is accessed. In this way, the continuous address is concentrated in a single SRAM, which not only leads to bandwidth waste, but also may access to a hollow address interval and cause the MBIST test to fail.

[0130] After the address line mapping adjustment, the arrangement of the total address (A_total) is: [A_mid][A_high][A_low]. That is, A_high is moved from the highest bit to between "A_mid" and "A_low" (i.e. between the kth bit (log2(sub_size)) and the k+log2(N)-1th bit of the original address line). In this way, when the continuous address is incremented, A_low overflows first, triggering A_high to be incremented (rather than A_mid), that is, after accessing "Bank0 of SRAM0", the next address automatically jumps to "Bank0 of SRAM1", and then to "Bank0 of SRAM2"... until A_high overflows, triggering A_mid to be incremented, and accessing the next Bank of SRAM0.

[0131] In this way, in the embodiment of the utility model, through determining reasonable access Bank granularity (sub_size) and adjusting address line mapping relationship, and the adjusted Bank access order and real physical address one-to-one mapping, not only realize the uniform distribution between multiple spliced SRAMs when continuous address is accessed (i.e. after accessing a certain Bank of a SRAM, the next address automatically jumps to the corresponding Bank of the next SRAM), but also can avoid the problem of MBIST test failure caused by accessing the hollow address interval of the physical address boundary, and improve the access parallelism and efficiency under the multi-SRAM splicing scene.

[0132] In another embodiment of the utility model, based on the storage device 10 described in the foregoing embodiment, an SRAM Wrapper design scheme is provided, which converts the functionally bit-width spliced SRAM into deep splicing in MBIST design to greatly optimize the MBIST logic resource use of large bit-width SRAM and greatly reduce the number of interface buses, and reduce the back-end MBIST logic routing pressure.

[0133] In the embodiment of the utility model, the bit-width spliced SRAM Wrapper design scheme provided herein mainly includes the following two steps:

[0134] Step 1, SRAM Wrapper MBIST interface bit-width splicing to deep splicing scheme.

[0135] For a large bit-width SRAM, it is usually not directly generated by Memory compiler, and needs to be split into multiple generatable SRAM Wrapper for bit-width splicing. In this way, in the DFT MBIST general design process, multiple SRAM Wrapper also need to be individually designed for MBIST. For example, Figure 8As shown, assuming a large bit-width SRAM with a size of DEPTH*WIDTH needs to be bit-width spliced by N pieces of small bit-width SRAM, the SRAM information seen in the MBIST design flow and the function mode are the same.

[0136] As shown in Figure 8 , each memory module has a corresponding storage packaging module and test logic module, for example, memory module RM_1 has a corresponding first storage packaging module and first test logic module, memory module RM_2 has a corresponding second storage packaging module and second test logic module, and so on, and memory module RM_N has a corresponding Nth storage packaging module and Nth test logic module. In addition, there are also a plurality of fourth selection modules (e1, e2, … eN), a plurality of fifth selection modules (j1, j2, … jN), and a plurality of sixth selection modules (i1, i2, … iN). The fourth selection modules (e1, e2, … eN) have a similar function to the first selection module, and are used to generate the read and write enable signals of each memory module; the fifth selection modules (j1, j2, … jN) have a similar function to the second selection module, and are used to select and process the write data of the MBIST test side and the function design side according to the test enable signal mbist_en; the sixth selection modules (i1, i2, … iN) have a similar function to the third selection module, and are used to select and process the read and write addresses of the MBIST test side and the function design side according to the test enable signal mbist_en.

[0137] That is, in Figure 5 , each Memory compiler generates an SRAM corresponding to a separate storage packaging module (SRAM_Wrapper_old), and each Wrapper corresponds to a separate MBIST test logic, and the MUX of the interface signal is automatically inserted outside the Wrapper by the DFT design flow. Among them, the depth of the SRAM participating in splicing is DEPTH, the data bit width of the SRAM participating in splicing is SUB_WIDTH, and there are N SRAM splices. In addition, f_* represents the Function logic related interface; m_* represents the MBIST logic related interface.

[0138] In this way, based on Figure 5 the SRAM information shown: the address bit width is log2(DEPTH), the data bit width is SUB_WIDTH, and the SRAM interface bus is N groups. When designing MBIST, N pieces of MBIST control logic need to be generated, and timing registers need to be inserted for (log2(DEPTH)+SUB_WIDTH)*N interface lines.

[0139] To save on these resource costs, such as Figure 5 As shown, this embodiment of the invention separates the addr, wdata, and rdata interfaces of the underlying SRAM in MBIST mode and Function mode after mux selection via the test enable signal mbist_en. The processing of the interface on the Function side is the same as that of the general design scheme to ensure the correctness of the logic function; the MBIST side interface performs chip selection on addr, wdata, and rdata of different SRAM MBIST interfaces by adding log2(N) bit address lines. In this way, all SRAM MBIST interfaces in the storage packaging module will reuse the same set of test buses, realizing the purpose of converting bit-width splicing to depth splicing in MBIST design.

[0140] In other words, Figure 6 In this process, multiple SRAMs split into large-width segments can be processed separately within the same storage wrapper module (SRAM_Wrapper_new) using either a Function branch or an MBIST branch. The Function branch maintains the bit-width concatenation, while the MBIST branch converts the bit-width concatenation into depth concatenation. The depth of the SRAMs involved in the concatenation is DEPTH, and the data bit width of the SRAMs involved in the concatenation is SUB_WIDTH, with a total of N SRAMs concatenated. Furthermore, f_* represents the Function logic-related interface; m_* represents the MBIST logic-related interface.

[0141] Thus, based on Figure 6 The SRAM information shown is as follows: the test address width is log2(DEPTH) + log2(N), the test data width is SUB_WIDTH, and there is one SRAM interface bus. In the MBIST process, only one MBIST Wrapper needs to be generated for the test address width of log2(DEPTH) + log2(N) and the test data width of SUB_WIDTH. The number of interface timing registers that need to be inserted at the back end is reduced to log2(DEPTH) + log2(N) + SUB_WIDTH + 2. Here, 2 represents 2 bits of read / write enable signals; for example, it can include a 1-bit read enable signal and a 1-bit write enable signal.

[0142] Step 2: MBIST address contiguous mapping scheme for SRAM splicing of depths other than powers of 2.

[0143] For the storage package design listed in Step 1, when DEPTH is equal to an integer power of 2, the Wrapper can cope with the full address scan read-write test issued by the MBIST logic, but the full address scan read-write test encounters problems when DEPTH is not equal to an integer power of 2. As shown in Figure 7 , because the depth of a single SRAM is not aligned to an integer power of 2, the MBIST control logic accesses a hollow address interval beyond the actual SRAM physical address boundary when issuing an incrementing logical address, such as sram0_rsv, sram1_rsv... sram(N-1)_rsv, and so on, thereby causing the SRAM MBIST test to fail (in the general design flow, the MBIST test logic is automatically generated according to the output file of the Memory compiler, and the test addresses issued are logically continuous and incrementing).

[0144] That is, in Figure 7 , when the new address is in the high bit, the logical address incrementally accesses the Bank access order of the full space of the SRAM, with the minimum access Bank being Bank0 and the maximum access Bank being Bank(M*N-1). The dot-filled part is the hollow address region caused by the non-2 integer power alignment of the SRAM depth, and this part of the logical address does not have a real physical address corresponding thereto.

[0145] To solve this problem, when the SRAM depth is not equal to an integer power of 2, the MBIST interface address lines of the SRAM Wrapper spliced in Step 1 can be remapped to achieve the purpose of converting the discontinuous addresses to address-continuous addresses.

[0146] As shown in Figure 8 , first, the data access Bank granularity sub_size that the spliced SRAM Wrapper can support needs to be determined, and sub_size needs to satisfy 2 conditions: (i) is an integer power of 2; (ii) can divide the depth DEPTH of the original SRAM. After satisfying the two conditions, the largest value can be selected as the access Bank granularity of the SRAM Wrapper. Then only the newly added log2(N) bit address line originally in the highest bit needs to be exchanged to between the log2(sub_size) bit and the log2(sub_size)+log2(N)-1 bit of the original address line. In this way, when the addresses are continuously incremented, after the Bank0 address interval of SRAM1 is accessed, the next address will jump to the first Bank of SRAM2. In this way, the purpose of the MBIST control logic accessing addresses continuously in the 0 address and the maximum address interval can be achieved (the MBIST control logic will ensure that no address beyond the maximum Bank (M*N-1) is issued).

[0147] That is, in Figure 5 , the logical increment increment access SRAM full space Bank access order after adjusting the minimum access Bank is Bank0, and the maximum access Bank is Bank(M*N-1). Based on the address increment order shown by the arrow, the adjusted Bank access order and the real physical address are one-to-one mapped. Wherein, N represents the number of SRAM participating in splicing, and is an integer power of 2; M or m represents the number of Banks that can be split for each SRAM; d represents the address bit width corresponding to the SRAM depth; and b represents the address bit width corresponding to the Bank depth.

[0148] Exemplarily, it is assumed that in the storage chip design, a piece of SRAM with a depth of 320 and a bit width of 4096 bits needs to be customized, and the maximum SRAM entity that can be generated by the Memory compiler has a depth of 320 and a bit width of 512 bits. Therefore, the designer can use 8 pieces of 320*512 (referring to depth*bit width, the same below) SRAM Wrapper to splice the bit width into 320*4096 specifications.

[0149] In the general design process, 8 storage packaging modules (SRAM_Wrapper_old) with a depth of 320*512 as shown in Figure 9 will be generated first. When performing bit width splicing in terms of function, 9 bits of read / write addresses of the 8 wrappers are connected to the same group, read / write enables are connected to the same control signal, and 4096 bits of write data are divided into 8 groups according to 512 bits as a unit and connected to Wrapper0-7 respectively. The read data is combined into 4096 bits of data of the 8 wrappers and provided to the logic for use. The MBIST design process of DFT will generate a test logic module (MBIST Test Logic) for each Wrapper respectively, and then an interface MUX is made outside each Wrapper to control the MBIST control logic to access the corresponding SRAM. A total of 8 wrappers need to generate 8 sets of MBIST control logic respectively, and in addition, the interface signals involved have a total of 8×(9×2+1×2+512×2)=8352 bits. 8352 registers are needed to consume in the timing simulation in the back end. Wherein, "×2" here refers to a group of interface signal lines corresponding to read data and another group of interface signal lines corresponding to write data; and the 1 bit added here refers to the read / write enable signal such as m_mem1_en, m_mem2_en or m_memN_en.

[0150] When the technical scheme of the embodiment of the utility model is used, as Figure 9As shown, first, the functional side interface and the MBIST test interface are bifurcated using the mbist_en control signal at each SRAM interface, so that the functional design and the MBIST test design have bus interfaces that are different from each other. When processing inside the storage wrapper module (SRAM_Wrapper_new), the interface processing of the functional side and the general design flow are the same, and the 9-bit read / write addresses of the 8 SRAMs are connected to the same group, the read / write enable is connected to the same control signal, and the 4096-bit write data is divided into 8 groups of 512 bits each and connected to Wrapper0-7, and the read data is combined into 4096 bits of 512-bit data from the 8 wrappers and provided to the logic. The interface processing of the MBIST side is different from the general design, and the high bits of the address line need to be increased by log2(8)=3 bits to select SRAM0-7, and the low 9-bit address line is connected to the 9-bit address line of the 8 SRAMs through a one-to-many connection, and the Wrapper has a total of 12-bit address lines; the 1-bit read / write enable signal input by the Wrapper and the newly added 3-bit address decoding (generating 8-bit decoding signals) are logically ANDed to serve as the read / write enable signal of each SRAM; the 512-bit wdata signal is connected to the wdata interface of the 8 SRAMs through a one-to-many connection; and the 512-bit rdata of the 8 SRAMs is used as the read data of the MBIST test after being decoded by the newly added 3-bit address. A Wrapper needs 1 copy of MBIST control logic, in addition to the interface signals involved, which are 12*2+1*2+512*2=1050 bits, and only 1050 registers are needed for timing punching in the back end. Among them, if it is a single-port memory, i.e., the read and write share a set of addresses, then it should be 12+1*2+512*2=1038 bits; if it is a dual-port memory, i.e., the read and write use a set of addresses respectively, then it should be 12*2+1*2+512*2=1050 bits. In addition, the 1-bit added here is provided by the test logic module and input to the first decoding module, which can be regarded as a signal line parallel to m_addr_ext. Considering that read and write are set separately, 1*2=2 bits are needed, which include: 1-bit read enable signal under read operation and 1-bit write enable signal under write operation.

[0151] It should also be noted that since the depth of SRAM is 320, which is not an integer power of 2, and the 12-bit access address issued by the MBIST control logic is from 0x0 to 0x9FF (320*8-1) in continuous increment. When the access address is 0x140 (320), since addr[11:9]=0x0, the access is still in the logical address region of SRAM1, while the physical address of SRAM1 is only from 0x0 to 0x13F (depth 320), resulting in the address 0x140 falling in the hole address region and not being responded, thus causing the MBIST test to be wrong. At this time, the address needs to be remapped.

[0152] In a specific implementation, first, the Bank access granularity satisfying the two conditions (i) an integer power of 2; (ii) divisible by 320 is found. According to the two conditions, 64 is the maximum Bank granularity satisfying the two conditions. Then the newly added addr[11:9] needs to be exchanged between the 6th and 8th bits of the address (i.e. the original new addresses 9, 10, 11 are adjusted to the 6th, 7th, and 8th bits) of log2(64)=6 and log2(64)+1=8. The adjusted address order is addr_new={addr[8:6], addr[11:9], addr[5:0]}. When the access address is 0x40 (64), since addr_new[8:6]=0x1, the access will fall in the 0x0 address of Bank0 of SRAM2, so that the address access between the maximum address 0x9FF can be guaranteed to correspond to the physical address one by one.

[0153] In the embodiments of the present application, the specific implementation of the foregoing embodiments is described in detail through the foregoing embodiments, and it can be seen from the foregoing embodiments that the technical solutions of the foregoing embodiments not only provide an SRAM Wrapper MBIST interface bit width splicing to depth splicing scheme, but also provide a non-2 integer power depth SRAM splicing address continuous mapping scheme. In this way, in the SRAM MBIST design process, the scheme provided by the embodiments of the present application has significant benefits compared with the current general design scheme, and the greater the SRAM bit width and the more the splicing numbers, the more obvious the advantages. Mainly reflected in the following aspects: first, the MBIST logic design resources and the interface bus beating resources can be greatly reduced. A large bit width SRAM formed by splicing N small bit width SRAMs uses the Wrapper designed by the embodiments of the present application for MBIST logic design, and the logic resource usage is about 1 / N of the general scheme. Second, the MBIST logic routing problem in the layout and wiring stage can be greatly optimized. The large bit width SRAM formed by splicing N small bit width SRAMs (assuming the bit width is W) uses the MBIST logic wiring number of about N*W designed by the general scheme; and the MBIST logic wiring number designed by the scheme of the present application is reduced to about W.

[0154] In another embodiment of the present application, ​ A chip composition structure schematic diagram is provided for the embodiments of the present application. As shown in the drawings, ​ The chip 90 can include the storage device 10 described in any one of the foregoing embodiments. Wherein the chip 90 here can be a storage chip, mainly for a chip generated for a large bit width SRAM, and internally integrated with MBIST test logic.

[0155] Those skilled in the art can realize that the modules and algorithm steps of each example described in combination with the embodiments disclosed by the present application can be realized by electronic hardware or a combination of software and electronic hardware. Whether the functions are executed in hardware or software depends on the specific application and design constraints of the technical solutions. Professional technicians can use different methods to realize the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0156] The above is only a preferred embodiment of the present application, and is not used to limit the protection scope of the present application, and any modification, equivalent replacement and improvement made within the spirit and principle of the present application should be included in the protection scope of the present application.

[0157] It should be understood that the reference herein to "one embodiment" or "an embodiment" or "some embodiments" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the application. The appearance of the phrase "in one embodiment" or "in an embodiment" or "in some embodiments" in various places herein are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that the sequence of the above-described processes does not mean the order of execution, and the execution order of the processes should be determined according to the functions and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the application. The above-mentioned sequence of the embodiments of the application is only for description, and does not represent the advantages or disadvantages of the embodiments. The above description of each embodiment tends to emphasize the differences between each embodiment, and the same or similar parts can be referred to each other, and for the sake of brevity, the text will not be repeated.

[0158] It should also be noted that the terms "comprising", "including", or any other variant thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements recited, but can also include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without more limitations, the element defined by the statement "comprising a" does not exclude the presence of additional identical elements in the process, method, article, or apparatus including the element.

[0159] The above-mentioned sequence of the embodiments of the application is only for description, and does not represent the advantages or disadvantages of the embodiments.

[0160] The features disclosed in the several product embodiments of the application can be arbitrarily combined without conflict, to obtain new product embodiments.

[0161] The above describes only the specific implementation of the application, but the protection scope of the application is not limited thereto, and any skilled person in the art can easily think of changes or replacements within the technical range disclosed by the application, which should be covered within the protection scope of the application.

Claims

1. A memory device, comprising: The storage device comprises a storage package module and a test logic module corresponding to the storage package module, wherein: The storage package module comprises a plurality of memory modules corresponding to a target memory, and the test logic module is connected with the plurality of memory modules in the storage package module through a group of test buses; The test logic module is further connected with the storage package module through at least one extension address line, and the at least one extension address line is used for selecting the memory modules in the storage package module; The group of test buses comprises at least one test address line and at least one test data line, and the number of the test address lines is equal to the address bit width of the memory modules, and the number of the test data lines is equal to the data bit width of the memory modules.

2. The storage device according to claim 1, wherein: The test address bit width of the storage package module is equal to the sum of the address bit width of the memory modules and the extension bit width corresponding to the at least one extension address line; The test data bit width of the storage package module is equal to the data bit width of the memory modules; The address bit width of the memory modules is equal to the logarithm value of the depth of the memory modules with 2 as the base, the depth of the memory modules is equal to the depth of the target memory, and the data bit width of the memory modules is equal to 1 / N times the width of the target memory, N representing the number of the plurality of memory modules.

3. The memory device of claim 2, wherein, The storage device further comprises a plurality of timing registers, wherein: The timing registers are arranged between each interface of the test logic module and the storage package module, and the number of the timing registers is equal to the sum of 2, the test address bit width of the storage package module and the test data bit width of the storage package module.

4. The memory device of claim 1, wherein, The storage package module further comprises a first decoding module, wherein: The enable end of the first decoding module is used for receiving a chip selection enable signal; The input end of the first decoding module is connected with the at least one extension address line, and the output end of the first decoding module is used for outputting a plurality of read-write control signals, and the plurality of read-write control signals have a one-to-one correspondence with the plurality of memory modules.

5. The memory device of claim 4, wherein, The storage package module further comprises a plurality of first selection modules, and the output end of the first selection module is connected with the read-write enable port of the memory module; wherein: The first input end of the first selection module is used for receiving the read-write control signal, the second input end of the first selection module is used for receiving a first read-write enable signal, and the output end of the first selection module is used for outputting a second read-write enable signal to the memory module.

6. The memory device of claim 1, wherein, The test data line comprises a read test data line, and the storage package module further comprises a second decoding module, wherein: The enable end of the second decoding module is used for receiving a chip selection enable signal; The plurality of input ends of the second decoding module are connected with the read port of the plurality of memory modules one by one, and are used for receiving the respective read data signals of the plurality of memory modules. An output terminal of the second decoding module is connected with a reading terminal of the test logic module through at least one reading test data line, for transmitting the reading data signal of each memory module to the test logic module.

7. The memory device of claim 6, wherein, The test data line further comprises a writing test data line, and the storage package module further comprises a plurality of second selection modules and a plurality of third selection modules, wherein an output terminal of the second selection module is connected with a writing terminal of the memory module, and an output terminal of the third selection module is connected with an address terminal of the memory module; wherein: An enable terminal of the second selection module is used for receiving a test enable signal; a first input terminal of the second selection module is connected with the writing terminal of the test logic module through at least one writing test data line, for receiving a writing data test signal; a second input terminal of the second selection module is used for receiving a writing data function signal, and an output terminal of the second selection module is used for outputting a target writing data signal to the memory module; An enable terminal of the third selection module is used for receiving a test enable signal; a first input terminal of the third selection module is connected with the address terminal of the test logic module through at least one test address line, for receiving a test address signal; a second input terminal of the third selection module is used for receiving a function address signal, and an output terminal of the third selection module is used for outputting a target address signal to the memory module.

8. The memory device of any one of claims 1-7, wherein, The memory module comprises a plurality of memory blocks; In the case that the depth of the memory module is not equal to an integer power of 2, the size of the memory block satisfies the following two conditions: The size of the memory block is equal to an integer power of 2; The size of the memory block is divisible by the depth of the memory module.

9. The memory device of claim 8, wherein, The number of bits of the at least one extension address line is mapped between the xth bit and the x+yth bit of the corresponding test address line; Wherein, x represents the logarithm value of the size of the memory block with 2 as the base, and y represents the value of the number of the extension address lines minus 1.

10. A chip, characterized by The chip comprises the storage device as claimed in any one of claims 1 to 9.

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