Signal processing board card fault simulation equipment
By designing a fault simulation device for signal processing boards, and using FPGA and CPU chips to simulate faults, the problem that existing signal processing boards cannot fully simulate faults is solved, thereby improving the safety and detection efficiency of the boards and reducing maintenance time and costs.
Patent Information
- Application Number
- CN202423295362.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-31
- Publication Date
- 2025-11-18
- Estimated Expiration
- 2034-12-31
AI Technical Summary
Existing technologies lack effective means to comprehensively simulate faults in signal processing boards, which makes it impossible to guarantee their fault handling capabilities in real application scenarios, affecting the safety and stability of the boards.
Design a signal processing board fault simulation device, including a signal processing board under test, a communication board, and a driver board. Fault simulation is performed using an FPGA chip and a CPU chip, data transmission is performed using serial communication and a local bus, and fault location is assisted by LED display and CPU recording of work logs.
It improves the safety and reliability of signal processing boards in practical applications, increases detection efficiency, reduces maintenance time and costs, and helps to accurately locate the source of faults.
Smart Images
Figure CN223566140U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of signal processing, in particular to a signal processing board card fault simulation device. BACKGROUND
[0002] The signal processing board card lacks effective fault simulation means before being put into use, which leads to the inability to guarantee its fault handling capability in real application scenarios, and the fault handling capability of the board card can only be simulated through the front-end simulation test, and some simple faults, such as over-temperature, over-voltage, under-voltage and the like, are tested, and for some internal faults of the board card and abnormal data transmission between boards, the tester cannot simulate, which affects the safety and stability of the signal processing board card, and therefore it is necessary to design a signal processing board card fault simulation device to solve the problem. SUMMARY
[0003] To solve the above problems, the utility model discloses a signal processing board card fault simulation device, which comprises:
[0004] The signal processing board card, the communication board card and the drive board card, wherein,
[0005] The communication board card communicates with the signal processing board card to be tested through a serial communication interface;
[0006] The drive board card communicates with the signal processing board card to be tested through a local bus.
[0007] Further, the signal processing board card to be tested comprises:
[0008] An FPGA chip generates an abnormal input excitation signal in cooperation with a row pin to simulate faults of the board card to be tested, communicates with the drive board card through a local bus and communicates with the communication board card through a serial communication interface; the FPGA chip serves as a PCI slave device for reading and writing of a CPU chip of a host device;
[0009] A CPU chip communicates with the FPGA chip through a PCI bus, sends a read-write command, the read command is to read a related register of the FPGA chip, and the write command is a drive command for the drive board card;
[0010] A row pin is used to control the FPGA chip and simulate an abnormal input excitation signal.
[0011] Further, the communication board card comprises:
[0012] A communication data receiving module verifies and receives data from the signal processing board card to be tested;
[0013] A communication data sending module transmits data of the communication board card to the signal processing board card to be tested through a serial communication interface.
[0014] Further, the drive board card comprises:
[0015] A drive data receiving module receives data transmitted by the signal processing board under test through the local bus, processes the data from the signal processing board under test, and puts the data into RAM.
[0016] A drive module reads the drive command in the RAM, drives the 24-way drive circuit, and the drive circuit drives the external relay coil.
[0017] Further, the FPGA chip comprises:
[0018] An MSI data receiving module verifies and receives data transmitted by the communication board card, classifies the data after confirming that the data is transmitted without error, and transmits the data to a data processing module.
[0019] An MSI data sending module transmits the state information and fault information of the signal processing board under test to the communication board card through a serial communication interface.
[0020] The data processing module processes the received data and outputs various state information to an LED display module and a PCI module.
[0021] The LED drive module receives the state information from the data processing module and drives the on-off state of the corresponding LED.
[0022] The PCI module receives and executes the read-write command issued by the CPU chip through the PCI bus, receives the state information transmitted by the data processing module, and receives the data returned by the drive board card.
[0023] The fault simulation decoding module is used for converting the pin simulation input signal into a specific fault number, each fault code corresponds to a fault, and the output control signal is output to the module corresponding to the fault number to control the signal in the corresponding module.
[0024] Further, the CPU chip comprises:
[0025] The data read-write module issues a read-write command for the PCI slave device, which has a period of 200 ms.
[0026] The data recording module records the fault information in the log after reading the register of the FPGA, for the device manager to check.
[0027] Further, the FPGA chip is an XC7A series chip, and the CPU chip is an MPC8323E series processor.
[0028] The signal processing board fault simulation equipment can simulate various fault conditions of a single signal processing board, and can verify whether the board can be guided to a safe state in time when various faults occur, improve the safety, reliability and availability of the signal processing board in actual application, greatly improve the detection efficiency of the signal processing board before being put into use, and reduce the fault positioning time of maintenance personnel within a certain limit after the board is put into use, and assist the maintenance personnel to more accurately locate the fault source, avoid overall replacement of the module due to inaccurate positioning of the fault source, and save the board maintenance cost. BRIEF DESCRIPTION OF DRAWINGS
[0029] The drawings described herein are used to provide further understanding of the present application, and form a part of the present application, the illustrative embodiments of the present application and the description thereof are used to explain the present application, and do not constitute undue limitation on the present application. In the drawings:
[0030] Figure 1 It is a structural principle diagram of the utility model;
[0031] Figure 2 It is a structural principle diagram of the FPGA chip in the utility model. DETAILED DESCRIPTION
[0032] In order to make the technical solutions and advantages in the embodiments of the present application clearer and more apparent, the exemplary embodiments of the present application are further described in detail below with reference to the drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, and not all the embodiments. It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict.
[0033] In the description of the actual engineering case, "MSI" is a kind of serial communication interface, and the interface includes data line and clock line; "VME" in the text is a kind of local bus.
[0034] As shown in Figure 1 The signal processing board fault simulation equipment of the present application embodiment comprises: a signal processing board to be tested, a drive board and a communication board, the signal processing board to be tested comprises an FPGA chip, a CPU chip and a pin, the drive board comprises a data receiving module and a drive module, and the communication board comprises an MSI communication module composed of an MSI data sending module and an MSI data receiving module. Wherein:
[0035] FPGA chip is matched with pin (pin specification is 2.54mm pitch 2X8 vertical pin) to simulate the generation of various faults, and the fault simulation is carried out on the signal processing board to be tested; the chip model is XC7A series chip of AMD company, and main logic resources in the chip include: 101440 minimum logic units, 126800 CLB flip-flops, a total of 4860Kb BlockRAM, 6 groups of clock crystal oscillator (1MMCM+1PLL), 300 external IO interface, 240 on-chip DSP, 8-way 6.6GGT transceiver, supports multi-channel PCIe Gen2.0 and high-speed data transmission, and supports JTAG mode, can carry out online debugging, and solidifies bit file into flash, and is separated from debugging tool;
[0036] The CPU chip is used as a PCI host device to read and write the FPGA chip as a slave device, and the CPU chip comprises:
[0037] The data read-write module issues a read-write command for the PCI slave device, and has a periodicity of reading and writing once every 200ms;
[0038] The data recording module records the fault information in the log after reading and writing, so that the device manager can check the fault information;
[0039] The drive board card receives the drive command transmitted by the FPGA chip through the local bus, and drives the corresponding circuit;
[0040] The communication board card communicates with the signal processing board to be tested through a serial communication interface.
[0041] As shown in Figure 2 The FPGA chip comprises:
[0042] The fault simulation decoding module cooperates with the pin (pin specification is 2.54mm pitch 2X8 vertical pin) outside the chip, and 8-bit input signals are generated at the pin end, one of which (corresponding to pin 15-16) is used as a fault simulation effective signal, and the other seven bits (corresponding to pin 1-14) are used as fault original code, up to 127 kinds of fault codes can be translated, and all the translated fault codes are transmitted to each module of the FPGA chip according to the requirement, when the fault simulation effective signal is valid, the fault code controls the abnormal input signal of the corresponding module, wherein the simulation of the signal abnormality is generally a square wave signal, and the module controlled by the fault code includes the PCI module, the data processing module, the MSI data receiving module and the MSI data sending module;
[0043] The PCI module is used for receiving and executing the read-write command transmitted by the CPU chip through the PCI bus, and part of the related command related to the drive board card is connected to the VME host, and the PCI module can be divided into four modules:
[0044] PCI slave interface module, receiving and storing data transmitted from processing module for CPU read and write;
[0045] PCI user interface module, receiving read and write commands from CPU chip, if the command is related to drive board card, then the command is transmitted to PCI_VME adapter module, otherwise the command is directly read and written to PCI slave interface module;
[0046] PCI_VME adapter module, converting read and write commands transmitted by PCI user interface into data format required by VME bus, and transmitting data to VME host module;
[0047] VME host module, transmitting data transmitted by adapter module to drive board card according to format specified by VME bus.
[0048] MSI data receiving module, receiving clock and data transmitted by communication board card through MSI channel, which is divided into two parts:
[0049] Clock line detection module, responsible for detecting whether the clock line of MSI channel is normal;
[0050] Data line detection module, responsible for detecting whether the data line of MSI channel is normal.
[0051] MSI data sending module, sending main data of signal processing board card to communication board card through MSI channel, which is divided into two parts:
[0052] State reporting module, concentrating processing of state data to be transmitted to communication board card, and transmitting data to data format standardization module;
[0053] Data format standardization module, transmitting original data from state reporting module to communication board card according to standard MSI data transmission format, cooperating with clock line signal.
[0054] Data processing module, processing received data, and judging whether there is a fault, if there is a fault, transmitting fault information to LED display module and PCI register module respectively;
[0055] LED drive module, receiving main data from data processing module, driving the on-off state of corresponding LED, main LED lights include: VME communication indicator, MSI communication indicator, fault light, power indicator.
[0056] In summary, the signal processing board card fault simulation equipment can simulate various fault conditions of a single signal processing board card, through observing the board card running condition after fault simulation, LED lamp display and work log recorded at the CPU end, whether the board card can be directed to a safe state in time when various faults occur can be verified, the safety, reliability and availability of the signal processing board card in actual application are improved, the detection efficiency of the signal processing board card before being put into use is greatly improved; after the board card is put into use, the equipment can reduce the fault positioning time of maintenance personnel within a certain limit, and assist the maintenance personnel to more accurately locate the fault source, avoid the overall replacement of the module due to the failure to accurately locate the fault source, and save the board card maintenance cost.
[0057] Although preferred embodiments of the application have been described, those skilled in the art will be able to make additional modifications and variations to the described embodiments without departing from the spirit and scope of the application. Accordingly, the appended claims are intended to encompass all such modifications and variations as falling within the scope of the application.
[0058] Obviously, those skilled in the art can make various modifications and variations to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application also intends to include these modifications and variations.
Claims
1. A signal processing board fault simulation device, characterized in that, include: The signal processing board, communication board, and driver board under test, among which, The communication board communicates with the signal processing board under test via a serial communication interface; The driver board communicates with the signal processing board under test via a local bus.
2. The signal processing board fault simulation device according to claim 1, characterized in that, The signal processing board under test includes: The FPGA chip, in conjunction with the pin header, generates abnormal input excitation signals to simulate faults in the board under test. It communicates with the driver board via a local bus and with the communication board via a serial communication interface. The FPGA chip also acts as a PCI slave device for the master device's CPU chip to read and write. The CPU chip communicates with the FPGA chip via the PCI bus, sending read and write commands. The read command reads the relevant registers of the FPGA chip, while the write command is a driver command for the driver board. Pin headers are used to control FPGA chips and simulate abnormal input excitation signals.
3. The signal processing board fault simulation device according to claim 1, characterized in that, The communication board includes: The communication data receiving module verifies and receives data from the signal processing board under test. The communication data transmission module transmits the data from the communication board to the signal processing board under test via a serial communication interface.
4. The signal processing board fault simulation device according to claim 1, characterized in that, The driver board includes: The driver data receiving module receives data transmitted from the signal processing board under test via the local bus, processes the data from the signal processing board under test, and puts it into RAM. The driver module reads the driver commands from RAM and drives 24 driver circuits, which in turn drive external relay coils.
5. The signal processing board fault simulation device according to claim 2, characterized in that, The FPGA chip includes: The MSI data receiving module verifies and receives the data transmitted by the communication board, classifies it after confirming that the transmission is correct, and then transmits it to the data processing module. The MSI data transmission module transmits the status and fault information of the signal processing board under test to the communication board through the serial communication interface. The data processing module processes the received data and outputs various status information to the LED display module and the PCI module. The LED driver module receives status information from the data processing module and drives the corresponding LEDs to turn on or off. The PCI module receives and executes read and write commands issued by the CPU chip through the PCI bus, receives status information transmitted by the data processing module, and receives data returned by the driver board. The fault simulation decoding module is used to convert the pin analog input signal into a specific fault number. Each fault code corresponds to a fault. The module outputs a control signal to the module corresponding to the fault number to control the signals in the corresponding module.
6. The signal processing board fault simulation device according to claim 2, characterized in that, The CPU chip includes: The data read / write module issues read / write commands to the PCI slave device periodically, performing a read / write operation every 200ms. The data logging module, after reading the FPGA registers, records fault information in the log for equipment administrators to view.
7. The signal processing board fault simulation device according to claim 2, characterized in that: The FPGA chip is an XC7A series chip; The CPU chip is an MPC8323E series processor.