Driving hardware interlocking circuit
By designing two isolated drive circuits and an RC series hysteresis control circuit in the switching power supply drive circuit, the problem of simultaneous MOSFET operation under harsh conditions was solved, hardware interlocking was achieved, and the reliability of the power supply was improved.
Patent Information
- Application Number
- CN202423049139.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-11
- Publication Date
- 2025-11-18
- Estimated Expiration
- 2034-12-11
AI Technical Summary
In switching power supply drive circuits, under harsh conditions, the main circuit current changes rapidly and the transient current spike is large, which can easily lead to controller misjudgment and simultaneous opening of MOSFETs, causing product damage.
A hardware interlock circuit for driving is designed, which adopts two isolated driving circuits. Each circuit consists of a logic control circuit, an isolation driving IC, a primary-side filter capacitor, a current-limiting resistor, and an RC series hysteresis control circuit. Through hardware interlocking and hysteresis control, the two driving circuits are prevented from being turned on at the same time.
Hardware interlocking of the drive circuit under harsh conditions was achieved, preventing simultaneous operation of MOSFETs and improving the reliability and stability of the power supply.
Smart Images
Figure CN223567521U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to circuit technical field especially relates to a drive hardware interlock circuit. BACKGROUND
[0002] In the existing switching power supply drive circuit, the power PFC DRI H (PFC DRI L) is the signal of driving, generally is sent by the main control IC of mainboard and is connected to the PFC DRI H (PFC DRI L) pin on the power through the power connection line.
[0003] When the main control IC of mainboard controls this signal to be high level, the output of drive IC changes from low level to high level, makes the MOS connected to the secondary side of drive IC open, when the main control IC of mainboard controls this signal to change from high level to low level, the output of drive IC is low level, makes the MOS connected to the secondary side of drive IC drive voltage to reduce to zero, and shuts off MOS. In the actual use of the circuit of bridge structure topology application, the application condition can have the change of big load jump, input voltage drop, surge impact, input voltage non-sinusoidal wave and other complex and diverse adverse conditions, these adverse conditions usually make the main circuit current change rate fast, transient current peak value big, product detection signal coupling noise big, and easily cause controller misjudgment.
[0004] Therefore, it is necessary to provide a drive hardware interlock circuit, increase drive interlock connection and hysteresis control, ensure that the drive can realize hardware interlock. Utility model content
[0005] The utility model discloses a drive hardware interlock circuit relates to server switching power supply, especially relates to the circuit application of requiring hardware drive can interlock, and it can effectively solve the technical problem in the background art.
[0006] To achieve the above object, the technical scheme of the utility model is:
[0007] A kind of drive hardware interlock circuit, including port PFC_DRI_H and port PFC_DRI_L;The port PFC_DRI_H connects one end of resistance R0, the other end of the resistance R0 is connected with the negative terminal of diode D1 and one end of resistance R1, the positive terminal of the diode D1 is connected with the other end of the resistance R1, one end of resistance R4 and the base of triode Q1, the collector of the triode Q1 is connected with the pin 3 of drive chip U1 and one end of resistance R3, the other end of the resistance R3 is connected with one end of capacitor C5, the pin 1 of the drive chip U1 is connected with port VCP, one end of resistance R2 and one end of capacitor C2, the pin 2 of the drive chip U1 is connected with the other end of the resistance R2, the pin 4 of the drive chip U1 is connected with the other end of the capacitor C5, the other end of the capacitor C2, the emitter of the triode Q1, the other end of the resistance R4 and port AGND, the pin 5 of the drive chip U1 is connected with one end of capacitor C1, one end of capacitor C3 and port VPFC_H, the other end of the capacitor C3 is connected with port DRIVER_HL and one end of capacitor C4, the pin 6 of the drive chip U1 is connected with port DRIVER_H, the pin 8 of the drive chip U1 is connected with the other end of the capacitor C1, the other end of the capacitor C4 and port-3VH;The port PFC_DRI_L is connected with one end of resistance R12, the other end of the resistance R12 is connected with the negative terminal of diode D2 and one end of resistance R7, the positive terminal of the diode D2 is connected with the other end of the resistance R7, one end of resistance R13 and the base of triode Q3, the collector of the triode Q3 is connected with the pin 3 of drive chip U2 and one end of resistance R9, the other end of the resistance R9 is connected with one end of capacitor C11, the pin 1 of the drive chip U2 is connected with port VCP, one end of resistance R8 and one end of capacitor C8, the pin 2 of the drive chip U2 is connected with the other end of the resistance R8, the pin 4 of the drive chip U2 is connected with the other end of the capacitor C11, the other end of the capacitor C8, the emitter of the triode Q3, the other end of the resistance R13 and port AGND, the pin 5 of the drive chip U2 is connected with one end of capacitor C7, one end of capacitor C9 and port VPFC_L, the other end of the capacitor C9 is connected with port DRIVER_LL and one end of capacitor C10, the pin 6 of the drive chip U2 is connected with port DRIVER_L, the pin 8 of the drive chip U2 is connected with the other end of the capacitor C7, the other end of the capacitor C10 and port-3VL;The pin 2 of the drive chip U1 is connected with the pin 3 of the drive chip U2, the pin 3 of the drive chip U1 is connected with the pin 2 of the drive chip U2.
[0008] Specifically, a kind of driving hardware interlock circuit is disclosed, including two-way isolation driving circuit, interlock signal connection line.Each way isolation driving circuit is by logic control circuit, one isolation driving IC, one driving IC primary side filter capacitor, one driving IC primary side current limiting resistor, RC series hysteresis control circuit, hardware interlock connection line composition.Each way driving circuit's primary side logic control circuit includes current limiting resistor, the DR current limiting discharge circuit of one diode reverse parallel one resistance, triode BE extreme pull-down resistance, one triode.Each way driving circuit in primary side logic control circuit current limiting resistor R0 (R12) first end connects driving signal level PFC_DRI_H (PFC_DRI_L), second end connects DR current limiting discharge circuit diode D1 (D2) cathode, DR current limiting discharge circuit diode anode connects triode Q1 (Q2) base, and is connected with triode BE extreme pull-down resistance R4 (R13) first end, triode BE extreme pull-down resistance second end connects triode emitter and is connected to driving IC U1 (U2) primary side reference ground AGND and driving IC PIN4;Driving IC primary side power supply VCP connects IC primary side filter capacitor C2 (C8) first end and IC primary side power supply PIN1 (VCC1) and driving IC primary side current limiting resistor R2 (R8) first end, driving IC primary side filter capacitor second end connects AGND, driving IC primary side current limiting resistor second end and driving IC PIN2 (IN+) are connected, driving IC primary side PIN3 (IN-) connect triode collector in logic control circuit, simultaneously driving IC primary side PIN3 (IN-) connect RC series circuit resistance R3 (R9) first end, RC series circuit resistance second end connects RC series circuit capacitor C5 (C11) first end, RC series circuit capacitor second end connects driving IC primary side reference ground AGND.Hardware interlock connection line first way driving IC primary side input positive PIN2 (IN+) is connected to the connection of second way driving IC primary side input negative PIN3 (IN-), second way driving IC primary side input positive PIN2 (IN+) is connected to the first way driving IC primary side input negative PIN3 (IN-), the utility model can be hardware interlock drive, meet two-way driving level same open output interlock not output drive circuit demand.
[0009] As a preferred improvement of the utility model: the port PFC_DRI_H and the port PFC_DRI_L are connected with a controller.
[0010] As a preferred improvement of the utility model: the port DRIVER_H is the voltage output end of the drive MOS tube one that the drive chip U1 outputs, connects the drive circuit input end of MOS tube one, the port DRIVER_HL connects the ground end of MOS tube one, the port DRIVER_L is the voltage output end of the drive MOS tube two that the drive chip U2 outputs, connects the drive circuit input end of MOS tube two, the port DRIVER_LL connects the ground end of MOS tube two.
[0011] As a preferred improvement of the utility model: the port VCP connects power supply.
[0012] As a preferred improvement of the utility model: the port VPFC_H connects positive voltage supply, and the port -3VH connects negative voltage supply.
[0013] As a preferred improvement of the utility model: the port VPFC_L connects positive voltage supply, and the port -3VL connects negative voltage supply.
[0014] As a preferred improvement of the utility model: the drive chip U1 and the drive chip U2 are single-channel isolated gate drivers with clamping function, and the pin 7 of the drive chip U1 and the drive chip U2 corresponds to the gate of the MOS tube driven by the drive chip U1 and the drive chip U2 respectively.
[0015] As a preferred improvement of the utility model: the model of the drive chip U1 and the drive chip U2 is NSI6601MC-DSPR or UCC5350MCDR.
[0016] The utility model has the advantages as follows:
[0017] Two-way drive interlocking can avoid the MOS of driving to open simultaneously, so that the product will not be damaged due to simultaneous opening, and the RC series hysteresis circuit is introduced to control the opening delay of driving, and appropriate RC parameters can delay the opening time of the other way without dead zone, avoid driving simultaneous opening, and meet the driving hardware interlocking application of power supply. BRIEF DESCRIPTION OF DRAWINGS
[0018] In order to more clearly illustrate the technical scheme in the embodiment of the utility model, the drawings needed to be used in the embodiment description will be briefly introduced as follows, and obviously, the drawings in the following description are only some embodiments of the utility model, and other drawings can be obtained according to these drawings without paying creative labor for those skilled in the art, wherein:
[0019] Figure 1 It is a schematic diagram of a drive circuit;
[0020] Figure 2The utility model discloses a schematic diagram of driving hardware interlocking circuit. DETAILED DESCRIPTION
[0021] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application.
[0022] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present application are only used to explain the relative positional relationship, movement condition, etc. between components in a certain posture (as shown in the drawings), and if the certain posture changes, the directional indications also change accordingly.
[0023] In addition, the description such as "first", "second" and the like in the present application is only for the purpose of description, and cannot be understood as indicating or implying the relative importance of the indicated technical features or implicitly indicating the number of the indicated technical features. Therefore, the features limited by "first", "second" can explicitly or implicitly include at least one of the features. In the description of the present application, the meaning of "multiple" is at least two, for example, two, three, etc., unless otherwise specifically limited.
[0024] In the present application, unless otherwise specifically defined and limited, the terms "connection", "fixing" and the like should be understood in a broad sense, for example, "fixing" can be fixed connection, or detachable connection, or integral; can be mechanical connection, or electrical connection; can be direct connection, or indirect connection through intermediate medium; can be the internal communication of two elements or the interaction relationship between two elements, unless otherwise specifically limited. For a person of ordinary skill in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.
[0025] In addition, the technical solutions of each embodiment of the present application can be combined with each other, but it must be based on the fact that a person of ordinary skill in the art can realize it, and when the combination of technical solutions appears contradictory or unachievable, it should be considered that the combination of technical solutions does not exist, and is not within the protection scope required by the present application.
[0026] Please refer to Figure 1As shown, U1, U2 are driving ICs, in each driving circuit, the first end of the current limiting resistor R0 (R12) in the primary side logic control circuit is connected to the driving signal level PFC_DRI_H (PFC_DRI_L), the second end of the current limiting resistor R0 (R12) is connected to the negative electrode of the diode (D1; D2) in the DR current limiting discharge circuit (D1 / / R1; D2 / / R7), the positive electrode of the diode (D1; D2) in the DR current limiting discharge circuit (D1 / / R1; D2 / / R7) is connected to the base of the transistor (Q1; Q3) and the first end of the BE pull-down resistor (R4; R13), the second end of the BE pull-down resistor (R4; R13) is connected to the emitter of the transistor (Q1; Q3) and the primary side reference ground AGND of the driving IC (U1; U2) and the PIN4 of the driving IC, the primary side power supply VCP of the driving IC is connected to the first end of the primary side filter capacitor (C2; C8) and the PIN1 (VCC1) of the driving IC and the first end of the first current limiting resistor (R2; R8) and the second current limiting resistor (R101; R102) of the driving IC, the second end of the first current limiting resistor (R2; R8) of the driving IC is connected to the PIN2 (IN+) of the driving IC, the second end of the second current limiting resistor (R101; R102) of the driving IC is connected to the PIN3 (IN-) of the driving IC and the collector of the transistor in the logic control circuit. In actual application, a high level is input to the driving signal level PFC_DRI_H (PFC_DRI_L), the transistor (Q1; Q3) in the logic control circuit is turned on, the PIN3 (IN-) of the driving IC (U1; U2) is pulled low, the PIN6 of the driving IC (U1; U2) outputs a high level to make the driven MOS conduct, when the input of the driving signal level PFC_DRI_H (PFC_DRI_L) changes from high level to low level, the transistor (Q1; Q3) in the logic control circuit is turned off, the voltage of the PIN3 (IN-) of the driving IC (U1; U2) rises, the PIN6 of the driving IC (U1; U2) outputs a low level to make the driven MOS turn off, and the switching control of the MOS is realized in this way. In the application of bridge architecture topology, the driving controlled by the driving signal level PFC_DRI_H is called upper road, the driving controlled by the driving signal level PFC_DRI_L is called lower road, and the two driving cannot be high level at the same time, otherwise the upper and lower main MOS will be common and the machine will be blown up, therefore the dead time is usually set for the upper and lower road driving to avoid such problems. However, in the actual use of the circuit in the application of bridge architecture topology, there are various complex and harsh conditions such as large load jump change, input voltage drop, surge impact and non-sinusoidal input voltage. These harsh conditions usually easily cause the fast change rate of the main circuit current, the large transient current peak value, the large coupling noise of the product detection signal and the easy misjudgment of the controller.As the upper road drive signal level PFC_DRI_H is high, the lower road drive signal level PFC_DRI_L is abnormally outputted high in the misjudgment case, and the two MOS are opened simultaneously, and the product is blown.
[0027] Therefore, in order to improve the reliability of the power supply under harsh conditions, the drive interlocking drive drive end MOS cannot be opened simultaneously in the hardware drive when the controller sets the appropriate dead zone. Figure 2 As shown in the figure, the utility model provides a drive hardware interlocking circuit, including port PFC_DRI_H and port PFC_DRI_L, the port PFC_DRI_H and the port PFC_DRI_L connect controller. The one end of resistance R0 is connected with the port PFC_DRI_H, the other end of resistance R0 is connected with the negative end of diode D1 and the one end of resistance R1, the positive end of diode D1 is connected with the other end of resistance R1, the one end of resistance R4 and the base of triode Q1, the collector of triode Q1 is connected with the pin 3 of drive chip U1 and the one end of resistance R3, the other end of resistance R3 is connected with the one end of capacitor C5, the pin 1 of drive chip U1 is connected with port VCP, the one end of resistance R2 and the one end of capacitor C2, the pin 2 of drive chip U1 is connected with the other end of resistance R2, the pin 4 of drive chip U1 is connected with the other end of capacitor C5, the other end of capacitor C2, the emitter of triode Q1, the other end of resistance R4 and port AGND, the pin 5 of drive chip U1 is connected with the one end of capacitor C1, the one end of capacitor C3 and port VPFC_H, the other end of capacitor C3 is connected with port DRIVER_HL and the one end of capacitor C4, the pin 6 of drive chip U1 is connected with port DRIVER_H, the pin 8 of drive chip U1 is connected with the other end of capacitor C1, the other end of capacitor C4 and port -3VH, port VCP is connected with power supply, port DRIVER_H is connected with the input end of the drive circuit of MOS tube one, port DRIVER_HL is connected with the ground end of MOS tube one, port VPFC_H is connected with positive voltage power supply, port -3VH is connected with negative voltage power supply.
[0028] One end of the port PFC DRI L is connected with one end of the resistance R12, the other end of the resistance R12 is connected with the negative end of the diode D2 and one end of the resistance R7, the positive end of the diode D2 is connected with the other end of the resistance R7, one end of the resistance R13 and the base of the triode Q3, the collector of the triode Q3 is connected with pin 3 of the driving chip U2 and one end of the resistance R9, the other end of the resistance R9 is connected with one end of the capacitor C11, pin 1 of the driving chip U2 is connected with the port VCP, one end of the resistance R8 and one end of the capacitor C8, pin 2 of the driving chip U2 is connected with the other end of the resistance R8, pin 4 of the driving chip U2 is connected with the other end of the capacitor C11, the other end of the capacitor C8, the emitter of the triode Q3, the other end of the resistance R13 and the port AGND, pin 5 of the driving chip U2 is connected with one end of the capacitor C7, one end of the capacitor C9 and the port VPFC L, the other end of the capacitor C9 is connected with the port DRIVER LL and one end of the capacitor C10, pin 6 of the driving chip U2 is connected with the port DRIVER L, pin 8 of the driving chip U2 is connected with the other end of the capacitor C7, the other end of the capacitor C10 and the port -3VL, pin 2 of the driving chip U1 is connected with pin 3 of the driving chip U2, pin 3 of the driving chip U1 is connected with pin 2 of the driving chip U2. The port DRIVER L is connected with the input end of the driving circuit of the MOS tube two, the port DRIVER LL is connected with the ground end of the MOS tube two, the port VPFC L is connected with the positive voltage power supply, the port -3VL is connected with the negative voltage power supply. The driving chip U1 and the driving chip U2 are single-channel isolated gate drivers with clamping function, preferably, the model of the driving chip U1 and the driving chip U2 is NSI6601MC-DSPR or UCC5350MCDR. The circuit adds driving interlocking connection and hysteresis control, which ensures that the driving can realize hardware interlocking.
[0029] A kind of drive hardware interlock circuit, including two-way isolation drive circuit, interlock signal connection line.Each way isolation drive circuit is by logic control circuit, an isolation drive IC, a drive IC primary side filter capacitor, a drive IC primary side current-limiting resistance, RC series circuit, three drive IC secondary side filter capacitors, drive signal level PFC_DRI_H (PFC_DRI_L), drive IC primary side power supply VCP, drive IC primary side ground AGND, drive IC secondary side power supply VPFC_H (VPFC_L), drive IC secondary side negative voltage supply-3V_H (-3V_L), drive voltage output DRIVER_H (DRIVER_L), drive voltage ground DRIVER_HL (DRIVER_LL) Composition.Hysteresis control is RC series hysteresis circuit R3 and C5, R9 and C11.The drive chip U1 and the drive chip U2 are single-channel isolated gate driver with clamping function (CLAMP, pin 7) The pin 7 of drive chip U1 and drive chip U2 is connected with the drive circuit input end of MOS tube driven by it respectively, when drive IC primary and secondary VCC1 and VCC2 power supply all meet the voltage range of working demand, the input and output working characteristics of IC are PIN2 (IN+) High level, PIN3 (IN-) Low level, then IC output PIN6 is high level;PIN2 (IN+) Low level, PIN3 (IN-) Whether high level or low level, then IC output PIN6 is low level.
[0030] Embodiment one
[0031] The first drive circuit (upper drive) comprises a DR current limiting discharge circuit composed of current limiting resistor R0, D1 and R1, a logic control circuit composed of transistor BE pull-down resistor R4 and transistor Q1, drive IC U1, drive IC primary side power supply filter capacitor C2 and drive IC primary side current limiting resistor R2. The first end of current limiting resistor R0 is connected to drive signal level PFC_DRI_H, the second end is connected to the negative electrode of D1, the positive electrode of D1 is connected to the base electrode of transistor Q1 and the first end of transistor BE pull-down resistor R4, R1 and D1 are connected in parallel, the second end of transistor BE pull-down resistor R4 is connected to the emitter electrode of transistor Q1 and is connected to the primary side reference ground AGND of drive IC U1 and drive IC PIN4; the first end of drive IC primary side power supply VCP is connected to IC primary side filter capacitor C2, drive IC primary side power supply PIN1 (VCC1) and drive IC primary side current limiting resistor R2, the second end of drive IC primary side current limiting resistor R2 is connected to drive IC PIN2 (IN+), drive IC primary side PIN3 (IN-) is connected to the collector electrode of transistor Q1 in the logic control circuit, at the same time, drive IC primary side PIN3 (IN-) is connected to the first end of RC series circuit resistor R3, the second end of RC series circuit resistor R3 is connected to the first end of RC series circuit capacitor C5, and the second end of RC series circuit capacitor C5 is connected to the primary side reference ground AGND of drive IC.
[0032] The second drive circuit (lower drive) comprises a DR current limiting discharge circuit composed of current limiting resistor R12, D2 and R7, a logic control circuit composed of transistor BE pull-down resistor R13 and transistor Q3, drive IC U2, drive IC primary side power supply filter capacitor C8 and drive IC primary side current limiting resistor R8. The first end of current limiting resistor R12 is connected to drive signal level PFC_DRI_L, and the second end is connected to the negative electrode of D2, the positive electrode of D2 is connected to the base electrode of transistor Q3 and the first end of transistor BE pull-down resistor R13, R7 and D2 are connected in parallel, the second end of transistor BE pull-down resistor R13 is connected to the emitter electrode of transistor Q3, and is connected to the primary side reference ground AGND of drive IC U2 and drive IC PIN4; the first end of drive IC primary side power supply VCP is connected to IC primary side filter capacitor C8, drive IC primary side power supply PIN1 (VCC1) and drive IC primary side current limiting resistor R8, the second end of drive IC primary side current limiting resistor R8 is connected to drive IC PIN2 (IN+), drive IC primary side PIN3 (IN-) is connected to the collector electrode of transistor Q1 in the logic control circuit, at the same time, drive IC primary side PIN3 (IN-) is connected to the first end of RC series circuit resistor R9, the second end of RC series circuit resistor R9 is connected to the first end of RC series circuit capacitor C11, and the second end of RC series circuit capacitor C11 is connected to the primary side reference ground AGND of drive IC.
[0033] The first route driving IC U1 original side input positive PIN2 (IN+) is connected to the second route driving IC U2 original side input negative PIN3 (IN-), and the second route driving IC U2 original side input positive PIN2 (IN+) is connected to the first route driving IC U1 original side input negative PIN3 (IN-). The utility model discloses the above hardware interlocking connection, and the RC circuit of R3 and C5 is added to the upper route to carry out the hysteresis control, and the RC series hysteresis circuit control of R9 and C11 is added to the lower route, to realize the function of the driving hardware interlocking circuit.
[0034] When the upper route driving signal PFC_DRI_H is high level first, Q1 is turned on, U1 PIN3 (IN-) and U2 PIN2 (IN+) are pulled low, U1 works, and U1 PIN6 outputs high level to drive MOS when the interlocking connection is added, and the lower route driving signal is high level again under the condition that the upper route is opened, Q3 is turned on, Q3 pulls U1 PIN2 (IN+) low rapidly, U1 does not work, and U1 PIN6 has no output, U2 PIN2 (IN+) is pulled low due to the fact that Q1 is in the turned-on state under the condition that the upper route PFC_DRI_H is high level, although U2 PIN3 (IN-) is pulled low due to the fact that Q3 is turned on, U2 also has no output because U2 PIN (IN+) is low at this time, the lower route MOS end has no drive, and the two routes have no output under the condition that the two driving signals PFC_DRI_H and PFC_DRI_L are high level, and the hardware interlocking is realized.
[0035] When the upper route driving PFC_DRI_H is changed from high to low at the same time that the lower route driving PFC_DRI_L is changed from low to high without setting the dead zone delay switch, Q1 is just in the cut-off state and Q3 is in the turned-on state at this time, U1 PIN2 (IN+) is pulled low by Q3, U1 PIN3 (-) is released and rises by Q1, and the voltage of U1 PIN6 changes from high to low, U2 PIN2 (IN+) is released by Q1, U2 PIN2 (IN-) is pulled low by Q3, and the voltage of U2 PIN6 changes from low to high, that is, the upper route MOS driving voltage is reduced at the same time that the lower route driving voltage rises, and the intersection of them is about 1 / 2Vg (half of the driving voltage amplitude) at this time, if 1 / 2Vg is greater than the complete cut-off threshold of the driving MOS and greater than the minimum opening threshold of the driving MOS, the upper and lower route driving MOSs are commonly connected in this case.
[0036] In order to avoid the common problem of up and down road drive without dead zone, the up road increases R3 and C5 RC series circuit to do delay control, and the down road increases R9 and C11 RC series delay circuit control. When the two-way drive does not set the dead zone delay switch, the up road drive PFC_DRI_H changes from high to low at the same time, and the down road drive PFC_DRI_L changes from low to high. At this time, Q1 is just in the off state and Q3 is in the on state; U1 PIN2(IN+) is quickly pulled down by Q3, U1 PIN3(-) is released and raised by Q1, and U1 PIN6 voltage changes from high to low; and U2 PIN2(IN-) is quickly pulled down by Q3, and U2 PIN2(IN+) is released by Q1. Since U2 PIN2(IN+) and U1 PIN3(IN-) are interlocked, U1 PIN3(IN-) is connected with R3 in series with C5 and then connected with AGND, when Q1 is off and U2 PIN2(IN+) and U1 PIN3(IN-) are released, due to the existence of C5 in R3 in series with C5, the release time of U2 PIN2(IN+) and U1 PIN3(IN-) by Q1 will be slow, and the output of U2 PIN6 will be delayed. By setting the capacitance to a suitable value, the voltage of U1 PIN6 of the up road can be completely delayed to zero, and the voltage of U2 can start to rise from zero, thereby avoiding the possibility of driving cross-on. It should be further pointed out that other components can be used to achieve the above effects, which should be within the inventive concept of the utility model, and should be within the protection scope of the utility model.
[0037] The drive hardware interlocking circuit of the above embodiment of the utility model can avoid the MOS on of the drive by two-way drive interlocking, so that the product will not be damaged due to on. At the same time, the RC series delay circuit is introduced to do the on delay control of the drive, and the appropriate RC parameters can delay the on time of the other way without dead zone, avoid the on of the drive, and meet the drive hardware interlocking application of the power supply.
[0038] Although the embodiments of the utility model have been disclosed as above, they are not limited to the application listed in the specification and the embodiments, and can be fully applied to various fields suitable for the utility model. For those skilled in the art, other modifications can be easily realized, and therefore the utility model is not limited to specific details and the figures shown and described herein without departing from the general concept defined by the claims and the equivalent scope.
Claims
1. A drive hardware interlock circuit, characterized by: The port PFC_DRI_H and the port PFC_DRI_L are connected to a controller. The port PFC_DRI_H is connected to one end of a resistor R0, the other end of the resistor R0 is connected to a negative end of a diode D1 and one end of a resistor R1, a positive end of the diode D1 is connected to the other end of the resistor R1, one end of a resistor R4 and a base of a transistor Q1, a collector of the transistor Q1 is connected to a pin 3 of a driving chip U1 and one end of a resistor R3, the other end of the resistor R3 is connected to one end of a capacitor C5, a pin 1 of the driving chip U1 is connected to a port VCP, one end of a resistor R2 and one end of a capacitor C2, a pin 2 of the driving chip U1 is connected to the other end of the resistor R2, a pin 4 of the driving chip U1 is connected to the other end of the capacitor C5, the other end of the capacitor C2, an emitter of the transistor Q1, the other end of the resistor R4 and a port AGND, a pin 5 of the driving chip U1 is connected to one end of a capacitor C1, one end of a capacitor C3 and a port VPFC_H, the other end of the capacitor C3 is connected to a port DRIVER_HL and one end of a capacitor C4, a pin 6 of the driving chip U1 is connected to a port DRIVER_H, a pin 8 of the driving chip U1 is connected to the other end of the capacitor C1, the other end of the capacitor C4 and a port -3VH. The port PFC_DRI_L is connected to one end of a resistor R12, the other end of the resistor R12 is connected to a negative end of a diode D2 and one end of a resistor R7, a positive end of the diode D2 is connected to the other end of the resistor R7, one end of a resistor R13 and a base of a transistor Q3, a collector of the transistor Q3 is connected to a pin 3 of a driving chip U2 and one end of a resistor R9, the other end of the resistor R9 is connected to one end of a capacitor C11, a pin 1 of the driving chip U2 is connected to a port VCP, one end of a resistor R8 and one end of a capacitor C8, a pin 2 of the driving chip U2 is connected to the other end of the resistor R8, a pin 4 of the driving chip U2 is connected to the other end of the capacitor C11, the other end of the capacitor C8, an emitter of the transistor Q3, the other end of the resistor R13 and a port AGND, a pin 5 of the driving chip U2 is connected to one end of a capacitor C7, one end of a capacitor C9 and a port VPFC_L, the other end of the capacitor C9 is connected to a port DRIVER_LL and one end of a capacitor C10, a pin 6 of the driving chip U2 is connected to a port DRIVER_L, a pin 8 of the driving chip U2 is connected to the other end of the capacitor C7, the other end of the capacitor C10 and a port -3VL. The pin 2 of the driving chip U1 is connected to the pin 3 of the driving chip U2, and the pin 3 of the driving chip U1 is connected to the pin 2 of the driving chip U2.
2. The drive hardware interlock circuit of claim 1, wherein: The port PFC_DRI_H and the port PFC_DRI_L are connected to a controller.
3. The drive hardware interlock circuit of claim 1, wherein: The port DRIVER_H is a voltage output end of the driving chip U1 outputting a driving MOS tube 1, and is connected to a driving circuit input end of the MOS tube 1; the port DRIVER_HL is connected to a ground end of the MOS tube 1; the port DRIVER_L is a voltage output end of the driving chip U2 outputting a driving MOS tube 2, and is connected to a driving circuit input end of the MOS tube 2; and the port DRIVER_LL is connected to a ground end of the MOS tube 2.
4. The drive hardware interlock circuit of claim 1, wherein: The port VCP is connected to a power supply.
5. The drive hardware interlock circuit of claim 1, wherein: The port VPFC_H is connected to a positive voltage power supply, and the port -3VH is connected to a negative voltage power supply.
6. The drive hardware interlock circuit of claim 1, wherein: The port VPFC_L is connected to a positive voltage power supply, and the port -3VL is connected to a negative voltage power supply.
7. The drive hardware interlock circuit of claim 1, wherein: The driving chip U1 and the driving chip U2 are single-channel isolated gate drivers with a clamping function, and the pin 7 of the driving chip U1 and the pin 7 of the driving chip U2 correspond to the gate of the MOS tube driven thereby, respectively.
8. The drive hardware interlock circuit of claim 1, wherein: The model of the driving chip U1 and the driving chip U2 is NSI6601MC-DSPR or UCC5350MCDR.