Miniaturized ADS-B terminal

Abstract

The utility model discloses a miniaturized ADS-B (Automatic Dependent Surveillance-Broadcast) terminal, which comprises an ADS-B transceiver module and an omnidirectional antenna, the ADS-B transceiver module comprises a digital processing part, a radio frequency processing part, a clock part and a power supply part, and ADS-B messages broadcasted by other aircrafts are received through the omnidirectional antenna. The ADS-B message is processed by the digital processing part after being amplified, subjected to frequency conversion and sampled by the radio frequency processing part, meanwhile, the ADS-B message generated by the digital processing part is filtered and amplified by the radio frequency processing part and then broadcasted by the omnidirectional antenna, and the clock part and the power supply part provide a clock and a power supply for the digital processing part and the radio frequency processing part. According to the utility model, the processing module, the radio frequency transceiver module, the power supply module and the like are integrated in one ADS-B transceiver module, so that the space occupation of equipment is reduced under the condition that the DO-260B standard protocol is met, and the ADS-B function can be integrated on a small industrial unmanned aerial vehicle.

Description

TECHNICAL FIELD

[0001] The utility model belongs to airborne equipment air traffic control field relates to a kind of miniaturization ADS-B terminal, mainly solve the ADS-B supervisory needs of small industrial unmanned aerial vehicle. BACKGROUND

[0002] The scheme for solving unmanned aerial vehicle communication and monitoring in the current market is realized by installing transponder with ADS-B function or other ADS-B independent terminal equipment, but due to its large size, installation mode occupies airborne equipment space on board, it is difficult to apply on small industrial unmanned aerial vehicle. INVENTION CONTENT

[0003] The application aims to provide a kind of miniaturization ADS-B terminal, which can be applied in small unmanned aerial vehicle, small general aircraft and other air traffic control monitoring use scenarios, integrates conventional processing module, radio frequency transceiver module, power module and the like in one ADS-B transceiver module, reduces the space occupation of equipment itself under the standard protocol of DO-260B, so as to integrate ADS-B function on small industrial unmanned aerial vehicle.

[0004] The application aims to realize the following technical solutions:

[0005] A kind of miniaturization ADS-B terminal, including ADS-B transceiver module, omnidirectional antenna, ADS-B transceiver module includes digital processing part, radio frequency processing part, clock part and power supply part, the ADS-B message broadcasted by other aircraft received by omnidirectional antenna, after amplification, frequency conversion and sampling by radio frequency processing part, it is handled by digital processing part, while the ADS-B message generated by digital processing part is broadcasted by omnidirectional antenna after filtering and amplification by radio frequency processing part, clock part and power supply part provide clock and power supply for digital processing part and radio frequency processing part, wherein:

[0006] Digital processing part includes XC7Z020 chip, Flash circuit and DDR3 circuit;

[0007] XC7Z020 chip includes PS and PL, DDR3 circuit and FLASH circuit are hung on PS side, one of two GigabitEthernet Controller is connected to PL side through interface bus between PS and PL, PPS signal and network message are received by NTP module on PL side, after processing message, NTP function is realized by communication with special PHY chip hung on PL side.

[0008] Preferably, Flash circuit is composed of two pieces of Flash in parallel, one piece stores data, and the other piece stores program.

[0009] Preferably, the DDR3 circuit is composed of two pieces of DDR3 in parallel.

[0010] Preferably, the digital processing part further comprises a watchdog chip.

[0011] Preferably, the radio frequency part comprises a transmitter and a receiver.

[0012] The transmitter comprises baseband signal generation, signal modulation and power amplification.

[0013] The baseband signal generation is built by the TRL circuit of the FPGA and the soft core processor.

[0014] The signal modulation part is composed of a VCO and a high-speed radio frequency switch, the VCO is responsible for generating a 1090MHz CW signal, and the FPGA controls the high-speed radio frequency switch to generate a PPM modulation signal.

[0015] The power amplification part comprises radio frequency filtering, drive stage amplification, final stage amplification and a circulator.

[0016] The receiver adopts a single conversion superheterodyne receiver scheme.

[0017] Preferably, in the signal modulation part, a digital attenuator and an amplifier are arranged between the VCO and the switch.

[0018] Preferably, the radio frequency part further comprises self-checking, and the self-checking comprises:

[0019] Transmitting link self-checking, a microstrip is coupled at the output of the final stage PA.

[0020] Receiving link self-checking, the ADS-B signal generated by the transmitting link is switched to the input port of the receiving link through a high-speed switch, and a microstrip is coupled.

[0021] Antenna port standing wave ratio self-checking: the size of the reflected power is directly judged, or the size of the antenna port standing wave ratio is calculated by cooperating with the output power detection of the transmitting link to judge.

[0022] The utility model discloses the beneficial effects are in that:

[0023] The miniaturized ADS-B terminal is an information system integrating communication and monitoring, and since it has only one terminal board card, can be integrated in other airborne equipment cases or plugged with other board cards, is flexible in installation, has small space requirement, and has low 12V power supply requirement, and has small requirement to airborne power supply.

[0024] The miniaturized ADS-B terminal can complete ADS-B OUT and ADS-B IN functions, has a high positioning accuracy, and has a positive effect on reducing the spacing standard of aircraft, optimizing the route setting, and improving airspace capacity.

[0025] The miniaturized ADS-B terminal can receive navigation information including local longitude, latitude, speed, height, etc. from a local navigation device, assemble multiple different types of ADS-B messages, and transmit the messages at different rates through an omnidirectional antenna in a broadcast form.

[0026] The miniaturized ADS-B terminal can receive ADS-B messages broadcast by other aircraft in real time, reassemble the received messages of various types according to different ADS-B user application requirements, assemble the messages into ADS-B reports conforming to the RTCA / DO-260B standard, and report the ADS-B reports to an upper layer user for further application processing. BRIEF DESCRIPTION OF DRAWINGS

[0027] Figure 1 The figure shows a cross-link diagram of the miniaturized ADS-B terminal.

[0028] Figure 2 shows a principle block diagram of an ADS-B module.

[0029] Figure 3 shows a principle block diagram of a radio frequency part.

[0030] Figure 4 shows a power tree diagram. DETAILED DESCRIPTION

[0031] The application will be further described in detail below in combination with the drawings and embodiments.

[0032] Referring to Figure 1 The miniaturized ADS-B terminal shown in the embodiment is composed of an ADS-B transceiving module, an omnidirectional antenna, etc. The ADS-B transceiving module is a core component of the system, and completes processing of transceiving signals, protocol processing, interface adaptation, etc. The omnidirectional antenna is used for receiving and transmitting ADS-B messages.

[0033] The principle block diagram of the ADS-B transceiving module is shown in Figure 2 The ADS-B transceiving module is divided into four main parts: a digital processing part, a radio frequency processing part, a clock part, and a power supply part. ADS-B message information broadcast by other aircraft received through the omnidirectional antenna is amplified, frequency-converted, and sampled by the radio frequency processing part, and then processed by the digital processing part to parse out the position and other data information of the aircraft, and sent to two on-board devices. The navigation position data of the local terminal can be obtained through an external interface of the ADS-B transceiving module, processed by a protocol, and framed into data to form an ADS-B message. The message is filtered and amplified by the radio frequency processing part, and then broadcast through the omnidirectional antenna. The clock part and the power supply part provide clock and power supply for the digital processing part and the radio frequency processing part.

[0034] 1) Digital processing part

[0035] The digital processing part adopts Xilinx 28nm ARM+FPGA SOC integration scheme, integrates dual-core ARM® Cortex™-A9, the minimum system uses DDR3, and the maximum capacity is 1GB. At the same time, a multi-core software and hardware development platform is developed based on the new Vivado18.3 IDE. The software is developed based on the linux software development platform, and the hardware and FPGA are developed based on the viva platform development tool.

[0036] It is mainly composed of XC7Z020, Q-SPI Flash circuit, DDR3 circuit, watchdog and reset circuit, etc.

[0037] a) XC7Z020:

[0038] XC7Z020 is a XILINX fully programmable system on a chip, mainly including PS (Processing System) and PL (Programmable Logic) two parts. The PS takes 2 Cortex-A9 ARM cores as the core, and the PL is the programmable logic part, which is equivalent to the FPGA of K7 series.

[0039] The PS leads out common peripherals through the MIO interface, such as SPI, IIC, UART, Gigabit Ethernet, USB, SD / SDIO, CAN and other interfaces. The PS also has an external static memory management interface, which can drive NOR, NAND and Q-SPI flash. Among them, SPI, IIC, UART, Gigabit Ethernet, SD / SDIO, CAN bus can be led out through the EMIO of PL. The PS and PL both contain DDR control interface, which can access DDR2, DDR3, DDR3L and LPDDR2 devices. The PS and the PL access each other through high-performance AXI interface and ACP interface.

[0040] In this design, the interfaces of DDR3, FLASH, GE PHY, USB PHY, UART1, SDIO are directly hung on the PS side, the IIC, SPI, UART0 interface controllers are distributed through the PL side chip selection, and the communication and control of the on-board peripheral devices are realized. At the same time, in order to realize the network time protocol NTP function, one of the two Gigabit Ethernet Controllers is connected to the PL side through the interface bus between PS and PL. The PPS signal and network message are received by the NTP module on the PL side, the message is processed, and the NTP function is realized through the communication with the special PHY chip hung on the PL side.

[0041] b) Flash:

[0042] Flash selects SPANSION's S25FL512SAGBHIC10, which is a 512Mbit Q-SPI Flash, and two pieces are used in parallel in the design, one of which stores data and the other stores program.

[0043] c) DDR3:

[0044] DDR3 selects Micron's MT41K256M16TW-107IT:P, single 4Gbit, 16-bit wide, two pieces are used in parallel in the design, which constitutes 1GB, 32-bit wide, and supports ECC function.

[0045] d) watchdog and reset design:

[0046] The watchdog chip uses SP706, which integrates watchdog, reset, power supply monitoring alarm and manual reset functions. The reset function is also realized by SP706, and the MR signal is grounded by pressing the key to realize the manual reset function.

[0047] 2) RF processing part

[0048] The RF part is divided into transmitter, receiver and self-checking three parts. The transmitter can generate ADS-B RF signal and perform filtering and amplification, and finally transmit it through the antenna; while the receiver performs amplification, frequency conversion and sampling on the received ADS-B RF signal; at the same time, the link also designs a self-checking function. The basic principle diagram is shown in Figure 3

[0049] The self-checking channel is used to simulate the generation of ADS-B signal to detect whether the receiver works normally. The self-checking channel generates a 1090MHz CW signal by a VCO, and simulates the generation of PPM modulation through a high-speed RF switch. The generated PPM signal is filtered by a digital attenuator and a filter, which can be switched to the receiver for internal self-checking through the RF switch, or switched to the TX_OUT port for external output.

[0050] a) transmitter

[0051] The transmitter includes three parts of baseband signal generation, signal modulation and power amplification.

[0052] Baseband signal generation:

[0053] The baseband signal generation is built by the TRL circuit of FPGA and the soft core processor, and the specific implementation steps are as follows:

[0054] ​First step: ARM received data information (including positioning information and their own identity, status information) through the Avalon bus UART serial port read into the kernel, and then in kernel PVT information and other data information encoding, assembly into 112 bits of standard data frame format, according to the specific rate to frame sequence generation part.

[0055] Second step: in frame sequence generation part, a frame message received by UART serial port according to field split into the corresponding register. According to the timing requirements of message frame output, first output fixed 4 pulse header, then output DF, CA, AA, ME and PI field in turn. When taking out the data bits of each field, pulse position coding is carried out, and the timing waveform corresponding to single bit 1 / 0 is generated by the counter, producing 120us ADS-B baseband signal.

[0056] Signal modulation:

[0057] Signal modulation part consists of VCO and high-speed RF switch.

[0058] VCO is responsible for generating 1090MHz CW signal, and FPGA controls high-speed RF switch to generate PPM modulation signal.

[0059] At the same time, in order to avoid the load traction caused by high-speed switch rapid switching on VCO output frequency, digital attenuator and amplifier are added between VCO and switch, which can not only solve the problem of VCO output impedance change when switching, but also can adjust the VCO output power properly.

[0060] Power amplification:

[0061] Power amplification part includes RF filter, drive level amplification, final stage amplification and circulator.

[0062] RF filter uses surface acoustic wave filter or dielectric filter to suppress out-of-band signals and harmonics.

[0063] Drive level amplification and final stage amplification amplify the ADS-B signal to the required power level.

[0064] Circulator suppresses harmonic signals on the one hand, and plays a role in reverse isolation on the other hand, preventing the final PA from being damaged.

[0065] b) receiver

[0066] The receiver adopts a superheterodyne receiver scheme, which receives ADS-B signal through antenna, and then amplifies the signal through LNA after limiting. The amplified signal is sent to the mixer for conversion to intermediate frequency signal, and then filtered and amplified at intermediate frequency. Finally, ADC is used for sampling.

[0067] c) Self-checking function design

[0068] Self-checking of the radio frequency part includes three parts: transmit chain, receive chain and antenna port VSWR.

[0069] Transmit chain self-checking:

[0070] The principle of transmit chain self-checking is to add a microstrip coupling at the output of the final PA. With the rated output power of 37dBm, the coupling degree is designed to be 45dB. By detecting the power coupled over, it is determined whether the gain and output power of the entire transmit chain are normal.

[0071] Receive chain self-checking:

[0072] Receive chain self-checking is completed with the help of the ADS-B signal generation part of the transmit chain. The transmit chain generates a 1090MHz test signal with an output power of 0dBm, which is switched to the input port of the receive chain through a high-speed switch. Again, through the form of microstrip coupling, the test signal is filled into the receive chain, and the coupling degree is designed to be 45dB. The FPGA calculates the size of the received signal to determine whether the gain of the receive chain is normal.

[0073] Antenna port VSWR self-checking:

[0074] The matching self-checking of the antenna port is to detect the size of the reflected power when the transmitter is normally rated to output, to determine whether the port matching is normal.

[0075] There are two schemes, one is to directly judge by the size of the reflected power, and the other is to cooperate with the output power detection of the transmit chain to calculate the size of the antenna port VSWR to judge.

[0076] 3) Clock part

[0077] The clock part generates the FPGA system clock, ADC sampling clock and reference clock of the radio frequency part PLL.

[0078] 4) Power supply part

[0079] Working input voltage: +12V ±0.5V

[0080] The power supply part is designed to output 1.0V, 1.8V, 3.3V, 1.5V, 7.4V and 5V through each power supply chip and peripheral voltage dividing circuit to the chip and functional module.

[0081] Single board power tree as follows Figure 4 :

[0082] It can be understood that, for those ordinary skilled in the art, equivalent replacements or changes can be made according to the technical solutions and the inventive concept of the present application, and all the changes or replacements shall fall within the protection scope of the appended claims of the present application.

Claims

1. A miniaturized ADS-B terminal, characterized in that: The application relates to an ADS-B transceiver module, an omnidirectional antenna, an ADS-B transceiver module comprising a digital processing part, a radio frequency processing part, a clock part and a power supply part, an ADS-B message broadcasted by other aircrafts received through the omnidirectional antenna, amplified, frequency-converted and sampled by the radio frequency processing part and processed by the digital processing part, and an ADS-B message generated by the digital processing part filtered and amplified by the radio frequency processing part and broadcasted through the omnidirectional antenna, the clock part and the power supply part providing clock and power supply for the digital processing part and the radio frequency processing part; The digital processing part comprises an XC7Z020 chip, a flash circuit and a DDR3 circuit; The XC7Z020 chip comprises a PS and a PL, the DDR3 circuit and the FLASH circuit are hung on the PS side, one of the two Gigabit Ethernet Controllers is connected to the PL side through an interface bus between the PS and the PL, and the PPS signal and the network message are received by the NTP module on the PL side, the message is processed, the NTP function is realized through communication with the special PHY chip hung on the PL side.

2. The miniaturized ADS-B terminal according to claim 1, characterized in that The flash circuit is composed of two pieces of flash in parallel, one piece of which stores data and the other piece of which stores programs.

3. The miniaturized ADS-B terminal according to claim 1, characterized in that The DDR3 circuit is composed of two pieces of DDR3 in parallel.

4. The miniaturized ADS-B terminal according to claim 1, characterized in that The digital processing part further comprises a watchdog chip.

5. The miniaturized ADS-B terminal according to claim 1, characterized in that The radio frequency part comprises a transmitter and a receiver; The transmitter comprises baseband signal generation, signal modulation and power amplification; The baseband signal generation is built by the TRL circuit of the FPGA and a soft core processor; The signal modulation part is composed of a VCO and a high-speed radio frequency switch, the VCO is responsible for generating a 1090MHz CW signal, and the FPGA controls the high-speed radio frequency switch to generate a PPM modulation signal; The power amplification part comprises radio frequency filtering, driving stage amplification, final stage amplification and a circulator; The receiver adopts a single conversion superheterodyne receiver scheme.

6. The miniaturized ADS-B terminal according to claim 5, characterized in that In the signal modulation part, a digital attenuator and an amplifier are arranged between the VCO and the switch.

7. The miniaturized ADS-B terminal according to claim 1, characterized in that The radio frequency part further comprises self-checking, and the self-checking comprises: Transmitting link self-checking, a microstrip is coupled at the output of the final stage PA; Receiving link self-checking, the ADS-B signal generated by the transmitting link is switched to the input port of the receiving link through the high-speed switch, and a microstrip is coupled; Antenna port standing wave ratio self-checking: the size of the reflected power is directly judged, or the size of the antenna port standing wave ratio is calculated by combining the output power of the transmitting link.

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