Circuit board structure
By designing the base's circuit area and connection area on the circuit board substrate, and directly plating a gold layer in the circuit area, the problem of improving the position and structure of the base and the gold plating layer was solved, realizing the precise electroplating of the circuit board and the manufacturing of low-power compressed connection memory modules.
Patent Information
- Application Number
- CN202422901696.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-26
- Publication Date
- 2025-11-18
- Estimated Expiration
- 2034-11-26
AI Technical Summary
There is room for improvement in the position and structure of the base and gold plating layer in the existing circuit board structure.
By forming the base circuit area and connection area on the substrate, and directly plating the gold plating layer in the circuit area, the formation of the copper plating layer is avoided. A multi-step etching process is used to precisely control the position and shape of the gold plating layer.
The position and structure of the base and the gold plating layer have been improved, resulting in a more precise electroplating effect, which is suitable for the manufacture of low-power compressed connection memory modules.
Smart Images
Figure CN223567846U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to a kind of circuit boards, in particular to a kind of circuit board structure. BACKGROUND
[0002] The existing circuit board structure usually includes base and multiple gold plating layers, but the position and structure of the base and multiple gold plating layers have room for improvement. SUMMARY
[0003] One embodiment of the utility model discloses a circuit board structure, comprising: a substrate, including a plurality of bases formed on a surface of the substrate; wherein each base defines a circuit area and a connection area extending from one side of the circuit area; and
[0004] Multiple gold plating layers are formed in the circuit areas of the plurality of bases.
[0005] Optionally, the length of each base is between 2.8 inches and 3.2 inches, and the width of each base is between 1.05 inches and 1.65 microns.
[0006] Optionally, the gold plating layer thickness of each gold plating layer is between 15 microns and 40 microns.
[0007] Optionally, the surface of the circuit area of each base is rectangular, each connection area is a wide side protruding from the circuit area, and the surface of each connection area is trapezoidal.
[0008] Optionally, in each base, a first length of the circuit area is greater than a second length of the connection area, and a first width of the circuit area is greater than a second width of the connection area.
[0009] Optionally, the first length of the circuit area is between 2.8 inches and 3.2 inches, the first width of the circuit area is between 0.75 inches and 1.05 inches, the second length of the connection area is between 0.8 inches and 1.2 inches, and the second width of the connection area is between 0.3 inches and 0.6 inches.
[0010] Optionally, the circuit board structure does not have any copper plating layer formed thereon.
[0011] Optionally, the surface of each gold plating layer is circular, and the diameter of the surface of each gold plating layer is between 20,000 microns and 24,000 microns.
[0012] In summary, the circuit board structure of the present application can effectively improve the position and structure of the base and gold plating layer on the existing circuit board structure through the technical solutions of "each base defining the circuit area and the connection area extending from one side of the circuit area" and "a plurality of gold plating layers formed in a plurality of circuit areas of the base".
[0013] For further understanding of the features and technical contents of the present application, please refer to the following detailed description and drawings of the present application. However, the description and drawings are only used to illustrate the present application, and do not limit the protection scope of the present application. BRIEF DESCRIPTION OF DRAWINGS
[0014] Figure 1 Flow chart of the electroplating method of the circuit board structure of the embodiment of the present application.
[0015] Figure 2 Schematic diagram of the pre-step of the electroplating method of the circuit board structure of the embodiment of the present application.
[0016] Figure 3 Schematic diagram of the copper plating step of the electroplating method of the circuit board structure of the embodiment of the present application.
[0017] Figure 4 Schematic diagram of the masking film covering step of the electroplating method of the circuit board structure of the embodiment of the present application.
[0018] Figure 5 Schematic diagram of the first micro-etching step of the electroplating method of the circuit board structure of the embodiment of the present application.
[0019] Figure 6 Schematic diagram of the gold plating step of the electroplating method of the circuit board structure of the embodiment of the present application.
[0020] Figure 7 Schematic diagram of the second micro-etching step of the electroplating method of the circuit board structure of the embodiment of the present application.
[0021] Figure 8 Schematic diagram of the circuit board structure of the embodiment of the present application. DETAILED DESCRIPTION
[0022] The following specific embodiments illustrate the implementation of the "circuit board structure" disclosed in this utility model. Those skilled in the art can understand the advantages and effects of this utility model from the content disclosed in this specification. This utility model can be implemented or applied through other different specific embodiments, and various details in this specification can also be modified and changed based on different viewpoints and applications without departing from the concept of this utility model. Furthermore, the accompanying drawings of this utility model are for simple illustrative purposes only and are not depictions of actual dimensions, as stated in advance. The following embodiments will further describe the relevant technical content of this utility model in detail, but the disclosed content is not intended to limit the scope of protection of this utility model.
[0023] It should be understood that while terms such as "first," "second," and "third" may be used in this document to describe various components or signals, these components or signals should not be limited by these terms. These terms are primarily used to distinguish one component from another, or one signal from another. Furthermore, the term "or" as used herein should, as appropriate, include any combination of one or more of the related listed items.
[0024] Electroplating methods for circuit board structures
[0025] See Figure 1 As shown, Figure 1 This is a flowchart illustrating an electroplating method for a circuit board structure according to an embodiment of the present invention. The first embodiment of the present invention provides an electroplating method for a circuit board structure. The electroplating method for the circuit board structure may include a pre-processing step S110, a copper plating step S120, a masking film covering step S130, a first micro-etching step S140, a gold plating step S150, and a second micro-etching step S160. Of course, the electroplating method for the circuit board structure may also include other steps as needed, and the present invention does not impose any limitations thereon.
[0026] Please see Figure 2 As shown, Figure 2 This is a schematic diagram of the preliminary steps of the electroplating method for the circuit board structure according to an embodiment of the present invention. In the preliminary step S110, a substrate 1 is provided, and a plurality of bases 11 are formed on one surface of the substrate 1. Each base 11 defines a line region 11a and a connection region 11b extending from one side of the line region.
[0027] In the embodiment, the length of each base 11 is between 2.8 inches and 3.2 inches, and the width of each base 11 is between 1.05 inches and 1.65 inches, but the length and the width of each base 11 can be changed according to requirements, and the utility model is not limited to this. In addition, the length and the width referred to herein can be regarded as the maximum length and the maximum width of each base 11.
[0028] In addition, in the embodiment, the surface of the circuit area 11a of each base 11 is rectangular, each connecting area 11b is a wide side protruding from the circuit area 11a, and the surface of each connecting area 11b is trapezoidal. More specifically, the surface of each connecting area 11b is isosceles trapezoidal, but the utility model is not limited to this.
[0029] In each base 11 of the embodiment, a first length L1 of the circuit area 11a is greater than a second length L2 of the connecting area 11b, and a first width W1 of the circuit area 11a is greater than a second width W2 of the connecting area 11b, but the utility model is not limited to this. Alternatively, the first length L1 of the circuit area is between 2.8 inches and 3.2 inches, the first width W1 of the circuit area 11a is between 0.75 inches and 1.05 inches, the second length L2 of the connecting area 11b is between 0.8 inches and 1.2 inches, and the second width W2 of the connecting area 11b is between 0.3 inches and 0.6 inches, but the utility model is not limited to this.
[0030] In addition, it should be noted that the first length L1 and the second length L2 respectively refer to the dimensions of the circuit area 11a and the connecting area 11b in the length direction, the first width W1 and the second width W2 respectively refer to the dimensions of the circuit area 11a and the connecting area 11b in the width direction, the first length L1 is the length of the base 11, and the sum of the first width W1 and the second width W2 is the width of the base 11.
[0031] Please refer to Figure 3 shown, Figure 3The utility model discloses a copperization step of the electroplating method of the circuit board structure. In the copperization step S120, a copperization layer 2 is formed on the substrate 1 by copperization. In the copperization step S120 of the embodiment, the thickness (not shown in the figure) of the copperization layer 2 is between 5 micro inches and 20 micro inches. Alternatively, the thickness of the copperization layer 2 is between 10 micro inches and 15 micro inches. In the embodiment, the copperization layer 2 is formed on one surface of the substrate 1, but the utility model is not limited to this. In other embodiments not shown in the utility model, the copperization layer 2 can also be formed on both surfaces of the substrate 1 or cover the entire substrate 1.
[0032] Referring to Figure 4 as shown, Figure 4 The utility model discloses a covering step of the electroplating method of the circuit board structure. In the covering step S130, a covering film 3 is covered on the copperization layer 2 on the substrate 1, the covering film 3 has a plurality of windows 3a, and the copperization layer 2 on the plurality of circuit areas 11a of the plurality of pedestals 11 is exposed from the plurality of windows 3a. Specifically, the covering film 3 can partially cover the plurality of circuit areas 11a of the plurality of pedestals 11, so that the copperization layer 2 on each circuit area 11a is partially exposed from the covering film 3. In addition, as long as the covering film 3 has the property of resisting etching, the utility model does not limit the specific material of the covering film 3, and the specific shape of the window 3a can also vary according to requirements.
[0033] Referring to Figure 5 as shown, Figure 5 The utility model discloses a first microetching step of the electroplating method of the circuit board structure. In the first microetching step S140, the substrate 1 covered with the covering film 3 is microetched to remove the copperization layer 2 on the plurality of circuit areas 11a and exposed from the window 3a. In the first microetching step S140 of the embodiment, a first microetching solution is used to microetch the substrate, and the first microetching solution contains 5-35 g / L sulfuric acid, but the utility model is not limited to this. Alternatively, the first microetching solution contains 10-30 g / L sulfuric acid.
[0034] Specifically, the first microetching solution microetches the copperization layer 2 on the circuit area 11a and exposed from the window 3a of the covering film 3, and the first microetching solution does not microetch the copperization layer 2 covered by the covering film 3.
[0035] Referring to Figure 6 as shown,Figure 6 This is a schematic diagram of the gold plating step in the electroplating method for a circuit board structure according to an embodiment of the present invention. In the gold plating step S150, multiple gold plating layers 4 are plated on multiple circuit regions 11a of multiple substrates 11. It is worth mentioning that after the first micro-etching step S140, the copper oxide layer 2 is not formed on the substrate 1 at the position corresponding to the opening 3a of the masking film 3, and in the gold plating step S150, electroplating is performed directly on the substrate 1 exposed from the opening 3a, thereby directly forming the gold plating layer 4 on the circuit region 11a of the substrate 1. In other words, the gold plating layer 4 is directly formed on the circuit region 11a of the substrate 1, and the copper oxide layer 2 is not formed between the gold plating layer 4 and the substrate 1. Therefore, in the gold plating step S150, electroplating can be precisely performed on specific areas of a substrate with a specific shape.
[0036] In the gold plating step S150 of this embodiment, the thickness T of each gold plating layer 4 is between 15 microinches and 40 microinches. However, the thickness T of the gold plating layer 4 can vary according to actual needs, and this invention is not limited thereto. Optionally, the thickness T of each gold plating layer 4 is between 20 microinches and 35 microinches. Furthermore, in this embodiment, the surface of each gold plating layer 4 can be circular, and the diameter D of the surface of each gold plating layer 4 can be between 20,000 microinches and 24,000 microinches, but this invention is not limited thereto.
[0037] Please see Figure 7 As shown, Figure 7 This is a schematic diagram of the second micro-etching step of the electroplating method for a circuit board structure according to an embodiment of the present invention. In the second micro-etching step S160, the substrate 1 is micro-etched to remove the copper plating layer 2 on the substrate, thereby forming a circuit board structure 100 (e.g., ...). Figure 8 (As shown). It is worth mentioning that after the second micro-etching step S160, the circuit board structure 100 may not have the copper plating layer 2. In addition, before the second micro-etching step S160, the masking film 3 can be removed first.
[0038] In the second etching step S160 of the embodiment, the substrate 1 is etched by a second etching solution, and the second etching solution contains 55 g / L to 105 g / L of sodium persulfate, but the present application is not limited thereto. Alternatively, the second etching solution contains 60 g / L to 100 g / L of sodium persulfate. It should be noted that in the first etching step S140 and the second etching step S160, the copper layer 2 in the circuit area 11a and the copper layer 2 in other areas are removed by etching, so the composition of the first etching solution is different from that of the second etching solution.
[0039] In addition, in each of the pedestals 11, the circuit area 11a where the gold plating layer 4 is formed can be used to dispose a related chip thereon, and the connection area 11b can be used to connect with a spring of a connector, and the circuit board structure 100 can be used to manufacture a low power compression attached memory module (LPCAMM), but the present application is not limited thereto.
[0040] [Circuit board structure]
[0041] Please refer to Figure 8 , Figure 8 is a three-dimensional flowchart of the circuit board structure of the embodiment. The embodiment of the present application further provides a circuit board structure 100. The circuit board structure 100 can be obtained, for example, by the manufacturing method of the circuit board structure described above, but the present application is not limited thereto.
[0042] The circuit board structure 100 includes a substrate 1 and a plurality of gold plating layers 4. The substrate 1 includes a plurality of pedestals 11 formed on a surface of the substrate 1. Each of the pedestals 11 defines a circuit area 11a and a connection area 11b extending from one side of the circuit area 11a.
[0043] The length of each of the pedestals 11 is between 2.8 inches and 3.2 inches, and the width of each of the pedestals 11 is between 1.05 inches and 1.65 inches.
[0044] The surface of the circuit area 11a of each of the pedestals 11 is rectangular, each of the connection areas 11b is a wide side of the circuit area 11a protruding, and the surface of each of the connection areas 11b is trapezoidal.
[0045] In each of the pedestals 11, a first length L1 of the circuit region 11a is greater than a second length L2 of the connection region 11b, and a first width W1 of the circuit region 11a is greater than a second width W2 of the connection region 11b.
[0046] The first length L1 of the circuit region 11a is between 2.8 inches and 3.2 inches, the first width W1 of the circuit region 11a is between 0.75 inches and 1.05 inches, the second length L2 of the connection region 11b is between 0.8 inches and 1.2 inches, and the second width W2 of the connection region 11b is between 0.3 inches and 0.6 inches.
[0047] No copper plating layer is formed on the circuit board structure 100. A plurality of gold plating layers 4 are formed on the circuit regions 11a of the pedestals 11. A gold plating layer thickness T of each of the gold plating layers 4 is between 15 micro inches and 40 micro inches.
[0048] [Advantages of the embodiments]
[0049] One of the advantages of the present application is that the circuit board structure can effectively improve the position and structure of the pedestal and the gold plating layer on the existing circuit board structure by the technical solutions of "each of the pedestals defining the circuit region and the connection region extending from one side of the circuit region" and "a plurality of gold plating layers formed on the circuit regions of the pedestals".
[0050] The above description is only an optional and feasible embodiment of the present application, and does not limit the patent range of the present application. Therefore, any equivalent technical changes made by applying the content of the present application specification and drawings are included in the protection range of the present application.
Claims
1. A circuit board structure, characterized by, The circuit board structure comprises: a substrate including a plurality of pedestals formed on a surface of the substrate; wherein each of the pedestals defines a circuit area and a connection area extending from a side of the circuit area; and a plurality of gold plated layers formed on the circuit areas of the pedestals.
2. The circuit board structure according to claim 1, characterized by Each of the pedestals has a length between 2.8 inches and 3.2 inches, and each of the pedestals has a width between 1.05 inches and 1.65 inches.
3. The circuit board structure according to claim 1, characterized by Each of the gold plated layers has a gold plated layer thickness between 15 micro inches and 40 micro inches.
4. The circuit board structure according to claim 1, characterized by The circuit area of each of the pedestals has a rectangular surface, each of the connection areas has a protruding wide side from the circuit area, and each of the connection areas has a trapezoidal surface.
5. The circuit board structure of claim 1, wherein In each of the pedestals, a first length of the circuit area is greater than a second length of the connection area, and a first width of the circuit area is greater than a second width of the connection area.
6. The circuit board structure according to claim 5, characterized by The first length of the circuit area is between 2.8 inches and 3.2 inches, the first width of the circuit area is between 0.75 inches and 1.05 inches, the second length of the connection area is between 0.8 inches and 1.2 inches, and the second width of the connection area is between 0.3 inches and 0.6 inches.
7. The circuit board structure of claim 1, wherein The circuit board structure does not have any copper plating formed thereon.
8. The circuit board structure of claim 1, wherein Each of the gold plated layers has a circular surface, and each of the gold plated layers has a diameter between 20,000 micro inches and 24,000 micro inches.