Display panel

Abstract

A display panel includes: a driving element layer including: a first pixel driver including a first conductive pattern; and a second pixel driver including a second conductive pattern; a light emitting element on the driving element layer and including a first electrode, an intermediate layer on the first electrode, and a second electrode on the intermediate layer; a connection electrode on the driving element layer and electrically connected with the first pixel driver and the second electrode; and a metal layer between the second conductive pattern and the connection electrode in a cross-sectional view.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0166461, filed on November 27, 2023, in the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. TECHNICAL FIELD

[0003] Aspects of embodiments of the present disclosure relate to a display panel, and more particularly, to a display panel having reduced afterimage. BACKGROUND

[0004] Multimedia electronic devices such as televisions, mobile phones, computers such as tablet computers, navigators, or game consoles are provided with display panels for displaying images. The display panel includes light emitting elements and a circuit for controlling the light emitting elements. The light emitting elements included in the display panel emit light to generate an image according to a voltage applied from the circuit. In order to improve the reliability of the display panel, improved connection between the light emitting elements and the circuit can be desired.

[0005] The above information disclosed in this Background section is only for enhancing the understanding of the background of the present disclosure, and therefore, it can contain information that does not constitute prior art. SUMMARY

[0006] One or more embodiments of the present disclosure can relate to a display panel having reduced afterimage.

[0007] According to one or more embodiments of the present disclosure, a display panel includes: a driving element layer including: a first pixel driver including a first conductive pattern; and a second pixel driver including a second conductive pattern; a light emitting element on the driving element layer, and including a first electrode, an intermediate layer on the first electrode, and a second electrode on the intermediate layer; a connection electrode on the driving element layer, and electrically connected with the first pixel driver and the second electrode; and a metal layer between the second conductive pattern and the connection electrode in a cross-sectional view.

[0008] In an embodiment, the first conductive pattern can include: a 1-1 pattern; and a 2-1 pattern electrically connected with the connection electrode.

[0009] In an embodiment, the second conductive pattern can include a 1-2 pattern and a 2-2 pattern.

[0010] In an embodiment, the 1-2 pattern and the 2-2 pattern can overlap with the metal layer and / or the connection electrode in a plan view.

[0011] In an embodiment, the first-1 pattern and the first-2 pattern can include a source electrode pattern, and / or the second-1 pattern and the second-2 pattern can include a drain electrode pattern.

[0012] In an embodiment, the display panel can further include an intermediate connection electrode electrically connecting the first pixel driver and the connection electrode to each other, wherein the metal layer positioning can be at a same layer as a layer of the intermediate connection electrode.

[0013] In an embodiment, the metal layer can be connected to the first electrode.

[0014] In an embodiment, the display panel can further include a pixel definition layer on the drive element layer and having an emission opening through the pixel definition layer, the emission opening exposing at least a portion of the first electrode, wherein the connection electrode can have a ring shape surrounding the emission opening.

[0015] In an embodiment, a bottom surface of the second electrode can contact a top surface of the connection electrode.

[0016] In an embodiment, the display panel can further include a partition on the connection electrode, wherein the second electrode and the connection electrode can be connected to each other at an area adjacent to the partition, and wherein the connection electrode can include a first edge and a second edge surrounding the first edge and overlapping the partition.

[0017] According to one or more embodiments of the present disclosure, a display panel includes a drive element layer including a first pixel driver including a first conductive pattern and a second pixel driver including a second conductive pattern; a light emitting element on the drive element layer and including a first electrode, an intermediate layer on the first electrode, and a second electrode on the intermediate layer; a connection electrode on the drive element layer and electrically connected to the first pixel driver and the second electrode; and a metal layer between the second conductive pattern and the connection electrode in a cross-sectional view.

[0018] In an embodiment, the first conductive pattern can include a first-1 pattern and a second-1 pattern electrically connected to the connection electrode.

[0019] In an embodiment, the second conductive pattern can include a first-2 pattern and a second-2 pattern.

[0020] In an embodiment, the first-2 pattern and the second-2 pattern can overlap the metal layer in a plan view.

[0021] In an embodiment, the 1st-2 pattern and the 2nd-2 pattern can overlap with the connection electrode in a plan view.

[0022] In an embodiment, the 1st-1 pattern and the 1st-2 pattern can include a source electrode pattern.

[0023] In an embodiment, the 2nd-1 pattern and the 2nd-2 pattern can include a drain electrode pattern.

[0024] In an embodiment, the display panel can further include an intermediate connection electrode electrically connecting the first pixel driver and the connection electrode to each other.

[0025] In an embodiment, the metal layer can include the same material as a material of the intermediate connection electrode, and can be positioned at the same layer as a layer of the intermediate connection electrode.

[0026] In an embodiment, the metal layer can include the same material as a material of the first electrode, and can be connected to the first electrode.

[0027] In an embodiment, the display panel can further include a pixel definition layer on the driving element layer and having an emission opening through the pixel definition layer, the emission opening exposing at least a portion of the first electrode. The connection electrode can have a ring shape surrounding the emission opening.

[0028] In an embodiment, a bottom surface of the second electrode can contact a top surface of the connection electrode.

[0029] In an embodiment, the display panel can further include a partition on the connection electrode, and the second electrode and the connection electrode can be connected to each other at an area adjacent to the partition.

[0030] In an embodiment, the connection electrode can include a first edge, and a second edge surrounding the first edge and overlapping with the partition.

[0031] According to one or more embodiments of the disclosure, a display panel includes a driving element layer including a pixel driver including a conductive pattern, a light emitting element on the driving element layer and including a first electrode, an intermediate layer on the first electrode, and a second electrode on the intermediate layer, a connection electrode on the driving element layer and electrically connected with the pixel driver and the second electrode, and a metal layer overlapping with the connection electrode and the conductive pattern in a plan view.

[0032] In an embodiment, the conductive pattern can include a first pattern, and a second pattern electrically connected with the connection electrode.

[0033] In an embodiment, the first pattern can include a source electrode pattern, and the second pattern can include a drain electrode pattern.

[0034] In an embodiment, the display panel can further include an intermediate connection electrode electrically connecting the pixel driver and the connection electrode to each other.

[0035] In an embodiment, the metal layer can include the same material as a material of the intermediate connection electrode, and the metal layer can be positioned on the same layer as a layer of the intermediate connection electrode.

[0036] In an embodiment, the metal layer can include the same material as a material of the first electrode, and the metal layer can be connected to the first electrode.

[0037] However, the present disclosure is not limited to the above-mentioned aspects and features, and the above-mentioned and other aspects and features of the present disclosure will be partially set forth in the detailed description below with reference to the accompanying drawings, and can be apparent from the detailed description, or can be appreciated by practicing one or more of the embodiments of the present disclosure presented. BRIEF DESCRIPTION OF DRAWINGS

[0038] The above-mentioned and other aspects and features of the present disclosure will become more apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the present disclosure.

[0039] Figure 1 is a block diagram of a display apparatus according to an embodiment of the present disclosure;

[0040] Figures 2A-2C is an equivalent circuit diagram of a pixel according to one or more embodiments of the present disclosure;

[0041] Figure 3A and Figure 3B is a plan view of a display panel according to one or more embodiments of the present disclosure;

[0042] Figures 4A-4D is an enlarged plan view of a partial area of a display panel according to one or more embodiments of the present disclosure;

[0043] Figure 5 is a cross-sectional view of a display panel according to an embodiment of the present disclosure;

[0044] Figure 6 is an enlarged plan view of a partial area of a display panel according to an embodiment of the present disclosure;

[0045] Figure 7 is a cross-sectional view of a display panel according to an embodiment of the present disclosure;

[0046] Figure 8 is a cross-sectional view of a display panel according to an embodiment of the disclosure;

[0047] Figure 9 is an enlarged cross-sectional view of a partial area of a display panel according to an embodiment of the disclosure; and

[0048] Figure 10 is a cross-sectional view of a display panel according to an embodiment of the disclosure. DETAILED DESCRIPTION

[0049] Hereinafter, embodiments will be described in greater detail with reference to the accompanying drawings, in which like numerals refer to like elements throughout the drawings. The disclosure may, however, be embodied in various different forms, and should not be construed as being limited only to the embodiments set forth herein. Rather, these embodiments are provided as examples so that the disclosure will be thorough and complete, and will fully convey the aspects and features of the disclosure to those skilled in the art. Therefore, processes, elements, and techniques not necessary to an understanding of the aspects and features of the disclosure can not be described. Like reference numerals refer to like elements throughout the drawings and written description, and thus, redundant descriptions can not be repeated.

[0050] When a specific embodiment can be implemented differently, a specific process sequence can be different from the described sequence. For example, two processes described in succession can be executed at the same time or substantially at the same time, or can be executed in an order opposite to the described sequence.

[0051] Further, as will be understood by those of ordinary skill in the art in light of the entire disclosure, each suitable feature of various embodiments of the disclosure can be partially or wholly combined or combined with each other, and can be technically interconnected and operated in various suitable ways, and each embodiment can be implemented independently of or in combination with each other in any suitable way, unless otherwise stated or implied.

[0052] In the drawings, the relative sizes and thicknesses of elements, layers, and regions can be exaggerated for clarity. Spatial relative terms, such as “beneath”, “below”, “lower”, “under”, “above”, “upper” and the like, can be used herein for ease of description to describe one element or feature’s relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatial relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is turned over, elements described as “below” or “beneath” or “under” other elements or features would then be oriented “above” the other elements or features. Thus, the example terms “below” and “under” can encompass both orientations of above and below. The device can be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatial relative terms used herein interpreted accordingly.

[0053] In the drawings, the first direction DR1, the second direction DR2, and the third direction DR3 are not limited to the directions indicated by the three axes of a rectangular coordinate system, and can be interpreted in a broader sense. For example, the first direction DR1, the second direction DR2, and the third direction DR3 can be perpendicular to each other or substantially perpendicular to each other, or can represent mutually different directions that are not perpendicular to each other.

[0054] It will be understood that, although the terms “first”, “second”, “third”, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section described later can be termed a second element, component, region, layer or section without departing from the spirit and scope of the present disclosure.

[0055] It will be understood that when an element or layer is referred to as being “on” another element or layer, “connected to” or “coupled to” another element or layer, it can be directly on, directly connected to, or directly coupled to the other element or layer, or one or more intervening elements or layers can be present. In similar manner, when a layer, region, or element is referred to as being “electrically connected” to another layer, region, or element, it can be electrically connected directly to the other layer, region, or element, and / or can be electrically connected indirectly to the other layer, region, or element such that one or more intervening layers, regions, or elements are present between the layer, region, or element and the other layer, region, or element. In addition, it will also be understood that when an element or layer is referred to as being “between” two elements or layers, it can be the only element or layer between the two elements or layers or one or more intervening elements or layers can also be present.

[0056] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” “including,” and “has,” “having,” when used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. For example, the expression “A and / or B” means A, B, or both A and B. Expressions such as “at least one of (one or more) A and B” when preceding the list of elements, modify the entire list of elements and do not modify the individual elements of the list. For example, the expression, “at least one of (one or more) a, b, and c” means a, b, c, a and b, a and c, b and c, or a, b, and c.

[0057] As used herein, the terms "substantially," "approximately," and similar terms are used as terms of approximation and not as terms of degree, and are intended to account for the inherent variations in a measurement or calculation that would be recognized by those of ordinary skill in the art. Moreover, the use of "can," "might," and "may" indicates that one or more embodiments of the disclosure are contemplated. As used herein, the terms "use," "using," and "used" can be considered synonymous with the terms "utilize," "utilizing," and "utilized," respectively. Additionally, the term "exemplary" is intended to refer to an example or illustration.

[0058] As used herein, various terms including "component" or "unit" can refer to a software component or a hardware component that performs a specific function. The hardware component can include, for example, a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC). The software component can refer to executable code and / or data used by the executable code in an addressable storage medium. Thus, the software component can be, for example, an object-oriented software component, a class component, and a task component, and can include processes, functions, attributes, procedures, subroutines, segments of program code, drivers, firmware, microcode, circuits, data, databases, data structures, tables, arrays, and / or variables. The functionality of the software component can be combined with the functionality of the hardware component, and vice versa.

[0059] Unless defined otherwise, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and / or the present specification, and should not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0060] Figure 1 is a block diagram of a display device DD according to an embodiment of the disclosure.

[0061] Referring to Figure 1 , the display device DD can include a display panel DP, panel drivers SDC, EDC, and DDC, a power component (e.g., a power supply or a power source) PWS, and a timing controller TC. In an embodiment, the display panel DP can be described in more detail in the context of a light-emitting display panel. The light-emitting display panel can include an organic light-emitting display panel, an inorganic light-emitting display panel, or a quantum dot light-emitting display panel. In an embodiment, the organic light-emitting display panel can be described in more detail hereinafter as a representative example of the display panel DP. The panel drivers SDC, EDC, and DDC can include a scan driver SDC, an emission driver EDC, and a data driver DDC.

[0062] The display panel DP can include scan lines GWL1 to GWLn, GCL1 to GCLn, GIL1 to GILn, GBL1 to GBLn, and GRL1 to GRLn, emission lines ESL1 to ESLn, and data lines DL1 to DLm, where n and m are integers greater than 1. The display panel DP can include a plurality of pixels connected to the scan lines GWL1 to GWLn, GCL1 to GCLn, GIL1 to GILn, GBL1 to GBLn, GRL1 to GRLn, the emission lines ESL1 to ESLn, and the data lines DL1 to DLm.

[0063] For example, a pixel PXij (where i is greater than or equal to 1 and less than or equal to n, and j is greater than or equal to 1 and less than or equal to m) located at an i-th horizontal line (e.g., an i-th pixel row) and a j-th vertical line (e.g., a j-th pixel column) can be connected to an i-th first scan line (e.g., a write scan line) GWLi, an i-th second scan line (e.g., a compensation scan line) GCLi, an i-th third scan line (e.g., a first initialization scan line) GILi, an i-th fourth scan line (e.g., a second initialization scan line) GBLi, an i-th fifth scan line (e.g., a reset scan line) GRLi, a j-th data line DLj, and an i-th emission line ESLi.

[0064] The pixel PXij can include at least one light emitting element, a plurality of transistors, and at least one capacitor. The pixel PXij can receive a first power voltage VDD, a second power voltage VSS, a third power voltage (e.g., a reference voltage) VREF, a fourth power voltage (e.g., a first initialization voltage) VINT1, a fifth power voltage (e.g., a second initialization voltage) VINT2, and a sixth power voltage (e.g., a compensation voltage) VCOMP through a power supply part PWS.

[0065] A value (e.g., a voltage value) of the first power voltage VDD and the second power voltage VSS can be determined (e.g., can be set) such that a current flows through the light emitting element to emit light. For example, the first power voltage VDD can be higher than the second power voltage VSS.

[0066] The third power voltage VREF can be used to initialize a gate of a driving transistor included in the pixel PXij. The third power voltage VREF can be used to implement a predetermined gray scale using a difference from a voltage of a data signal. Accordingly, the third power voltage VREF can have a predetermined voltage within a suitable voltage range of the data signal.

[0067] The fourth power supply voltage VINT1 can be used to initialize the capacitor included in the pixel PXij. The fourth power supply voltage VINT1 can be lower than the third power supply voltage VREF. For example, the fourth power supply voltage VINT1 can have a voltage lower than a difference between the third power supply voltage VREF and a threshold voltage of the drive transistor. However, the present disclosure is not limited thereto.

[0068] The fifth power supply voltage VINT2 can be used to initialize the cathode of the light emitting element included in the pixel PXij. The fifth power supply voltage VINT2 can have a voltage lower than the first power supply voltage VDD or the fourth power supply voltage VINT1, or can have a voltage similar to or the same as the third power supply voltage VREF, but the present disclosure is not limited thereto. The fifth power supply voltage VINT2 can have a voltage similar to or the same as the first power supply voltage VDD.

[0069] The sixth power supply voltage VCOMP can supply a predetermined current to the drive transistor when a threshold voltage of the drive transistor is compensated.

[0070] In Figure 1 In the above, the first power supply voltage VDD, the second power supply voltage VSS, the third power supply voltage VREF, the fourth power supply voltage VINT1, the fifth power supply voltage VINT2, and the sixth power supply voltage VCOMP are illustrated as being supplied from the power supply part PWS, but the present disclosure is not limited thereto. For example, the first power supply voltage VDD and the second power supply voltage VSS can be supplied regardless of the structure of the pixel PXij, and at least one of the third power supply voltage VREF, the fourth power supply voltage VINT1, the fifth power supply voltage VINT2, and the sixth power supply voltage VCOMP can not be supplied in correspondence with the structure of the pixel PXij.

[0071] In an embodiment of the present disclosure, the signal line connected to the pixel PXij can be designed in various suitable manners in correspondence with the circuit structure of the pixel PXij.

[0072] The scan driver SDC can receive the first control signal SCS from the timing controller TC, and can supply respective scan signals to the first scan lines GWL1 to GWLn, the second scan lines GCL1 to GCLn, the third scan lines GIL1 to GILn, the fourth scan lines GBL1 to GBLn, or the fifth scan lines GRL1 to GRLn based on the first control signal SCS.

[0073] Each of the plurality of scan signals can have a voltage through which a transistor supplied with the scan signal can be turned on. For example, a scan signal supplied to a P-type transistor can have a logic low level, and a scan signal supplied to an N-type transistor can have a logic high level. As used herein, the phrase "a scan signal is supplied" can be understood as a scan signal being supplied with a logic level (e.g., an on level) for turning on a transistor controlled by the scan signal.

[0074] For ease of explanation, Figure 1 The scan driver SDC is illustrated as having a single component, but the present disclosure is not limited thereto. According to an embodiment, a plurality of scan drivers can be included to supply scan signals to the first scan lines GWL1 through GWLn, the second scan lines GCL1 through GCLn, the third scan lines GIL1 through GILn, the fourth scan lines GBL1 through GBLn, or the fifth scan lines GRL1 through GRLn.

[0075] The emission driver EDC can output emission control signals to the plurality of emission lines ESL1 through ESLn based on a second control signal ECS. For example, a plurality of emission control signals can be sequentially supplied to the emission lines ESL1 through ESLn.

[0076] A transistor connected to the emission lines ESL1 through ESLn according to an embodiment of the present disclosure can be composed of an N-type transistor. An emission signal supplied to the emission lines ESL1 through ESLn can have a gate cut-off voltage. A transistor configured to receive the emission signal can be cut off when the emission signal is supplied, and can be in an on state otherwise.

[0077] The second control signal ECS can include an emission start signal and a clock signal. The emission driver EDC can be implemented with a shift register configured to sequentially shift the emission start signal of a pulse type using the clock signal to sequentially generate and output the emission signal having the pulse type.

[0078] The data driver DDC can receive a third control signal DCS and image data RGB from the timing controller TC. The data driver DDC can convert the image data RGB, which is digital, into an analog data signal (e.g., a data signal). The data driver DDC can supply the data signal to the data lines DL1 through DLm in response to the third control signal DCS.

[0079] The third control signal DCS can include a data enable signal for instructing output of the valid data signal, a horizontal start signal, or a data clock signal, etc. For example, the data driver DDC can include a shift register for shifting the data clock signal in synchronization with the horizontal start signal to generate a sampling signal, a latch for latching the image data RGB in response to the sampling signal, a digital-to-analog converter (e.g., a decoder) for converting the latched image data (e.g., digital data) into an analog data signal, and a buffer (e.g., an amplifier) for outputting the data signal to the data lines DL1 to DLm.

[0080] The power supply part PWS can supply the first power supply voltage VDD, the second power supply voltage VSS, or the third power supply voltage VREF for driving the pixels PXij to the display panel DP. In addition, the power supply part PWS can supply at least one of the fourth power supply voltage VINT1, the fifth power supply voltage VINT2, and the sixth power supply voltage VCOMP to the display panel DP.

[0081] For example, the power supply part PWS can supply the first power supply voltage VDD, the second power supply voltage VSS, the third power supply voltage VREF, the fourth power supply voltage VINT1, the fifth power supply voltage VINT2, or the sixth power supply voltage VCOMP to the display panel DP via a first power line VDL (e.g., see Figure 2A ), a second power line VSL (e.g., see Figure 2A ), a third power line (e.g., a reference voltage line) VRL (e.g., see Figure 2A ), a fourth power line (e.g., a first initialization voltage line) VIL1 (e.g., see Figure 2A ), a fifth power line (e.g., a second initialization voltage line) VIL2 (e.g., see Figure 2A ), and a sixth power line (e.g., a voltage compensation line) VCL (e.g., see Figure 2A ).

[0082] The power supply part PWS can be implemented as a power management integrated circuit, but the present disclosure is not limited thereto.

[0083] The timing controller TC can generate a first control signal SCS, a second control signal ECS, a third control signal DCS, and a fourth control signal PCS based on the input image data IRGB, a synchronization signal Sync (e.g., a vertical synchronization signal and a horizontal synchronization signal, etc.), a data enable signal DE, or a clock signal, etc. The first control signal SCS can be supplied to the scan driver SDC, the second control signal ECS can be supplied to the emission driver EDC, the third control signal DCS can be supplied to the data driver DDC, and the fourth control signal PCS can be supplied to the power supply part PWS. The timing controller TC can rearrange the input image data IRGB in response to the pixels PXij (e.g., arrangement of the pixels PXij) in the display panel DP to generate image data RGB (e.g., frame data).

[0084] The scan driver SDC, the emission driver EDC, the data driver DDC, the power supply part PWS, and / or the timing controller TC can be directly provided in the display panel DP, or can be provided in a separate driving chip to be connected to the display panel DP. Also, at least two of the scan driver SDC, the emission driver EDC, the data driver DDC, the power supply part PWS, and the timing controller TC can be provided together in one driving chip. For example, the data driver DDC and the timing controller TC can be provided together as one driving chip.

[0085] Although the display apparatus DD according to the embodiments has been described with reference to Figure 1 the configuration of the pixels PXij, but the present disclosure is not limited thereto. For example, a signal line can be further added or omitted according to the configuration of the pixels PXij. Also, various modifications can be made to the connection relationship between one pixel and a signal line as needed or desired. When any one of a plurality of signal lines is omitted, another signal line can replace the omitted signal line.

[0086] Figures 2A-2C is an equivalent circuit diagram of the pixels PXij, PXij-1, PXij-2 according to one or more embodiments of the present disclosure. Figures 2A-2C Some example equivalent circuit diagrams of the pixels PXij, PXij-1, and PXij-2 connected to the i-th first scan line (hereinafter, a write scan line) GWLi and the j-th data line (hereinafter, a data line) DLj are illustrated.

[0087] As shown in Figure 2A the pixel PXij includes a light emitting element LD and a pixel driver PDC. The light emitting element LD is connected to the first power line VDL and the pixel driver PDC.

[0088] The pixel driver PDC can be connected to the plurality of scan lines GWLi, GCLi, GBLi, GILi, GRLi, the data line DLj, the i-th emission line ESLi, and the plurality of power lines VDL, VSL, VIL1, VIL2, VRL, and VCL. The pixel driver PDC can include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and an eighth transistor T8, a first capacitor C1, and a second capacitor C2. Each of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 can be, for example, an N-type transistor. However, the disclosure is not limited thereto, and some of the first to eighth transistors T1 to T8 can be N-type transistors, and the remaining ones of the first to eighth transistors T1 to T8 can be P-type transistors. As another example, each of the first to eighth transistors T1 to T8 can be a P-type transistor, but the disclosure is not limited to any particular embodiment.

[0089] The gate of the first transistor T1 can be connected to the first node N1. The first electrode of the first transistor T1 can be connected to the second node N2, and the second electrode of the first transistor T1 can be connected to the third node N3. The first transistor T1 can be a driver transistor. The first transistor T1 can control a drive current ILD flowing from the first power line VDL to the second power line VSL via the light emitting element LD in response to a voltage of the first node N1. For example, the first power supply voltage VDD can have a potential higher than that of the second power supply voltage VSS.

[0090] As used herein, the expression "electrically connected between a transistor and a signal line or between transistors" can mean "a source, a drain, and a gate of the transistor have a shape integrated with the signal line or are connected through a connection electrode."

[0091] The second transistor T2 can include a gate connected to the write scan line GWLi, a first electrode connected to the data line DLj, and a second electrode connected to the first node N1. The second transistor T2 can supply the data signal DATA to the first node N1 in response to a write scan signal GW transmitted through the write scan line GWLi. When the write scan signal GW is supplied to the write scan line GWLi, the second transistor T2 can be turned on to connect the data line DLj and the first node N1 to each other.

[0092] The third transistor T3 can be connected between the first node N1 and a reference voltage line VRL. A first electrode of the third transistor T3 can receive a reference voltage VREF through the reference voltage line VRL, and a second electrode of the third transistor T3 can be connected to the first node N1. In an embodiment, a gate of the third transistor T3 can receive a reset scan signal GR through an i-th fifth scan line (hereinafter, a reset scan line) GRLi. When the reset scan signal GR is supplied to the reset scan line GRLi, the third transistor T3 can be turned on to supply the reference voltage VREF to the first node N1.

[0093] The fourth transistor T4 can be connected between the third node N3 and a first initialization voltage line VIL1. A first electrode of the fourth transistor T4 can be connected to the third node N3, and a second electrode of the fourth transistor T4 can be connected to the first initialization voltage line VIL1 through which the first initialization voltage VINT1 is supplied. The fourth transistor T4 can be referred to as a first initialization transistor. A gate of the fourth transistor T4 can receive a first initialization scan signal GI through an i-th third scan line (hereinafter, a first initialization scan line) GILi. When the first initialization scan signal GI is supplied to the first initialization scan line GILi, the fourth transistor T4 can be turned on to supply the first initialization voltage VINT1 to the third node N3.

[0094] The fifth transistor T5 can be connected between a voltage compensation line VCL and the second node N2. A first electrode of the fifth transistor T5 can receive a compensation voltage VCOMP through the voltage compensation line VCL, and a second electrode of the fifth transistor T5 can be connected to the second node N2 to be electrically connected to the first electrode of the first transistor T1. A gate of the fifth transistor T5 can receive a compensation scan signal GC through an i-th second scan line (hereinafter, a compensation scan line) GCLi. When the compensation scan signal GC is supplied to the compensation scan line GCLi, the fifth transistor T5 can be turned on to provide the compensation voltage VCOMP to the second node N2, and a threshold voltage of the first transistor T1 can be compensated during a compensation period.

[0095] The sixth transistor T6 can be connected between the first electrode of the first transistor T1 and the light emitting element LD. In more detail, the gate of the sixth transistor T6 can receive the emission signal EM through the i-th emission line (hereinafter, emission line) ESLi. The first electrode of the sixth transistor T6 can be connected to the cathode of the light emitting element LD through the fourth node N4, and the second electrode of the sixth transistor T6 can be connected to the first electrode of the first transistor T1 through the second node N2. The sixth transistor T6 can be referred to as a first emission control transistor. When the emission signal EM is supplied to the emission line ESLi, the sixth transistor T6 can be turned on to electrically connect the light emitting element LD and the first transistor T1 to each other.

[0096] The seventh transistor T7 can be connected between the second power line VSL and the third node N3. The first electrode of the seventh transistor T7 can be connected to the second electrode of the first transistor T1 through the third node N3, and the second electrode of the seventh transistor T7 can receive the second supply voltage VSS through the second power line VSL. The gate of the seventh transistor T7 can be electrically connected to the emission line ESLi. The seventh transistor T7 can be referred to as a second emission control transistor. When the emission signal EM is supplied to the emission line ESLi, the seventh transistor T7 can be turned on to electrically connect the second electrode of the first transistor T1 and the second power line VSL to each other.

[0097] In an embodiment, the sixth transistor T6 and the seventh transistor T7 are shown as being connected to the same emission line ESLi to be turned on by the same emission signal EM, but the present disclosure is not limited thereto. The sixth transistor T6 and the seventh transistor T7 can be independently turned on by different signals. Furthermore, in the pixel driver PDC according to an embodiment of the present disclosure, any one of the sixth transistor T6 and the seventh transistor T7 can be omitted as needed or desired.

[0098] The eighth transistor T8 can be connected between the second initialization voltage line VIL2 and the fourth node N4. In other words, the eighth transistor T8 can include a gate connected to the i-th fourth scan line (hereinafter, second initialization scan line) GBLi, a first electrode connected to the second initialization voltage line VIL2, and a second electrode connected to the fourth node N4. The eighth transistor T8 can be referred to as a second initialization transistor. The eighth transistor T8 can supply the second initialization voltage VINT2 to the fourth node N4 corresponding to the cathode of the light emitting element LD in response to the second initialization scan signal GB transmitted through the second initialization scan line GBLi. The cathode of the light emitting element LD can be initialized by the second initialization voltage VINT2.

[0099] In an embodiment, some of the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 can be turned on concurrently with or substantially simultaneously with each other by the same scan signal. For example, the eighth transistor T8 and the fifth transistor T5 can be turned on concurrently with or substantially simultaneously with each other by the same scan signal. For example, the eighth transistor T8 and the fifth transistor T5 can be operated by the same compensation scan signal GC. The eighth transistor T8 and the fifth transistor T5 can be turned on / off concurrently with or substantially simultaneously with each other by the same compensation scan signal GC. In this case, the compensation scan line GCLi and the second initialization scan line GBLi can be provided as the same signal line (e.g., provided as substantially a single scan line). Thus, the initialization of the cathode of the light emitting element LD can be implemented at the same time or substantially at the same time as the threshold voltage compensation of the first transistor T1. However, the disclosure is not limited thereto.

[0100] Further, according to an embodiment of the disclosure, applying the same power voltage can result in the initialization of the cathode of the light emitting element LD and the compensation of the threshold voltage of the first transistor T1. For example, the voltage compensation line VCL and the second initialization voltage line VIL2 can be provided as the same power line (e.g., provided as substantially a single power voltage line). In this case, the cathode initialization and the compensation of the driving transistor can be implemented with one power voltage, and thus, the design of the pixel driver PDC can be simplified. However, the disclosure is not limited thereto.

[0101] The first capacitor C1 can be disposed between the first node N1 and the third node N3. The first capacitor C1 can store a charge corresponding to a voltage difference between the first node N1 and the third node N3. The first capacitor C1 can be referred to as a storage capacitor.

[0102] The second capacitor C2 can be disposed between the third node N3 and the second power line VSL. In other words, one electrode of the second capacitor C2 can be connected to the second power line VSL to which the second power voltage VSS is supplied, and the other electrode of the second capacitor C2 can be connected to the third node N3. The second capacitor C2 can store a charge corresponding to a voltage difference between the second power voltage VSS and the third node N3. The second capacitor C2 can be referred to as a holding capacitor. The second capacitor C2 can have a high storage capacitance compared to the storage capacitance of the first capacitor C1. Thus, the second capacitor C2 can minimize or reduce a voltage change in the third node N3 in response to a voltage change in the first node N1.

[0103] In an embodiment, the light emitting element LD can be connected to the pixel driver PDC through the fourth node N4. The light emitting element LD can include an anode connected to the first power line VDL and a cathode opposite to the anode. In an embodiment, the light emitting element LD can be connected to the pixel driver PDC through the cathode. In other words, in the pixel PXij according to an embodiment of the disclosure, the connection node to which the light emitting element LD is connected, at which the pixel driver PDC is located, can be the fourth node N4, and the fourth node N4 can correspond to the connection node between the first electrode of the sixth transistor T6 and the cathode of the light emitting element LD. Accordingly, the potential of the fourth node N4 can correspond to or substantially correspond to the cathode potential of the light emitting element LD.

[0104] In more detail, the anode of the light emitting element LD can be connected to the first power line VDL to receive the first power voltage VDD as a constant or substantially constant voltage, and the cathode of the light emitting element LD can be connected to the first transistor T1 through the sixth transistor T6. In other words, in an embodiment in which the first transistor T1 to the eighth transistor T8 are N-type transistors, the potential of the third node N3 corresponding to the second electrode (e.g., source) of the first transistor T1 as a driving transistor can not be directly affected by the characteristics of the light emitting element LD. Accordingly, even when the light emitting element LD deteriorates, the gate-source voltage (Vgs) from the driving transistor among the plurality of transistors constituting the pixel driver PDC can be less affected. In other words, the amount of change in the driving current ILD due to the deterioration of the light emitting element LD can be reduced, and thus, the afterimage defect of the display panel due to the increase in the use time can be reduced and the lifespan can be improved.

[0105] In another embodiment, as shown in FIG. 1B, the pixel PXij-1 can include a light emitting element LD and a pixel driver PDC-1 including two transistors T1 and T2 and one first capacitor C1. The pixel driver PDC-1 can be connected to the light emitting element LD, the write scan line GWLi, the data line DLj, the first power line VDL, and the second power line VSL. Figure 2B The pixel driver PDC-1 shown in FIG. 1B can correspond to the pixel driver PDC described above with reference to FIG. 1A, and the third transistor T3 to the eighth transistor T8 and the second capacitor C2 are omitted from the pixel driver PDC. Figure 2B Figure 2A Each of the first transistor T1 and the second transistor T2 can be an N-type transistor or a P-type transistor. For convenience, an example case in which each of the first transistor T1 and the second transistor T2 is an N-type transistor is shown in FIG. 1B.

[0106] Each of the first transistor T1 and the second transistor T2 can be an N-type transistor or a P-type transistor. For convenience, an example case in which each of the first transistor T1 and the second transistor T2 is an N-type transistor is shown in FIG. 1B. Figure 2B Each of the first transistor T1 and the second transistor T2 can be an N-type transistor or a P-type transistor. For convenience, an example case in which each of the first transistor T1 and the second transistor T2 is an N-type transistor is shown in FIG. 1B.​

[0107] The first transistor T1 includes a gate connected to the first node N1, a first electrode connected to the second node N2, and a second electrode connected to the third node N3. The second node N2 can be a node connected to the first power line VDL side, and the third node N3 can be a node connected to the second power line VSL side. The first transistor T1 is connected to the light emitting element LD through the second node N2, and is connected to the second power line VSL through the third node N3. The first transistor T1 can be a driving transistor.

[0108] The second transistor T2 can include a gate configured to receive a write scan signal GW through a write scan line GWLi, a first electrode connected to a data line DLj, and a second electrode connected to the first node N1. The second transistor T2 can supply a data signal DATA to the first node N1 in response to the write scan signal GW transmitted through the write scan line GWLi.

[0109] The first capacitor C1 can include an electrode connected to the first node N1 and an electrode connected to the third node N3. The first capacitor C1 can store a charge corresponding to a voltage difference between the first node N1 and the third node N3.

[0110] The light emitting element LD can include an anode and a cathode. In an embodiment, the anode of the light emitting element LD is connected to the first power line VDL, and the cathode of the light emitting element LD is connected to the pixel driver PDC-1 through the second node N2. In an embodiment, the cathode of the light emitting element LD can be connected to the first transistor T1. The light emitting element LD can emit light in response to an amount of a current ILD flowing through the first transistor T1 of the pixel driver PDC-1.

[0111] In an embodiment in which the first transistor T1 and the second transistor T2 are N-type transistors, the second node N2 to which the light emitting element LD is connected, in which the pixel driver PDC-1 is located, can correspond to a drain of the first transistor T1. In other words, a change in a gate-source voltage (Vgs) of the first transistor T1 due to the light emitting element LD can be prevented or substantially prevented. In other words, an amount of a change in a driving current ILD due to degradation of the light emitting element LD can be reduced, and thus, a residual image defect of a display panel due to an increase in a utilization time can be reduced and a lifespan can be improved.

[0112] In another embodiment, as shown in Figure 2C PXij-2 can include a light emitting element LD and a pixel driver PDC-2 including six transistors T1, T2, T3, T4a, T5a, and T6a and two capacitors C1 and C2.

[0113] The pixel driver PDC-2 can be connected to the light emitting element LD, the write scan line GWLi, the reset scan line GRLi, the compensation scan line GCLi, the i-th first emission line (hereinafter, first emission line) ESL1i, the i-th second emission line (hereinafter, second emission line) ESL2i, the data line DLj, the first power line VDL, the second power line VSL, the third power line VRL, and the initialization voltage line VIL.

[0114] Figure 2C The pixel driver PDC-2 in FIG. 1A can be similar to the structure in which the fourth transistor T4 and the fifth transistor T5 are omitted from the pixel driver PDC described above with reference to FIG. 1. Figure 2A Since the area of the pixel driver PDC-2 in FIG. 1A is smaller than the area of the pixel driver PDC in FIG. 1, a high resolution can be implemented (e.g., can be easily implemented). Figure 2C Since the area of the pixel driver PDC-2 in FIG. 1A is smaller than the area of the pixel driver PDC in FIG. 1, a high resolution can be implemented (e.g., can be easily implemented). Figure 2A Since the area of the pixel driver PDC-2 in FIG. 1A is smaller than the area of the pixel driver PDC in FIG. 1, a high resolution can be implemented (e.g., can be easily implemented).

[0115] Each of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4a, the fifth transistor T5a, and the sixth transistor T6a can be an N-type transistor or a P-type transistor. In an embodiment, for convenience, an example case in which the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4a, the fifth transistor T5a, and the sixth transistor T6a are N-type transistors can be described in more detail hereinafter.

[0116] The first transistor T1 includes a gate connected to a first node N1, a first electrode connected to a second node N2, and a second electrode connected to a third node N3. The second node N2 can be a node connected to a first power line VDL side, and the third node N3 can be a node connected to a second power line VSL side. The first transistor T1 is connected to the light emitting element LD through the second node N2, and is connected to the second power line VSL through the third node N3. The first transistor T1 can be a driving transistor.

[0117] The second transistor T2 can include a gate configured to receive a write scan signal GW through a write scan line GWLi, a first electrode connected to a data line DLj, and a second electrode connected to the first node N1. The second transistor T2 can supply a data signal DATA to the first node N1 in response to the write scan signal GW transmitted through the write scan line GWLi.

[0118] The third transistor T3 can be connected between the first node N1 and a reference voltage line VRL. The first electrode of the third transistor T3 can receive the reference voltage VREF through the reference voltage line VRL, and the second electrode of the third transistor T3 can be connected to the first node N1. In an embodiment, the gate of the third transistor T3 can receive a reset scan signal GR through a reset scan line GRLi. When the reset scan signal GR is supplied to the reset scan line GRLi, the third transistor T3 can supply the reference voltage VREF to the first node N1.

[0119] The fourth transistor T4a can be connected between the first electrode of the first transistor T1 and the light emitting element LD. In more detail, the gate of the fourth transistor T4a can receive the first emission signal EM1 through a first emission line ESL1i. The first electrode of the fourth transistor T4a can be connected to the cathode of the light emitting element LD through a fourth node N4, and the second electrode of the fourth transistor T4a can be connected to the first electrode of the first transistor T1 through a second node N2. The fourth transistor T4a can be referred to as a first emission control transistor. When the first emission signal EM1 is supplied to the first emission line ESL1i, the fourth transistor T4a can be turned on to electrically connect the light emitting element LD and the first transistor T1 to each other.

[0120] The fifth transistor T5a can be connected between the second power line VSL and the third node N3. The first electrode of the fifth transistor T5a can be connected to the second electrode of the first transistor T1 through the third node N3, and the second electrode of the fifth transistor T5a can receive the second supply voltage VSS through the second power line VSL. The gate of the fifth transistor T5a can be electrically connected to a second emission line ESL2i. The fifth transistor T5a can be referred to as a second emission control transistor. When the second emission signal EM2 is supplied to the second emission line ESL2i, the fifth transistor T5a can be turned on to electrically connect the second electrode of the first transistor T1 and the second power line VSL to each other.

[0121] In an embodiment, the fourth transistor T4a and the fifth transistor T5a can be connected to the first emission line ESL1i and the second emission line ESL2i, respectively, to be turned on by the first emission signal EM1 and the second emission signal EM2. In other words, the fourth transistor T4a and the fifth transistor T5a can be independently turned on. However, the present disclosure is not limited thereto. For example, in an embodiment of the present disclosure, the fourth transistor T4a and the fifth transistor T5a can be connected to the same emission line and can be controlled by the same emission signal. Furthermore, in the pixel driver PDC-2 according to an embodiment of the present disclosure, any one of the fourth transistor T4a and the fifth transistor T5a can be omitted as needed or desired.

[0122] The sixth transistor T6a can be connected between the initialization voltage line VIL and the fourth node N4. The sixth transistor T6a can include a gate connected to the compensation scan line GCLi, a first electrode connected to the initialization voltage line VIL, and a second electrode connected to the fourth node N4. The sixth transistor T6a can be referred to as an initialization transistor. The sixth transistor T6a can supply the initialization voltage VINT to the fourth node N4 corresponding to the cathode of the light emitting element LD in response to the compensation scan signal GC transmitted through the compensation scan line GCLi. The cathode of the light emitting element LD can be initialized by the initialization voltage VINT.

[0123] The first capacitor C1 can be disposed between the first node N1 and the third node N3. The first capacitor C1 can store a charge corresponding to a voltage difference between the first node N1 and the third node N3. The first capacitor C1 can be referred to as a storage capacitor.

[0124] The second capacitor C2 can be disposed between the third node N3 and the second power line VSL. In other words, one electrode of the second capacitor C2 can be connected to the second power line VSL to receive the second supply voltage VSS supplied thereto, and the other electrode of the second capacitor C2 can be connected to the third node N3. The second capacitor C2 can store a charge corresponding to a voltage difference between the second supply voltage VSS and the third node N3. The second capacitor C2 can be referred to as a holding capacitor.

[0125] The light emitting element LD can include an anode and a cathode. In an embodiment, the anode of the light emitting element LD is connected to the first power line VDL, and the cathode of the light emitting element LD is connected to the pixel driver PDC-2 through the fourth node N4. In an embodiment, the cathode of the light emitting element LD can be connected to the first transistor T1 through the fourth transistor T4a. The light emitting element LD can emit light corresponding to an amount of the current ILD flowing through the first transistor T1 of the pixel driver PDC-2.

[0126] In an embodiment in which the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4a, the fifth transistor T5a, and the sixth transistor T6a are N-type transistors, the potential of the third node N3 corresponding to the second electrode (e.g., the source) of the first transistor T1 as a driving transistor can not be directly affected by the characteristics of the light emitting element LD. Accordingly, even when the light emitting element LD deteriorates, the deterioration can less affect a gate-source voltage (Vgs) from the driving transistor among the plurality of transistors constituting the pixel driver PDC-2. In other words, the amount of change in the driving current ILD due to the deterioration of the light emitting element LD can be reduced, and thus, the afterimage defect of the display panel due to an increase in the use time can be reduced and the lifespan can be improved.

[0127] Figure 2A 、 Figure 2B and Figure 2C Pixel drivers PDC, PDC-1, and PDC-2 according to some embodiments of the disclosure are shown, and a display panel according to embodiments of the disclosure can be designed in various suitable ways in terms of the number or arrangement relationship of transistors or capacitors, and thus, is not limited to any particular embodiment as long as the pixel driver is connected to the cathode of the light emitting element LD.

[0128] Figure 3A and Figure 3B are plan views of a display panel according to one or more embodiments of the disclosure. In Figure 3A and Figure 3B , some components are not shown for ease of illustration. Hereinafter, some embodiments of the disclosure will be described in more detail with reference to Figure 3A and Figure 3B .

[0129] Referring to Figure 3A , a display panel DP according to an embodiment can be divided into a display area DA and a peripheral area (e.g., a non-display area) NDA. The display area DA includes a plurality of light emitting portions EP.

[0130] The light emitting portion EP can be an area in which a corresponding pixel PXij (see, for example, Figure 1 ) emits light. In more detail, each of the plurality of light emitting portions EP can correspond to a corresponding emission opening OP-PDL (see, for example, Figure 5 ) which will be described in more detail later.

[0131] The peripheral area NDA can be disposed adjacent to the display area DA. In an embodiment, the peripheral area NDA can surround an edge of the display area DA (e.g., around a periphery of an edge of the display area DA). However, the disclosure is not limited thereto, and the peripheral area NDA can be disposed at one side of the display area DA (e.g., only at one side of the display area DA), or omitted as needed or desired.

[0132] In an embodiment, the scan driver SDC and the data driver DDC can be mounted in the display panel DP. In an embodiment, the scan driver SDC can be disposed in the display area DA, and the data driver DDC can be disposed in the non-display area NDA. The scan driver SDC can overlap at least some of the plurality of light emitting parts EP disposed in the display area DA in a plan view. Because the scan driver SDC is disposed in the display area DA, the area of the non-display area NDA can be reduced compared to the area of the non-display area of a display apparatus in which a scan driver is disposed in a non-display area, and thus, a display apparatus having a thin bezel can be implemented (e.g., can be easily implemented).

[0133] However, the present disclosure is not limited thereto, and unlike that shown in Figure 3A The scan driver SDC can include two separate parts, unlike that shown in

[0134] Although Figure 3A An example of a display panel DP in which the data driver DDC is disposed in the non-display area NDA is shown, but the present disclosure is not limited thereto, and the data driver DDC can be disposed in the display area DA. In this case, some of the plurality of light emitting parts EP disposed in the display area DA can overlap the data driver DDC in a plan view.

[0135] In an embodiment, the data driver DDC can be provided as a driver chip that is separate from the display panel DP and will be connected to the display panel DP. However, the present disclosure is not limited thereto, and the data driver DDC can be provided in the same process as that of the scan driver SDC so as to constitute the display panel DP, and the present disclosure is not limited to any particular embodiment.

[0136] Referring to Figure 3B , the display panel DP can have a shape in which a length of the display panel DP in the first direction DR1 is longer than a length of the display panel DP in the second direction DR2. As an example, the plurality of pixels PX11 to PXnm can be arranged in n rows and m columns in the display area DA, where n and m are integers greater than 1. In an embodiment, the display panel DP can include a plurality of scan drivers SDC1 and SDC2. The scan drivers SDC1 and SDC2 can include a first scan driver SDC1 and a second scan driver SDC2 spaced apart from each other in the first direction DR1.

[0137] The first scan driver SDC1 may be connected to some of the scan lines GL1 to GLn, and the second scan driver SDC2 may be connected to the others of the scan lines GL1 to GLn. For example, the first scan driver SDC1 may be connected to the odd scan lines among the scan lines GL1 to GLn, and the second scan driver SDC2 may be connected to the even scan lines among the scan lines GL1 to GLn.

[0138] For ease of explanation, Figure 3B pads PD of the data lines DL1 to DLm are shown. The pads PD may be defined at the ends of the data lines DL1 to DLm. The data lines DL1 to DLm may be connected to the data driver DDC through the pads PD (for example, see Figure 3A ).

[0139] According to an embodiment of the present disclosure, some of the plurality of pads PD may be disposed in the peripheral area NDA, at a position where the plurality of pads PD are spaced apart from each other and the display area DA is interposed between the plurality of pads PD. For example, some of the plurality of pads PD may be disposed on the upper side (such as a side adjacent to the first scan line GL1 among the scan lines GL1 to GLn), and others of the plurality of pads PD may be disposed on the lower side (such as a side adjacent to the last scan line GLn among the scan lines GL1 to GLn). In an embodiment, the pads PD connected to the odd data lines among the data lines DL1 to DLm may be disposed on the upper side, and the pads PD connected to the even data lines among the data lines DL1 to DLm may be disposed on the lower side.

[0140] The display panel DP may include a plurality of upper data drivers connected to the pads PD disposed on the upper side and / or a plurality of lower data drivers connected to the pads PD disposed on the lower side. However, the present disclosure is not limited thereto, and the display panel DP may include one upper data driver connected to the pads PD disposed on the upper side and / or one lower data driver connected to the pads PD disposed on the lower side. The pads PD according to an embodiment of the present disclosure may also be disposed at one side of the display panel DP (for example, disposed at only one side of the display panel DP) to be connected to a single data driver, and the present disclosure is not limited to any specific embodiment.

[0141] In addition, as described above with reference to Figure 3A the display panel DP in Figure 3B may also include a scan driver and / or a data driver disposed in the display area DA, and thus, some of the plurality of light emitting portions disposed in the display area DA may overlap with the scan driver and / or the data driver in a plan view.

[0142] Figures 4A-4Dis an enlarged plan view of a partial area of a display panel according to one or more embodiments of the present disclosure.

[0143] Figure 4A An example of light emitting units (e.g., light emitting unit areas) UT11, UT12, UT21, and UT22 arranged in two rows and two columns is shown. Each light emitting unit UT11, UT12, UT21, and UT22 can be an area in which a plurality of light emitting portions EP1, EP2, and EP3 are disposed. Referring to Figure 4A , the light emitting portions EP1, EP2, and EP3 in the first row Rk constitute the light emitting unit UT11 in the first row Rk and the first column and the light emitting unit UT12 in the first row Rk and the second column. The light emitting portions EP1, EP2, and EP3 in the second row Rk+1 constitute the light emitting unit UT21 in the second row Rk+1 and the first column and the light emitting unit UT22 in the second row Rk+1 and the second column.

[0144] The light emitting portions EP1, EP2, and EP3 can correspond to emission openings OP-PDL (see, for example, Figure 5 ) to be described in greater detail later. In more detail, each of the light emitting portions EP1, EP2, and EP3 can be an area in which light is emitted by a corresponding light emitting element. The light emitting portions EP1, EP2, and EP3 can correspond to units (e.g., the smallest units) for constituting an image displayed in a display panel DP (see, for example, Figure 1 ).

[0145] The light emitting portions EP1, EP2, and EP3 can include a first light emitting portion EP1, a second light emitting portion EP2, and a third light emitting portion EP3. The first light emitting portion EP1, the second light emitting portion EP2, and the third light emitting portion EP3 can emit light of different colors from each other. For example, the first light emitting portion EP1 can emit red light, the second light emitting portion EP2 can emit green light, and the third light emitting portion EP3 can emit blue light, but the present disclosure is not limited thereto, and the color combination of light emitted from the light emitting portions EP1, EP2, and EP3 can be variously modified as needed or desired. In some embodiments, at least two of the light emitting portions EP1, EP2, and EP3 can emit light of the same color as each other. For example, all of the first light emitting portion EP1, the second light emitting portion EP2, and the third light emitting portion EP3 can emit blue light or white light.

[0146] The third light emitting portion EP3 among the light emitting portions EP1, EP2, and EP3 from the third light emitting element can emit light emitted by the third light emitting element, and can include two sub light emitting portions EP31 and EP32 spaced apart from each other in the second direction DR2. However, the disclosure is not limited thereto, and the third light emitting portion EP3 can be provided with a one-body shaped pattern similar to the pattern of the first light emitting portion EP1 and the second light emitting portion EP2. As another example, at least one of the first light emitting portion EP1 and the second light emitting portion EP2 can also include sub light emitting portions spaced apart from each other, and the disclosure is not limited to any particular embodiment.

[0147] The light emitting portions in the first row Rk can include the first light emitting portion EP1, the second light emitting portion EP2, and the third light emitting portion EP3 constituting the light emitting unit UT11 in the first row Rk and the first column, and the first light emitting portion EP1, the second light emitting portion EP2, and the third light emitting portion EP3 (e.g., the third light emitting portion EP3a) constituting the light emitting unit UT12 in the first row Rk and the second column. The light emitting portions in the second row Rk+1 can include the first light emitting portion EP1, the second light emitting portion EP2, and the third light emitting portion EP3 (e.g., the third light emitting portion EP3a) constituting the light emitting unit UT21 in the second row Rk+1 and the first column, and the first light emitting portion EP1, the second light emitting portion EP2, and the third light emitting portion EP3 constituting the light emitting unit UT22 in the second row Rk+1 and the second column.

[0148] In an embodiment of the disclosure, the light emitting portion constituting the light emitting unit UT11 in the first row Rk and the first column can have the same or substantially the same shape as the light emitting portion constituting the light emitting unit UT22 in the second row Rk+1 and the second column. In addition, the light emitting portion constituting the light emitting unit UT12 in the first row Rk and the second column can have the same or substantially the same shape as the light emitting portion constituting the light emitting unit UT21 in the second row Rk+1 and the first column. The light emitting portion constituting the light emitting unit UT11 in the first row Rk and the first column can have a different shape from the light emitting portion constituting the light emitting unit UT12 in the first row Rk and the second column. For example, a portion of the light emitting portion in the first row Rk can have a symmetrical shape with respect to the light emitting portion in the second row Rk+1.

[0149] In an embodiment of the disclosure, the third light emitting part EP3a of the light emitting unit UT21 in the second row Rk+1 and the first column and the third light emitting part EP3 of the light emitting unit UT11 in the first row Rk and the first column can have a linearly symmetrical shape and arrangement with respect to an axis parallel to the first direction DR1. The third light emitting part EP3a of the light emitting unit UT12 in the first row Rk and the second column and the third light emitting part EP3 of the light emitting unit UT22 in the second row Rk+1 and the second column can have a linearly symmetrical shape and arrangement with respect to an axis parallel to the first direction DR1. However, the disclosure is not limited thereto.

[0150] Figure 4B The light emitting parts arranged in a row are illustrated. For ease of illustration, Figure 4B The plurality of second electrodes EL2_1, EL2_2, and EL2_3, the plurality of pixel drivers PDC1, PDC2, and PDC3, the first connection electrode CNE1, the second connection electrode CNE2, and the third connection electrode CNE3, and the separator SPR are illustrated. Figure 4C The separator SPR among the plurality of components from the display panel DP, the plurality of light emitting parts EP1, EP2, and EP3 disposed in the region divided by the separator SPR, and the plurality of connection electrodes CNE1, CNE2, and CNE3 are illustrated.

[0151] Referring to Figure 4B and Figure 4C The second electrodes EL2_1, EL2_2, and EL2_3 can be separated from each other by the separator SPR and can be electrically disconnected from each other. In an embodiment, one light emitting unit UT11 can include three light emitting parts EP1, EP2, and EP3. Accordingly, the light emitting unit UT11 can include three second electrodes (hereinafter, referred to as a first cathode, a second cathode, and a third cathode) EL2_1, EL2_2, and EL2_3, three pixel drivers PDC1, PDC2, and PDC3, and three connection electrodes CNE1, CNE2, and CNE3. However, the disclosure is not limited thereto, and the number and arrangement of the light emitting parts included in the light emitting unit UT11 can be variously modified as needed or desired.

[0152] The first pixel driver PDC1, the second pixel driver PDC2, and the third pixel driver PDC3 can be electrically connected to the light emitting elements LD1, LD2, and LD3 including the first light emitting part EP1, the second light emitting part EP2, and the third light emitting part EP3, respectively. As used herein, the term "connected" can include a case of being directly physically connected to each other by contact as well as a case of being electrically connected to each other.

[0153] Further, as Figure 4BThe first pixel driver PDC1, the second pixel driver PDC2, and the third pixel driver PDC3 can be arranged in sequence along the first direction DR1. However, the arrangement positions of the first pixel driver PDC1, the second pixel driver PDC2, and the third pixel driver PDC3 can be designed regardless of the positions and shapes of the first light emitting portion EP1, the second light emitting portion EP2, and the third light emitting portion EP3. Figure 2A ) of the pixel driver (pixel circuit) PDC that configures a light emitting element for driving a pixel.

[0154] The first pixel driver PDC1, the second pixel driver PDC2, and the third pixel driver PDC3 can be arranged in sequence along the first direction DR1. However, the arrangement positions of the first pixel driver PDC1, the second pixel driver PDC2, and the third pixel driver PDC3 can be designed regardless of the positions and shapes of the first light emitting portion EP1, the second light emitting portion EP2, and the third light emitting portion EP3.

[0155] For example, the first pixel driver PDC1, the second pixel driver PDC2, and the third pixel driver PDC3 can be arranged in the regions divided and defined by the partition SPR. The first pixel driver PDC1, the second pixel driver PDC2, and the third pixel driver PDC3 can be arranged at positions different from the positions where the first cathode EL2_1, the second cathode EL2_2, and the third cathode EL2_3 are provided, or can have areas and shapes different from the areas and shapes of the first cathode EL2_1, the second cathode EL2_2, and the third cathode EL2_3. As another example, the first pixel driver PDC1, the second pixel driver PDC2, and the third pixel driver PDC3 can be arranged to overlap the positions where the first light emitting portion EP1, the second light emitting portion EP2, and the third light emitting portion EP3 exist, respectively, and can also have areas / regions similar to the areas / regions divided and defined by the partition SPR, such as exemplified by the areas / regions of the first cathode EL2_1, the second cathode EL2_2, and the third cathode EL2_3.

[0156] In the embodiment, each of the first pixel driver PDC1, the second pixel driver PDC2, and the third pixel driver PDC3 is illustrated as having a rectangular shape, and each of the first light emitting portion EP1, the second light emitting portion EP2, and the third light emitting portion EP3 is illustrated as being arranged to have an area smaller than that of the first pixel driver PDC1 to the third pixel driver PDC3 and a type different from that of the first pixel driver PDC1 to the third pixel driver PDC3. The first cathode EL2_1, the second cathode EL2_2, and the third cathode EL2_3 can be provided to overlap the first light emitting portion EP1, the second light emitting portion EP2, and the third light emitting portion EP3, respectively, and can have an irregular shape.

[0157] Thus, as Figure 4BAs illustrated in FIG. 1, the first pixel driver PDC1 can be disposed to partially overlap with the first light emitting portion EP1, the second light emitting portion EP2, and another adjacent light emitting portion. The second pixel driver PDC2 can be disposed to overlap with the first light emitting portion EP1, the second light emitting portion EP2, and the third cathode EL2_3. The third pixel driver PDC3 can be disposed to overlap with the third light emitting portion EP3. However, the present disclosure is not limited thereto, and the first pixel driver PDC1, the second pixel driver PDC2, and the third pixel driver PDC3 can have various suitable shapes and arrangements regardless of the first light emitting portion EP1, the second light emitting portion EP2, and the third light emitting portion EP3.

[0158] The light emitting unit UT11 can include a first connection electrode CNE1, a second connection electrode CNE2, and a third connection electrode CNE3. The first connection electrode CNE1 can electrically connect the first light emitting element LD1 constituting (e.g., defining) the first light emitting portion EP1 and the first pixel driver PDC1 to each other. The second connection electrode CNE2 can connect the second light emitting element LD2 constituting (e.g., defining) the second light emitting portion EP2 and the second pixel driver PDC2 to each other. The third connection electrode CNE3 can connect the third light emitting element LD3 constituting (e.g., defining) the third light emitting portion EP3 and the third pixel driver PDC3 to each other. Each of the first light emitting element LD1, the second light emitting element LD2, and the third light emitting element LD3 can include a first electrode EL1 (e.g., see Figure 5 ), an intermediate layer IML (e.g., see Figure 5 ) disposed on the first electrode EL1, and a second electrode EL2 (e.g., see Figure 5 ) disposed on the intermediate layer IML.

[0159] In more detail, the first connection electrode CNE1, the second connection electrode CNE2, and the third connection electrode CNE3 can connect the first cathode EL2_1, the second cathode EL2_2, and the third cathode EL2_3 in one-to-one correspondence with the first pixel driver PDC1, the second pixel driver PDC2, and the third pixel driver PDC3. For example, the first connection electrode CNE1 can be electrically connected to the first pixel driver PDC1 and the first cathode EL2_1, the second connection electrode CNE2 can be electrically connected to the second pixel driver PDC2 and the second cathode EL2_2, and the third connection electrode CNE3 can be electrically connected to the third pixel driver PDC3 and the third cathode EL2_3.

[0160] The first connection electrode CNE1, the second connection electrode CNE2, and the third connection electrode CNE3 can be disposed in a pixel defining layer PDL (e.g., see Figure 5The first connection electrode CNE1, the second connection electrode CNE2, and the third connection electrode CNE3 can have a ring shape around the corresponding first light emitting portion EP1, the second light emitting portion EP2, and the third light emitting portion EP3 (e.g., around a periphery of the corresponding first light emitting portion EP1, the second light emitting portion EP2, and the third light emitting portion EP3). In an embodiment of the disclosure, each of the first connection electrode CNE1, the second connection electrode CNE2, and the third connection electrode CNE3 is illustrated as having a ring shape formed by a closed line, but the disclosure is not limited thereto. For example, at least a portion of the first connection electrode CNE1, the second connection electrode CNE2, and the third connection electrode CNE3 can have an open ring shape in which a portion thereof is broken.

[0161] Since the first connection electrode CNE1, the second connection electrode CNE2, and the third connection electrode CNE3 have a ring shape, the degree of freedom in which the first connection electrode CNE1, the second connection electrode CNE2, and the third connection electrode CNE3 are connected to positions at which the first pixel driver PDC1, the second pixel driver PDC2, and the third pixel driver PDC3 are located, respectively, can be improved. For example, the first connection electrode CNE1 can be connected to the first pixel driver PDC1 through the first connection portion CE1, the second connection electrode CNE2 can be connected to the second pixel driver PDC2 through the second connection portion CE2, and the third connection electrode CNE3 can be connected to the third pixel driver PDC3 through the connection line CN3. However, there can be no connection line additionally connected to the first connection electrode CNE1 and the second connection electrode CNE2.

[0162] One connection line CN3 can electrically connect the third pixel driver PDC3 and the third light emitting element LD3 constituting the third light emitting portion EP3 to each other. In more detail, the connection line CN3 can correspond to a light emitting element LD (e.g., see FIG. 1A) connected to a pixel driver (e.g., see Figures 2A-2C ) connected to a node (e.g., Figure 2A ) in which the pixel driver PDC-1 or Figure 2B ) in which the pixel driver PDC-2) is located. Figure 2C Figure 2A Figure 2B Figure 2C

[0163] The connection line CN3 can include a third connection portion CE3 and a driving connection portion CD3. The third connection portion CE3 can be provided to one side of the connection line CN3, and the driving connection portion CD3 can be provided to the other side (e.g., the opposite side) of the connection line CN3.

[0164] ​​​​The drive connection portion CD3 can be a portion of the connection line CN3 that is connected to the third pixel driver PDC3. In an embodiment, the drive connection portion CD3 can be connected to one electrode of a transistor that makes up the third pixel driver PDC3. In more detail, the drive connection portion CD3 can be connected to the drain of the sixth transistor T6 in Figure 2A or the drain of the fourth transistor T4a in Figure 2C Thus, the position of the drive connection portion CD3 can correspond to the position of the transistor in the corresponding third pixel driver PDC3 that is physically connected to the connection line CN3. The third connection portion CE3 can be a portion of the connection line CN3 that is connected to the third light emitting element LD3. In an embodiment, the third connection portion CE3 can be connected to the third connection electrode CNE3.

[0165] The first connection electrode CNE1 can include a first edge EG11 that surrounds at least a portion of the first light emitting portion EP1 (e.g., around a periphery of at least a portion of the first light emitting portion EP1) and a second edge EG12 that surrounds the first edge EG11 (e.g., around a periphery of the first edge EG11). The second connection electrode CNE2 can include a first edge EG21 that surrounds at least a portion of the second light emitting portion EP2 (e.g., around a periphery of at least a portion of the second light emitting portion EP2) and a second edge EG22 that surrounds the first edge EG21 (e.g., around a periphery of the first edge EG21). The third connection electrode CNE3 can include a first edge EG31 that surrounds at least a portion of the third light emitting portion EP3 (e.g., around a periphery of at least a portion of the third light emitting portion EP3) and a second edge EG32 that surrounds the first edge EG31 (e.g., around a periphery of the first edge EG31).

[0166] The first connection electrode CNE1, the second connection electrode CNE2, and the third connection electrode CNE3 can be spaced apart from each other. For example, gaps GP1, GP2, and GP3 between multiple adjacent connection electrodes from among the first connection electrode CNE1, the second connection electrode CNE2, and the third connection electrode CNE3 can overlap with the spacer SPR. For example, the first edges EG11, EG21, and EG31 of the first connection electrode CNE1, the second connection electrode CNE2, and the third connection electrode CNE3 can not be covered by the spacer SPR, and the second edges EG12, EG22, and EG32 of the first connection electrode CNE1, the second connection electrode CNE2, and the third connection electrode CNE3 can overlap with the spacer SPR. As another example, the second edges EG12, EG22, and EG32 of the first connection electrode CNE1, the second connection electrode CNE2, and the third connection electrode CNE3 can be covered by the spacer SPR.

[0167] In embodiments of the disclosure, the first connection part CE1, the second connection part CE2, and the third connection part CE3 can be disposed at positions non-overlapping with the light emitting parts EP1, EP2, and EP3 in a plan view. For example, the emission opening OP-PDL (see, for example, Figure 5 ) and the through-hole OP-P spaced apart from the emission opening OP-PDL can be defined in the pixel definition layer PDL.

[0168] The through-hole OP-P can include a first through-hole OP-P1, a second through-hole OP-P2, and a third through-hole OP-P3. The first connection part CE1, the second connection part CE2, and the third connection part CE3 can be arranged to correspond to the first through-hole OP-P1, the second through-hole OP-P2, and the third through-hole OP-P3, respectively. The emission opening OP-PDL can include a first emission opening OP-PDL1, a second emission opening OP-PDL2, and a third emission opening OP-PDL3. The first light emitting part EP1, the second light emitting part EP2, and the third light emitting part EP3 can be defined to correspond to the first emission opening OP-PDL1, the second emission opening OP-PDL2, and the third emission opening OP-PDL3, respectively. Accordingly, the first connection part CE1, the second connection part CE2, and the third connection part CE3 can be spaced apart from the first light emitting part EP1, the second light emitting part EP2, and the third light emitting part EP3.

[0169] The first connection electrode CNE1, the second connection electrode CNE2, and the third connection electrode CNE3 can be arranged on the pixel definition layer PDL (see, for example, Figure 5 ). In a plan view, the first connection electrode CNE1 can surround the first emission opening OP-PDL1 (for example, around a periphery of the first emission opening OP-PDL1), the second connection electrode CNE2 can surround the second emission opening OP-PDL2 (for example, around a periphery of the second emission opening OP-PDL2), and the third connection electrode CNE3 can surround the third emission opening OP-PDL3 (for example, around a periphery of the third emission opening OP-PDL3).

[0170] According to embodiments of the disclosure, the driving connection part CD3 at which the connection line CN3 is connected with the transistor TR1 of the third pixel driver PDC3 (see, for example, Figure 10 ) can be defined at a position non-overlapping with the third connection part CE3 in a plan view, and can be disposed at a position overlapping with the third light emitting part EP3 in a plan view. For example, the connection line CN3 can correspond to the connection line CN-ad described in more detail later with reference to Figure 10 . The driving connection part CD3 can correspond to a portion in contact with the intermediate connection electrode CN in Figure 10 . The third connection part CE3 can correspond to a portion in contact with the intermediate connection electrode CN in Figure 10The portion of the connection electrode CNEa in the first cathode EL2_1 contacts. Since the third cathode EL2_3 is connected to the third pixel driver PDC3 through the connection line CN3, it is possible to reduce the restriction according to the position or shape of the third light emitting part EP3 to improve the degree of freedom of its design.

[0171] The first cathode EL2_1, the second cathode EL2_2, and the third cathode EL2_3 can be connected with the first connection electrode CNE1, the second connection electrode CNE2, and the third connection electrode CNE3, respectively. For example, the bottom surface of the first cathode EL2_1, the second cathode EL2_2, and the third cathode EL2_3 can be connected with (e.g., can contact) the top surface of the first connection electrode CNE1, the second connection electrode CNE2, and the third connection electrode CNE3, respectively. Thus, it is possible to further improve the contact reliability (e.g., connection stability) between the first cathode EL2_1, the second cathode EL2_2, and the third cathode EL2_3 and the first connection electrode CNE1, the second connection electrode CNE2, and the third connection electrode CNE3, respectively.

[0172] Further, the connection region in which the first cathode EL2_1, the second cathode EL2_2, and the third cathode EL2_3 are connected with the first connection electrode CNE1, the second connection electrode CNE2, and the third connection electrode CNE3, respectively, can surround at least a portion of the first emission opening OP-PDL1, the second emission opening OP-PDL2, and the third emission opening OP-PDL3, respectively (e.g., around the periphery of at least a portion of the first emission opening OP-PDL1, the second emission opening OP-PDL2, and the third emission opening OP-PDL3). The first cathode EL2_1, the second cathode EL2_2, and the third cathode EL2_3 can be connected with the first connection electrode CNE1, the second connection electrode CNE2, and the third connection electrode CNE3, respectively, in a region adjacent to the partition SPR, and each of the plurality of connection regions can be defined adjacent to the partition SPR. For example, the first cathode EL2_1, the second cathode EL2_2, and the third cathode EL2_3 can be connected with the first connection electrode CNE1, the second connection electrode CNE2, and the third connection electrode CNE3, respectively, not at a specific point but in a relatively wide region (e.g., such as across a region having a shape similar to that of the first connection electrode CNE1, the second connection electrode CNE2, and the third connection electrode CNE3). Thus, it is possible to increase the area of the connection region to achieve a more stable connection.

[0173] Figure 4D The partition SPR, the light emitting parts EP1, EP2, and EP3, and the first electrode EL1 are shown.

[0174] Referring to Figure 4D, a light emitting element LD according to an embodiment of the present disclosure (see, for example, Figure 5 ) can be commonly provided to the first light emitting portion EP1, the second light emitting portion EP2, and the third light emitting portion EP3. In other words, the anode EL1 can be provided as a layer that is entirely or substantially entirely integrated with the display area DA, and thus, the anode layer of the anode EL1 can be disposed to overlap the partition SPR. As another example, the anode EL1 of each of the plurality of light emitting elements LD can be provided with a conductive pattern spaced apart from the other anodes, and can be electrically connected to the other anodes through another conductive layer. In this case, the anode EL1 does not overlap the partition SPR.

[0175] As described above, the anode EL1 can be applied with the first power supply voltage VDD (see, for example, Figure 2A ), and all of the plurality of light emitting portions EP1, EP2, and EP3 can be applied with a common voltage. The anode EL1 can also be connected with a first power line VDL (see, for example, Figure 2A ) through which the first power supply voltage VDD is supplied in the non-display area NDA, or can be connected with the first power line VDL in the display area DA, and the present disclosure is not limited to any particular embodiment.

[0176] According to an embodiment, a plurality of openings can be defined in the anode EL1, and the openings can penetrate the anode layer of the anode EL1. The openings in the anode layer of the anode EL1 can be disposed at positions that do not overlap the light emitting portion EP (see, for example, Figure 3A ) in a plan view, and can be defined at positions that overlap the partition SPR in a plan view. The openings can facilitate the discharge of gas that can be generated from an organic layer disposed below the anode EL1 (generated, for example, from the sixth insulating layer 60 (see, for example, Figure 5 ) to be described in greater detail later). Thus, in a process of manufacturing the display panel, gas from an organic layer disposed below the light emitting element can be sufficiently discharged, and after manufacturing, the discharge of gas from the organic layer can be reduced to decrease the rate of degradation of the light emitting element.

[0177] Figure 5 is a cross-sectional view of a display panel DP according to an embodiment of the present disclosure. Figure 5 shows a portion corresponding to a line I-I' in Figure 4A .

[0178] Referring to Figure 5According to an embodiment, the display panel DP can include a base layer BS, a driving element layer DDL, a light emitting element layer LDL, an encapsulation layer ECL, and a sensing layer ISL. However, the present disclosure is not limited thereto, and in an embodiment, the display panel DP can not include the sensing layer ISL.

[0179] The driving element layer DDL can include a plurality of insulating layers 10, 20, 30, 40, 50, and 60 disposed on the base layer BS, and a plurality of conductive patterns and semiconductor patterns disposed between the insulating layers 10, 20, 30, 40, 50, and 60. The conductive patterns and the semiconductor patterns can be disposed between the insulating layers 10, 20, 30, 40, 50, and 60 to constitute the pixel drivers PDC1 and PDC2. For convenience of explanation, Figure 5 An example cross-section from any one of a plurality of regions in which one light emitting part is disposed is illustrated.

[0180] The base layer BS can be a member for providing a base surface on which the pixel drivers PDC1 and PDC2 are disposed. The base layer BS can be a rigid substrate or a flexible substrate that is bendable, foldable, or rollable, etc. The base layer BS can be a glass substrate, a metal substrate, or a polymer substrate, etc. However, the present disclosure is not limited thereto, and the base layer BS can be an inorganic layer, an organic layer, or a composite material layer.

[0181] The base layer BS can have a multi-layer structure. The base layer BS can include a first polymer resin layer, a silicon oxide (SiO x ) layer disposed on the first polymer resin layer, an amorphous silicon (a-Si) layer disposed on the silicon oxide layer, and a second polymer resin layer disposed on the amorphous silicon layer. The silicon oxide layer and the amorphous silicon layer can be referred to as a base barrier layer.

[0182] The first polymer resin layer or the second polymer resin layer can include a polyimide-based resin. In addition, the first polymer resin layer or the second polymer resin layer can include at least one from among an acrylic-based resin, a methacrylic-based resin, a polyisoprene-based resin, a vinyl-based resin, an epoxy-based resin, a urethane-based resin, a cellulose-based resin, a siloxane-based resin, a polyamide-based resin, and a perylene-based resin. As used herein, the expression “~-based” resin means to include a functional group of “~”.

[0183] The insulating layers 10, 20, 30, 40, 50, and 60, the conductive layer or the semiconductor layer provided on the base layer BS can be provided in a suitable method such as coating or deposition. Then, the insulating layers 10, 20, 30, 40, 50, and 60, the semiconductor layer, and the conductive layer can be selectively patterned by a plurality of photolithography processes to provide holes in the insulating layers 10, 20, 30, 40, 50, and 60 and / or to provide a semiconductor pattern, a conductive pattern, or a signal line, and the like in the insulating layers 10, 20, 30, 40, 50, and 60.

[0184] The drive element layer DDL can include the first insulating layer 10, the second insulating layer 20, the third insulating layer 30, the fourth insulating layer 40, the fifth insulating layer 50, and the sixth insulating layer 60, and the pixel drivers PDC1 and PDC2 sequentially stacked on the base layer BS. Figure 5 Examples of the first pixel driver PDC1 and the second pixel driver PDC2 in Figure 4A and Figure 4B are shown. The first pixel driver PDC1 is shown to include one transistor TR1 and two capacitors C1 and C2, and the second pixel driver PDC2 is shown to include one transistor TR2. The transistor TR2 can be one of a plurality of transistors included in the second pixel driver PDC2.

[0185] The transistor TR1 of the first pixel driver PDC1 can correspond to a connection transistor connected to the light-emitting element LD through an intermediate connection electrode CN and a connection electrode CNE, such as a connection transistor connected to a node corresponding to a cathode of the light-emitting element LD (e.g., the fourth node N4 in Figure 2A the second node N2 in Figure 2B or the fourth node N4 in Figure 2C ). For example, the transistor TR1 can correspond to the sixth transistor T6 in Figure 2A the first transistor T1 in Figure 2B or the fourth transistor T4a in Figure 2C . Hereinafter, the transistor TR1 of the first pixel driver PDC1 can be referred to as a connection transistor TR1. The light-emitting element LD electrically connected to the first pixel driver PDC1 can be the first light-emitting element LD1 (e.g., see Figure 4C ).

[0186] The second pixel driver PDC2 can be electrically connected to the second light-emitting element LD2 adjacent to the first light-emitting element LD1 (e.g., see Figure 4C ). For example, the second pixel driver PDC2 can be electrically connected to the second light-emitting element LD2 through an intermediate connection electrode and a second connection electrode CNE2 (e.g., see Figure 4C ).

[0187] The other transistors constituting the pixel driver PDC1 or PDC2 can have the same or substantially the same structure as that of the transistor TR1 or TR2 in Figure 5 However, the disclosure is not limited thereto, and the other transistors constituting the pixel driver PDC1 or PDC2 can have a structure different from that of the transistor TR1 or TR2 in Figure 5

[0188] The first insulating layer 10 can be disposed on the base substrate BS. The first insulating layer 10 can include an inorganic material and / or an organic material, and can have a single layer structure or a multi-layer structure. The first insulating layer 10 can include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. In an embodiment, the first insulating layer 10 is illustrated as a single silicon oxide layer in Figure 5 The insulating layer to be described in greater detail later can include an inorganic layer and / or an organic layer, and have a single layer structure or a multi-layer structure. The inorganic layer can include at least one of the above-described materials, but the disclosure is not limited thereto.

[0189] The first insulating layer 10 can cover the bottom conductive layer BCL1 or BCL2. The display panel DP can further include the bottom conductive layer BCL1 or BCL2 disposed to overlap the transistor TR1 or TR2. The bottom conductive layer BCL1 or BCL2 can prevent a potential caused by polarization of the base substrate BS from affecting the transistor TR1 or TR2. In addition, the bottom conductive layer BCL1 or BCL2 can block light entering the transistor TR1 or TR2 from below. At least one of an inorganic barrier layer and a buffer layer can be further disposed between the bottom conductive layer BCL1 or BCL2 and the base substrate BS.

[0190] The bottom conductive layer BCL1 or BCL2 can include a reflective metal. For example, the bottom conductive layer BCL1 or BCL2 can include titanium (Ti), molybdenum (Mo), a molybdenum-containing alloy, aluminum (Al), an aluminum-containing alloy, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), or copper (Cu), etc.

[0191] ​The bottom conductive layer BCL1 or BCL2 can include a first bottom conductive layer BCL1 or a second bottom conductive layer BCL2. In an embodiment, the first bottom conductive layer BCL1 can be connected to the first source region SR1 of the connection transistor TR1 through the first source electrode pattern S1 (e.g., the 1-1 pattern S1). In this case, the first bottom conductive layer BCL1 can be synchronized with the first source region SR1 of the transistor TR1. The second bottom conductive layer BCL2 can be connected to the second source region SR2 of the connection transistor TR2 through the second source electrode pattern S2 (e.g., the 1-2 pattern S2). In this case, the second bottom conductive layer BCL2 can be synchronized with the second source region SR2 of the transistor TR2.

[0192] However, the disclosure is not limited thereto, and the bottom conductive layer BCL1 or BCL2 can be connected to and synchronized with the first gate electrode GE1 or the second gate electrode GE2 of the transistor TR1 or TR2. As another example, the bottom conductive layer BCL1 or BCL2 can be connected to another electrode to be independently applied with an electrostatic voltage or a pulse signal. As another example, the bottom conductive layer BCL1 or BCL2 can be provided to be isolated from another conductive pattern. The bottom conductive layer BCL1 or BCL2 according to an embodiment can be provided in various suitable forms and is not limited to any particular embodiment.

[0193] The transistor TR1 of the first pixel driver PDC1 and the transistor TR2 of the second pixel driver PDC2 can be disposed on the first insulating layer 10. The transistor TR1 of the first pixel driver PDC1 can include a first semiconductor pattern SP1 and a first gate electrode GE1. The transistor TR2 of the second pixel driver PDC2 can include a second semiconductor pattern SP2 and a second gate electrode GE2. The first semiconductor pattern SP1 and the second semiconductor pattern SP2 can be disposed on the first insulating layer 10. The first semiconductor pattern SP1 and the second semiconductor pattern SP2 can include an oxide semiconductor. For example, the oxide semiconductor can include a transparent conductive oxide (TCO) such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), or indium oxide (In2O3). However, the disclosure is not limited thereto, and the first semiconductor pattern SP1 and the second semiconductor pattern SP2 can include amorphous silicon, low-temperature polysilicon, or polysilicon.

[0194] Each of the first and second semiconductor patterns SP1 and SP2 can include a source region, a drain region, and a channel region divided according to a level of its electrical conductivity. For example, the first semiconductor pattern SP1 can include a first source region SR1, a first drain region DR_1, and a first channel region CR1. The first source region SR1 and the first drain region DR_1 can be spaced apart from each other with the first channel region CR1 interposed therebetween. The first channel region CR1 can overlap the first gate electrode GE1 in a plan view. The second semiconductor pattern SP2 can include a second source region SR2, a second drain region, and a second channel region CR2. The second source region SR2 and the second drain region can be spaced apart from each other with the second channel region CR2 interposed therebetween. The second channel region CR2 can overlap the second gate electrode GE2 in a plan view. Corresponding to Figure 5 the cross-sectional view of FIG. 7A, the line I-I' does not pass through the second drain region of the second semiconductor pattern SP2, and thus, the second drain region is not shown in Figure 5

[0195] When the semiconductor pattern SP1 or SP2 is an oxide semiconductor, each of the first or second source region SR1 or SR2 and the first or second drain region DR_1 or DR_2 can be a reduced region. Thus, the first or second source region SR1 or SR2 and the first or second drain region DR_1 or DR_2 can have a relatively high content ratio of a reduced metal. As another example, when the semiconductor pattern SP1 or SP2 is polysilicon, each of the first or second source region SR1 or SR2 and the first or second drain region DR_1 or DR_2 can be doped at a high concentration.

[0196] The first or second source region SR1 or SR2 and the first or second drain region DR_1 or DR_2 can have a relatively high electrical conductivity than that of the channel region CR1 or CR2. The first or second source region SR1 or SR2 can correspond to a source electrode of the transistor TR1 or TR2, and the first or second drain region DR_1 or DR_2 can correspond to a drain electrode of the transistor TR1 or TR2. As shown in Figure 5 separate source electrode patterns S1 or S2 and drain electrode patterns D1 or D2 can be further included to be connected to the first or second source region SR1 or SR2 and the first or second drain region DR_1 or DR_2, respectively. In more detail, the separate source electrode patterns S1 or S2 and drain electrode patterns D1 or D2 can be connected to a pixel driver (e.g., see the pixel driver PDC in Figure 2A Figure 2B the pixel driver PDC-1 in FIG. 7B, or the pixel driver PDC-2 in FIG. 7C).​​Figure 2C The respective one of the plurality of lines is integrally provided with the pixel driver PDC-2 in the pixel P1, and is not limited to any particular embodiment.

[0197] The second insulating layer 20 can overlap commonly with the plurality of pixels, and can cover the semiconductor patterns SP1 or SP2. The second insulating layer 20 can include an inorganic layer and / or an organic layer, and can have a single layer structure or a multi-layer structure. The second insulating layer 20 can include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. In the present embodiment, the second insulating layer 20 can be a single silicon oxide layer.

[0198] The gate electrodes GE1 and GE2 can be disposed on the second insulating layer 20. The first gate electrode GE1 can correspond to a gate of the transistor TR1 of the first pixel driver PDC1, and the second gate electrode GE2 can correspond to a gate of the transistor TR2 of the second pixel driver PDC2. Each of the gate electrodes GE1 and GE2 can be disposed above the semiconductor patterns SP1 and SP2. However, the present disclosure is not limited thereto, and the gate electrodes GE1 and GE2 can be disposed respectively under the semiconductor patterns SP1 and SP2, and is not limited to any particular embodiment.

[0199] Each of the gate electrodes GE1 and GE2 can include titanium (Ti), silver (Ag), molybdenum (Mo), aluminum (Al), aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), or a suitable alloy thereof, etc., but the present disclosure is not particularly limited thereto.

[0200] The third insulating layer 30 can be disposed on the gate electrodes GE1 and GE2. The third insulating layer 30 can include an inorganic layer and / or an organic layer, and have a single layer structure or a multi-layer structure. The fourth insulating layer 40 can include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide.

[0201] The first capacitor electrode CPE1 and the second capacitor electrode CPE2 from among the plurality of conductive patterns (e.g., the first source electrode pattern S1, the second source electrode pattern S2, the first drain electrode pattern D1, the second drain electrode pattern D2, the first capacitor electrode CPE1, the second capacitor electrode CPE2, and the third capacitor electrode CPE3) provide the first capacitor C1. The first capacitor electrode CPE1 and the second capacitor electrode CPE2 can be spaced apart from each other with the first insulating layer 10 and the second insulating layer 20 interposed therebetween.

[0202] In embodiments of the disclosure, the first capacitor electrode CPE1 and the first bottom conductive layer BCL1 can have a one-body shape. Further, the second capacitor electrode CPE2 can have a one-body shape with the first gate electrode GE1 connected to each other, and the capacitor electrode CPE can have a one-body shape with the second gate electrode GE2 connected to each other. However, the disclosure is not limited thereto. For example, the first capacitor electrode CPE1 and the first bottom conductive layer BCL1 can be disposed at the same layer (e.g., middle or upper) from each other and can be spaced apart from each other. The second capacitor electrode CPE2 and the first gate electrode GE1 can be disposed at the same layer (e.g., middle or upper) from each other and can be spaced apart from each other. The capacitor electrode CPE and the second gate electrode GE2 can be disposed at the same layer (e.g., middle or upper) from each other and can be spaced apart from each other.

[0203] The third capacitor electrode CPE3 can be disposed on the third insulating layer 30. The third capacitor electrode CPE3 can be spaced apart from the second capacitor electrode CPE2 with the third insulating layer 30 interposed therebetween. The third capacitor electrode CPE3 and the second capacitor electrode CPE2 can provide the second capacitor C2.

[0204] The fourth insulating layer 40 can be disposed on the third insulating layer 30 and / or the third capacitor electrode CPE3. The fourth insulating layer 40 can include an inorganic material and / or an organic material, and can have a single layer structure or a multi-layer structure. The fourth insulating layer 40 can include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide.

[0205] On the fourth insulating layer 40, a first source electrode pattern S1 and a first drain electrode pattern D1 connected to the first semiconductor pattern SP1, and a second source electrode pattern S2 and a second drain electrode pattern D2 connected to the second semiconductor pattern SP2 can be disposed.

[0206] The first source electrode pattern S1 can be connected to the first source region SR1 of the connection transistor TR1 through the first contact hole CNT1, and the first source electrode pattern S1 and the first source region SR1 of the first semiconductor pattern SP1 can function as a source of the connection transistor TR1. The first drain electrode pattern D1 can be connected to the first drain region DR_1 of the connection transistor TR1 through the second contact hole CNT2, and the first drain electrode pattern D1 and the first drain region DR_1 of the first semiconductor pattern SP1 can function as a drain of the connection transistor TR1.

[0207] The second source electrode pattern S2 can be connected to the second bottom conductive layer BCL2 of the second pixel driver PDC2 and the second source region SR2 of the transistor TR2 through a contact hole. The second source electrode pattern S2 and the second source region SR2 of the second semiconductor pattern SP2 can function as a source of the transistor TR2. The second drain electrode pattern D2 can be connected to the second gate electrode GE2 through a contact hole, and the second gate electrode GE2 can be connected to the second drain region of the second semiconductor pattern SP2. The second drain electrode pattern D2 can be connected to the second drain region of the transistor TR2, and the second drain electrode pattern D2 and the second drain region can function as a drain of the transistor TR2.

[0208] The fifth insulating layer 50 can be disposed on the first source electrode pattern S1, the first drain electrode pattern D1, the second source electrode pattern S2, and the second drain electrode pattern D2.

[0209] The intermediate connection electrode CN can be disposed on the fifth insulating layer 50. The intermediate connection electrode CN can electrically connect the first pixel driver PDC1 and the connection electrode CNE to each other. The intermediate connection electrode CN can electrically connect the light emitting element LD and the connection transistor TR1 of the first pixel driver PDC1 to each other. The intermediate connection electrode CN can be a connection node that connects the first pixel driver PDC1 and the light emitting element LD to each other. The intermediate connection electrode CN can correspond to the fourth node N4 (for example, see Figure 2A ), the second node N2 (for example, see Figure 2B ), or the fourth node N4 (for example, see Figure 2C ).

[0210] The sixth insulating layer 60 can be disposed on the intermediate connection electrode CN. The sixth insulating layer 60 can be disposed on the fifth insulating layer 50 to cover at least a portion of the intermediate connection electrode CN. Each of the fifth insulating layer 50 and the sixth insulating layer 60 can be an organic layer. For example, each of the fifth insulating layer 50 and the sixth insulating layer 60 can include benzocyclobutene (BCB), hexamethyldisiloxane (HMDSO), polymethyl methacrylate (PMMA), or a general-purpose polymer such as polystyrene (PS), a polymer derivative having a phenolic group, an acrylic polymer, an imide-based polymer such as polyimide, an arylether-based polymer, an amide-based polymer, a fluorine-containing polymer, a p-xylene-based polymer, a vinyl alcohol-based polymer, or a suitable blend thereof.

[0211] A via OP-60 exposing at least a portion of the intermediate connection electrode CN can be provided in the sixth insulating layer 60. The intermediate connection electrode CN can be connected to the connection electrode CNE through the portion exposed from the sixth insulating layer 60, and can be electrically connected to the light emitting element LD. The intermediate connection electrode CN can electrically connect the connection transistor TR1 and the light emitting element LD to each other together with the connection electrode CNE. In the display panel DP according to the embodiment of the disclosure, the sixth insulating layer 60 can be omitted or provided as a plurality as needed or desired, and thus, is not limited to any specific embodiment. When the sixth insulating layer 60 is omitted, the intermediate connection electrode CN can also be omitted.

[0212] The intermediate connection electrode CN can include a first layer L1, a second layer L2, and a third layer L3, which are sequentially stacked in the third direction DR3. The second layer L2 can include a material different from that of the first layer L1. Also, the second layer L2 can include a material different from that of the third layer L3. The second layer L2 can have a thickness relatively thicker than that of the first layer L1. Also, the second layer L2 can have a thickness relatively thicker than that of the third layer L3. The second layer L2 can include a suitable material having high electrical conductivity. In an embodiment, the second layer L2 can include aluminum (Al).

[0213] The light emitting element layer LDL can be disposed on the driving element layer DDL. The light emitting element layer LDL can include a pixel definition layer PDL, a light emitting element LD, and a spacer SPR.

[0214] The pixel definition layer PDL can be an organic layer. For example, the pixel definition layer PDL can include benzocyclobutene (BCB), hexamethyldisiloxane (HMDSO), PMMA, or a general-purpose polymer such as PS, a polymer derivative having a phenolic group, an acrylic polymer, an imide-based polymer such as polyimide, an arylether-based polymer, an amide-based polymer, a fluorine-containing polymer, a p-xylene-based polymer, a vinyl alcohol-based polymer, or a suitable blend thereof.

[0215] In an embodiment, the pixel definition layer PDL can have light absorption properties, and for example, can have a black color. In other words, the pixel definition layer PDL can include a black colorant. The black colorant can include a black dye or a black pigment. The black colorant can include carbon black, a metal such as chromium, or an oxide of the metal. The pixel definition layer PDL can correspond to a light blocking pattern having light blocking properties.

[0216] An opening (hereinafter, an emission opening) OP-PDL of at least a portion of the first electrode EL1 to be described below in more detail can be defined in the pixel definition layer PDL. The emission opening OP-PDL can be provided as a plurality to be respectively disposed in correspondence with the plurality of light emitting elements. The emission opening OP-PDL can be an area overlapping all components of the light emitting element LD and at which light emitted from the light emitting element LD is emitted or substantially emitted. Accordingly, a shape of the first light emitting part EP1 (for example, see Figure 4A ) can correspond to or substantially correspond to a shape of the emission opening OP-PDL in a plan view.

[0217] The connection electrode CNE can be disposed on the pixel definition layer PDL. The connection electrode CNE can electrically connect the pixel driver PDC (for example, see Figure 2A ) and the light emitting element LD to each other. The pixel driver PDC can be electrically connected to the light emitting element LD via the intermediate connection electrode CN and the connection electrode CNE. The connection electrode CNE can correspond to the first connection electrode CNE1 in Figure 4A . The second connection electrode CNE2 (for example, see Figure 4A ) and the third connection electrode CNE3 (for example, see Figure 4A ) can also have a structure similar or identical to that of the connection electrode CNE.

[0218] The connection electrode CNE can include a first edge EG1c adjacent to (for example, facing) the emission opening OP-PDL and a second edge EG2c surrounding the first edge EG1c (for example, around a periphery of the first edge EG1c). The second electrode EL2 of the light emitting element LD can contact the connection electrode CNE in an area adjacent to the second edge EG2c.

[0219] The connection electrode CNE can include a transparent conductive oxide (TCO) such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), or indium oxide (In2O3), etc. However, the material of the connection electrode CNE is not limited thereto.

[0220] A via OP-P can be defined in the pixel definition layer PDL spaced apart from the emission opening OP-PDL. The emission opening OP-PDL can be provided as a plurality, each of the plurality of emission openings OP-PDL can correspond to one of the plurality of light emitting elements LD. A size of the via OP-P defined in the pixel definition layer PDL can be greater than a size of the via OP-60 defined in the sixth insulating layer 60. The connection electrode CNE can be disposed in the via OP-P and the via OP-60 and can be connected to the intermediate connection electrode CN.

[0221] The light emitting element LD can include a first electrode EL1, an intermediate layer IML, and a second electrode EL2.

[0222] The first electrode EL1 can be a semi-transmissive electrode, a transmissive electrode, or a reflective electrode. According to an embodiment of the disclosure, the first electrode EL1 can include a reflective layer including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a suitable compound thereof, etc. (e.g., consisting of silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a suitable compound thereof, etc.) and a transparent electrode layer or a semi-transparent electrode layer provided on the reflective layer. The transparent electrode layer or the semi-transparent electrode layer can include at least one selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium oxide (In2O3), and aluminum-doped zinc oxide (AZO). For example, the first electrode EL1 can include a layer structure of ITO / Ag / ITO.

[0223] In the present embodiment, the first electrode EL1 can be an anode of the light emitting element LD. In other words, the first electrode EL1 can be connected with the first power line VDL (e.g., see Figure 2A ) and can be applied with the first power source voltage VDD. The first electrode EL1 can be connected to the first power line VDL in the display area DA (e.g., see Figure 3A or Figure 3B ) or connected to the first power line VDL in the peripheral area NDA. In the latter case, the first power line VDL can be disposed in the peripheral area NDA and the first electrode EL1 can have a shape extending to the peripheral area NDA.

[0224] In the cross-sectional view in Figure 5 , the first electrode EL1 is shown as overlapping with the emission opening OP-PDL and not overlapping with the partition SPR, but as shown in Figure 4D , the first electrode EL1 of the light emitting element can have an integral shape and can have a mesh shape or a lattice shape in which an opening is defined in a partial area. In other words, when the first power source voltage VDD is applied to the first electrodes EL1 of the plurality of light emitting elements, the shape of each of the plurality of first electrodes EL1 can be provided in various suitable ways and is not limited to any particular embodiment.

[0225] An intermediate layer IML can be disposed between the first electrode EL1 and the second electrode EL2. The intermediate layer IML can include an emission layer EML and a functional layer FNL. The light emitting element LD can include the intermediate layer IML having various suitable structures, and is not limited to any particular embodiment. For example, the functional layer FNL can be provided as a plurality, and can include two or more layers spaced apart from each other with the emission layer EML interposed therebetween.

[0226] The emission layer EML can include an organic emission material. Further, the emission layer EML can include an inorganic emission material, or can be provided with a mixed layer of an organic emission material and an inorganic emission material. In the present embodiment, the emission layer EML included in the adjacent light emitting portion EP (see, for example, Figure 3A ) can include an emission material for emitting light of a color different from each other. For example, the emission layer EML included in each of the plurality of light emitting portions EP can provide light of any one color among blue, red, and green. However, the present disclosure is not limited thereto, and the emission layer EML in all of the plurality of light emitting portions EP can have an emission material for emitting light of the same color as each other. In this case, the emission layer EML can provide blue light or white light.

[0227] The functional layer FNL can be disposed between the first electrode EL1 and the second electrode EL2. In more detail, the functional layer FNL can include a first intermediate functional layer FNLa (see, for example, Figure 9 ) disposed between the first electrode EL1 and the emission layer EML, and a second intermediate functional layer FNLb (see, for example, Figure 9 ) disposed between the second electrode EL2 and the emission layer EML. In the embodiment of the present disclosure, one of the first intermediate functional layer FNLa and the second intermediate functional layer FNLb can be omitted as needed or desired. In the present embodiment, the emission layer EML is shown as being embedded in the functional layer FNL. For example, it can be understood that the emission layer EML is disposed between the first intermediate functional layer FNLa and the second intermediate functional layer FNLb.

[0228] The functional layer FNL can control charge transport between the first electrode EL1 and the second electrode EL2. For example, the first intermediate functional layer FNLa can include one or more hole injection / transport materials and / or one or more electron injection / transport materials. The second intermediate functional layer FNLb can include at least one among an electron blocking layer, a hole transport layer, a hole injection layer, a hole blocking layer, an electron transport layer, an electron injection layer, and a charge generation layer.

[0229] The second electrode EL2 can be disposed on the intermediate layer IML. As described above, the second electrode EL2 can be connected to the connection electrode CNE to be electrically connected to the first pixel driver PDC1. The second electrode EL2 can be electrically connected to the connection transistor TR1 through the connection electrode CNE.

[0230] The spacer SPR can be disposed on the pixel definition layer PDL. Further, the spacer SPR can be disposed in a gap GP (see, for example, Figure 9 ) between the connection electrode CNE and an adjacent connection electrode CNEn adjacent to the connection electrode CNE on the pixel definition layer PDL (see, for example, Figure 9 ).

[0231] In an embodiment, the second electrode EL2 and the functional layer FNL can be commonly deposited in a plurality of pixels through an opening mask. Here, the second electrode EL2 and the functional layer FNL can be divided by the spacer SPR. As described above, the spacer SPR can have a closed linear shape for each of the plurality of light emitting portions, and thus, the second electrode EL2 and the functional layer FNL can have a separate shape for each of the plurality of light emitting portions. In other words, the second electrode EL2 and the intermediate layer IML can be electrically isolated from each adjacent pixel. The spacer SPR will be described in more detail hereinafter. Figure 9

[0232] The encapsulation layer ECL can be disposed on the light emitting element layer LDL. The encapsulation layer ECL can cover the light emitting element layer LDL and the spacer SPR. The encapsulation layer ECL can include a first inorganic layer IL1, an organic layer OL, and a second inorganic layer IL2 which are sequentially stacked. However, the present disclosure is not limited thereto, and the encapsulation layer ECL can further include a plurality of inorganic layers and organic layers. The encapsulation layer ECL can be a glass substrate.

[0233] The first inorganic layer IL1 and the second inorganic layer IL2 can protect the light emitting element LD from moisture and oxygen from the outside of the display panel DP, and the organic layer OL can protect the light emitting element LD from foreign matter such as particles that can be left in a process of providing the first inorganic layer IL1. The first inorganic layer IL1 and the second inorganic layer IL2 can include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer, etc. The organic layer OL can include an acrylic organic layer, but the present disclosure is not limited to the above-described materials.

[0234] ​The sensing layer ISL can sense an external input. In an embodiment, the sensing layer ISL can be provided on the encapsulation layer ECL through a continuous process. In this case, the sensing layer ISL can be understood as being disposed directly on the encapsulation layer ECL. As used herein, "directly disposed" can mean that no other component is disposed between the sensing layer ISL and the encapsulation layer ECL. In other words, no separate adhesive member can be disposed between the input sensing layer ISL and the encapsulation layer ECL. However, the present disclosure is not limited thereto. In the display panel DP according to an embodiment of the present disclosure, the sensing layer ISL can be separately provided and then can be combined with the display panel DP through an adhesive member, but the present disclosure is not limited to any particular embodiment.

[0235] The sensing layer ISL can include a plurality of conductive layers and a plurality of insulating layers. The plurality of conductive layers can include a first sensing conductive layer MTL1 and a second sensing conductive layer MTL2. The plurality of insulating layers can include a first sensing insulating layer 71, a second sensing insulating layer 72, and a third sensing insulating layer 73. However, the present disclosure is not limited thereto, and the number of conductive layers and insulating layers is not limited to any particular embodiment.

[0236] Each of the first sensing insulating layer 71, the second sensing insulating layer 72, and the third sensing insulating layer 73 can have a single layer structure or a multi-layer structure stacked in the third direction DR3. Each of the first sensing insulating layer 71, the second sensing insulating layer 72, and the third sensing insulating layer 73 can include an inorganic film. The inorganic film can include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. Each of the first sensing insulating layer 71, the second sensing insulating layer 72, and the third sensing insulating layer 73 can include an organic film. The organic film can include at least one of an acrylic resin, a methacrylic resin, a polyisoprene resin, a vinyl-based resin, an epoxy-based resin, a urethane-based resin, a cellulose-based resin, a siloxane-based resin, a polyimide-based resin, a polyamide-based resin, and a perylene-based resin.

[0237] The first sensing conductive layer MTL1 can be disposed between the first sensing insulating layer 71 and the second sensing insulating layer 72, and the second sensing conductive layer MTL2 can be disposed between the second sensing insulating layer 72 and the third sensing insulating layer 73. A portion of the second sensing conductive layer MTL2 can be connected to the first sensing conductive layer MTL1 through a contact hole CNT provided in the second sensing insulating layer 72. The first sensing conductive layer MTL1 and the second sensing conductive layer MTL2 can each have a single layer structure or a multi-layer structure stacked in the third direction DR3.

[0238] The sensing conductive layer of the single-layer structure can include a metal layer or a transparent conductive layer. The metal layer can include molybdenum, silver, titanium, copper, aluminum, or a suitable alloy thereof. The transparent conductive layer can include a transparent conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium zinc tin oxide (IZTO). As another example, the transparent conductive layer can include a conductive polymer such as poly(3,4-ethylenedioxythiophene) (PEDOT), a metal nanowire, or graphene, etc.

[0239] The sensing conductive layer of the multi-layer structure can include a plurality of metal layers. For example, the metal layers can have a three-layer structure of titanium / aluminum / titanium. As another example, the sensing conductive layer of the multi-layer structure can include at least one metal layer and at least one transparent conductive layer.

[0240] The first sensing conductive layer MTL1 and the second sensing conductive layer MTL2 can constitute a sensor for sensing an external input in the sensing layer ISL. The sensor can be driven in an electrostatic capacitance mode, and in more detail, can be driven in any one of a mutual capacitance mode and a self-capacitance mode. However, the present disclosure is not limited thereto. The sensor can be driven in a resistive film mode, an ultrasonic mode, or an infrared mode in addition to the electrostatic capacitance mode, and is not limited to any particular embodiment.

[0241] Each of the first sensing conductive layer MTL1 and the second sensing conductive layer MTL2 can further include a transparent conductive oxide, or can have a shape of a metal mesh including (e.g., consisting of) a non-transparent conductive material. Each of the first sensing conductive layer MTL1 and the second sensing conductive layer MTL2 can include various suitable materials and various suitable shapes as long as the visibility of an image displayed on the display panel DP is not reduced, and is not limited to any particular embodiment.

[0242] Figure 6 is a plan view of a partial area of a display panel according to an embodiment of the present disclosure. Figure 6 is a schematic diagram illustrating some components (e.g., connection electrodes CNE1, CNE2, and CNE3 and light emitting parts EP1, EP2, and EP3) and first, second, and third conductive patterns CP1, CP2, and CP3.

[0243] Referring to Figure 5 and Figure 6 , the display panel DP can include first, second, and third pixel drivers PDC1, PDC2, and PDC3 (e.g., see Figure 4B). The first pixel driver PDC1 can include a first conductive pattern CP1, the second pixel driver PDC2 can include a second conductive pattern CP2, and the third pixel driver PDC3 can include a third conductive pattern CP3.

[0244] The first conductive pattern CP1 can include a 1-1 pattern S1 and a 2-1 pattern D1 electrically connected to the first connection electrode CNE1. The second conductive pattern CP2 can include a 1-2 pattern S2 and a 2-2 pattern D2 electrically connected to the second connection electrode CNE2. The third conductive pattern CP3 can include a 1-3 pattern S3 and a 2-3 pattern D3 electrically connected to the third connection electrode CNE3. The 1-1 pattern S1, the 1-2 pattern S2, and the 1-3 pattern S3 can correspond to source electrode patterns of transistors, and the 2-1 pattern D1, the 2-2 pattern D2, and the 2-3 pattern D3 can correspond to drain electrode patterns of transistors.

[0245] The conductive patterns CP1 and CP2 can overlap with adjacent connection electrodes CNE1 and CNE2 to which they are not electrically connected. For example, the 1-1 pattern S1 and the 2-1 pattern D1 of the first conductive pattern CP1 are not electrically connected to the second connection electrode CNE2, but can overlap with the second connection electrode CNE2 in a plan view. The 1-2 pattern S2 and the 2-2 pattern D2 of the second conductive pattern CP2 are not electrically connected to the first connection electrode CNE1, but can overlap with the first connection electrode CNE1 in a plan view. Since the conductive patterns not electrically connected to the connection electrodes overlap with the connection electrodes in a plan view, the electric field can vary, and coupling noise can be generated or increased in response to the variation of the electric field.

[0246] Referring again to Figure 5 , the display panel DP can further include a first metal layer ML1. The first metal layer ML1 can include the same material as that of the first electrode EL1, and be connected to the first electrode EL1. The first metal layer ML1 can be provided in the same process as that of the first electrode EL1. The first metal layer ML1 can be disposed between the connection electrode CNE and the 1-2 pattern S2 and the 2-2 pattern D2 in a cross-sectional view. The 1-2 pattern S2 and the 2-2 pattern D2 of the second conductive pattern CP2 can overlap with the first metal layer ML1 in a plan view.

[0247] Figure 5 The connection electrode CNE in Figure 5 and Figure 6The first metal layer ML1 can include the same material as that of the first electrode EL1 of the first light emitting part EP1 and be connected to the first electrode EL1 of the first light emitting part EP1. The first metal layer ML1 can be disposed between the second conductive pattern CP2 and the first connection electrode CNE1 in the cross-sectional view and can overlap the 1-2 pattern S2 and the 2-2 pattern D2 of the second conductive pattern CP2 in the plan view.

[0248] However, the present disclosure is not limited thereto, and various modifications can be made to the position of the first metal layer ML1 as needed or desired. For example, the first metal layer ML1 can be disposed between the first conductive pattern CP1 and the second connection electrode CNE2 in the cross-sectional view and can overlap the 1-1 pattern S1 and the 2-1 pattern D1 of the first conductive pattern CP1 in the plan view.

[0249] According to an embodiment of the present disclosure, the first electrode EL1 of the display panel DP can be extended to be disposed between the connection electrode CNE and the conductive patterns CP1, CP2, and CP3. The first electrode EL1 can be provided with a first power voltage VDD (see, for example, Figure 2A ) Since the conductive patterns CP1, CP2, and CP3 and the connection electrode CNE are shielded using the first electrode EL1 provided with a constant voltage, coupling noise generated between the conductive patterns CP1, CP2, and CP3 and the connection electrode CNE can be reduced or removed.

[0250] Figure 7 is a cross-sectional view of a display panel DP-1 according to an embodiment of the present disclosure. Figure 7 shows a cross-section of a portion corresponding to line I-I' in Figure 4A In Figure 7 , like reference numerals are used to refer to like elements (e.g., the same or substantially the same elements) as those described above with reference to Figure 5 , and thus, redundant descriptions thereof can not be repeated.

[0251] Referring to Figure 7 , the display panel DP-1 can include a second metal layer ML2. The second metal layer ML2 can include the same material as that of the intermediate connection electrode CN and can be disposed at the same layer (e.g., middle or upper) as that of the intermediate connection electrode CN. The second metal layer ML2 can be provided in the same process as that of the intermediate connection electrode CN. The second metal layer ML2 can be disposed between the connection electrode CNE and the 1-2 pattern S2 and the 2-2 pattern D2. The 1-2 pattern S2 and the 2-2 pattern D2 can overlap the second metal layer ML2 in the plan view.

[0252] Figure 7The connecting electrode CNE in the diagram may not be electrically connected to patterns S2 (1-2) and D2 (2-2). For example, refer to... Figure 6 and Figure 7 The second metal layer ML2 may include the same material as the intermediate connecting electrode CN that electrically connects the first pixel driving portion PDC1 and the first connecting electrode CNE1 to each other, and may be disposed in the same layer as the intermediate connecting electrode CN (e.g., in the middle or on top). The second metal layer ML2 may be disposed between the second conductive pattern CP2 and the first connecting electrode CNE1 in a cross-sectional view, and may overlap with the first-second pattern S2 and the second-second pattern D2 of the second conductive pattern CP2 in a planar view.

[0253] However, this disclosure is not limited thereto, and the position of the second metal layer ML2 can be modified in various ways as needed or desired. For example, the second metal layer ML2 can be disposed between the first conductive pattern CP1 and the second connecting electrode CNE2 in a cross-sectional view, and can overlap with the first-1 pattern S1 and the second-1 pattern D1 in a planar view.

[0254] According to some embodiments of this disclosure, the intermediate connection electrode CN of the display panel DP-1 can be extended to reduce or eliminate coupling noise provided between the connection electrode CNE and the conductive patterns CP1, CP2 and CP3.

[0255] Figure 8 This is a cross-sectional view of the display panel DP-2 according to an embodiment of the present disclosure. Figure 8 It shows the corresponding Figure 4A The cross-section of the section of line I-I' in the diagram. Figure 8 In the figures, the same reference numerals are used to indicate references to the above. Figure 5 The elements described are the same elements (e.g., identical or substantially the same elements), and therefore, their redundant descriptions can be avoided.

[0256] Reference Figure 8 The display panel DP-2 may include both a first metal layer ML1 and a second metal layer ML2. The first metal layer ML1 may include the same material as the first electrode EL1 and is connected to the first electrode EL1. The second metal layer ML2 may include the same material as the intermediate connecting electrode CN and may be disposed in the same layer as the intermediate connecting electrode CN (e.g., in the middle or on top). The first metal layer ML1 may be provided in the same process as the first electrode EL1, and the second metal layer ML2 may be provided in the same process as the intermediate connecting electrode CN.

[0257] The first metal layer ML1 and the second metal layer ML2 can be disposed between the connecting electrode CNE and the first-second pattern S2 and the second-second pattern D2. The first-second pattern S2 and the second-second pattern D2 can overlap with the first metal layer ML1 and the second metal layer ML2 in a planar view.

[0258] Figure 8 The connecting electrode CNE in the diagram may not be electrically connected to patterns S2 (1-2) and D2 (2-2). For example, refer to... Figure 6 and Figure 8 The first metal layer ML1 may include the same material as the first electrode EL1 of the first light-emitting part EP1, and is connected to the first electrode EL1 of the first light-emitting part EP1. The second metal layer ML2 may include the same material as the intermediate connecting electrode CN that electrically connects the first pixel driver PDC1 and the first connecting electrode CNE1 to each other, and may be disposed in the same layer as the intermediate connecting electrode CN (e.g., in the middle or on top). The first metal layer ML1 and the second metal layer ML2 may be disposed between the second conductive pattern CP2 and the first connecting electrode CNE1 in a cross-sectional view, and may overlap with the first-second pattern S2 and the second-second pattern D2 in a planar view.

[0259] However, this disclosure is not limited thereto, and the positions of the first metal layer ML1 and the second metal layer ML2 can be modified as needed or desired. For example, the first metal layer ML1 and the second metal layer ML2 can be disposed between the first conductive pattern CP1 and the second connecting electrode CNE2 in a cross-sectional view, and can overlap with the first-1 pattern S1 and the second-1 pattern D1 in a planar view.

[0260] According to embodiments of the present disclosure, the intermediate connecting electrode CN and / or the first electrode EL1 of the display panel DP-2 may be extended to reduce or eliminate coupling noise provided between the conductive patterns CP1, CP2 and CP3 and the connecting electrode CNE.

[0261] Figure 9 This is an enlarged cross-sectional view of a portion of the display panel DP according to an embodiment of the present disclosure. Figure 9 yes Figure 5 An enlarged plan view of region AA' in the diagram.

[0262] Reference Figure 5 and Figure 9In an embodiment, the spacer SPR can have a reverse tapered shape. For example, the farther the spacer SPR is from the top surface of the pixel-defining layer PDL, the wider the width of the spacer SPR. The side surface TP of the spacer SPR can have a shape in which the tapering angle from the top surface of the pixel-defining layer PDL is an obtuse angle. However, the present disclosure is not limited thereto, and when the spacer SPR is electrically disconnected for each of the plurality of pixels, the spacer SPR can have a double structure in which various modifications can be made to the tapering angle (e.g., such that the tapering angle varies). Further, the spacer SPR can have the same or substantially the same structure as that of the tip portion, and is not limited to any particular embodiment.

[0263] The spacer SPR can include a suitable material having insulating properties, such as, for example, an organic insulating material. The spacer SPR can also include an inorganic insulating material or a multi-layer structure of an organic insulating material and an inorganic insulating material, and in some embodiments, can also include a conductive material. When the second electrode EL2 is electrically disconnected for each of the plurality of pixels, the spacer SPR is not particularly limited to any particular kind of material.

[0264] On the spacer SPR, a dummy layer UP can be provided. The dummy layer UP can include a first dummy layer UP1 disposed on the spacer SPR and a second dummy layer UP2 disposed on the first dummy layer UP1. The first dummy layer UP1 can be provided in the same process as that of the intermediate layer IML and include the same material as that of the intermediate layer IML. The first dummy layer UP1 can include a 1-1 dummy layer UP1a and a 1-2 dummy layer UP1b. The 1-1 dummy layer UP1a can be provided in the same process as that of the first intermediate functional layer FNLa and can include the same material as that of the first intermediate functional layer FNLa. The 1-2 dummy layer UP1b can be provided in the same process as that of the second intermediate functional layer FNLb and can include the same material as that of the second intermediate functional layer FNLb. The second dummy layer UP2 can be provided in the same process as that of the second electrode EL2 and can include the same material as that of the second electrode EL2. In other words, the first dummy layer UP1 and the second dummy layer UP2 can be concurrently provided in the manufacturing process of the functional layer FNL and the second electrode EL2. As Figure 9 As shown in FIG. 1A, the dummy layer UP can also be provided on a portion of the side surface TP and on the top surface of the spacer SPR. In another embodiment, the display panel DP can not include the dummy layer UP. The dummy layer UP can not contact the connection electrode CNE and the second electrode EL2. The second dummy layer UP2 included in the dummy layer UP can not contact the connection electrode CNE and the second electrode EL2.

[0265] A portion where the second electrode EL2 contacts the connection electrode CNE can be defined as a contact region. The contact region can be provided adjacent to the partition SPR. In the contact region, a top surface CNE-us of the connection electrode CNE contacts a bottom surface EL2-bs of the second electrode EL2. Since the partition SPR has a reverse tapered shape and is provided adjacent to the contact region, at least a portion of the contact region where the second electrode EL2 contacts the connection electrode CNE can be disposed under a side surface TP of the partition SPR.

[0266] In an embodiment, at least a portion of the connection electrode CNE can be disposed under the partition SPR. The partition SPR can be disposed in a gap GP between the connection electrode CNE and an adjacent connection electrode CNEn adjacent to the connection electrode CNE, and a second edge EG2c of the second electrode EL2 can be covered by the partition SPR.

[0267] According to an embodiment of the disclosure, the connection electrode CNE can have a shape that surrounds a portion of the emission region where the light emitting element LD is disposed (e.g., around a periphery of the portion of the emission region where the light emitting element LD is disposed). Accordingly, a connection position of the connection electrode CNE and the light emitting element LD and a degree of freedom at a connection position of the connection electrode CNE and the pixel driver PDC (e.g., see Figure 2A ) can be improved. In addition, a top surface CNE-us of the connection electrode CNE can contact a bottom surface EL2-bs of the second electrode EL2 of the light emitting element LD through a contact region defined adjacent to the partition SPR. Accordingly, since a bottom surface of the connection electrode CNE contacts a top surface of the intermediate connection electrode CN, a contact reliability of the connection electrode CNE and the second electrode EL2 can be improved. In the display panel DP according to the embodiment, due to the above-described structure, a size of the via OP-P and a size of the OP-60 for connecting the connection electrode CNE and the intermediate connection electrode CN can be reduced or minimized, and thus, an area or a resolution of a light emitting portion of the display panel DP can be improved (e.g., can be easily improved).

[0268] Figure 10 is a cross-sectional view of a display panel DP-3 according to an embodiment of the disclosure. Figure 10 is a cross-sectional view illustrating a portion corresponding to a line II-II' in Figure 4B . In Figure 10 , like reference numerals are used to refer to like elements (e.g., the same or substantially the same elements) as those described above with reference to Figure 5 , and thus, redundant descriptions thereof can not be repeated.

[0269] Referring to Figure 10The display panel DP-3 can further include a connection line CN-ad disposed between the sixth insulating layer 60 and the pixel definition layer PDL. The connection line CN-ad can be connected to the intermediate connection electrode CN through a via OP-60 exposing at least a portion of the intermediate connection electrode CN.

[0270] In an embodiment of the disclosure, the connection line CN-ad can be provided at the same layer (e.g., middle or upper) as that of the first electrode EL1. For example, the connection line CN-ad can have the same material as that of the first electrode EL1 and the same layer structure as that of the first electrode EL1. Also, the connection line CN-ad can be provided in the same process as that of the first electrode EL1. However, the disclosure is not limited thereto. For example, the connection line CN-ad can have a different material from that of the first electrode EL1 and can be provided in a different process from that of the first electrode EL1.

[0271] The via OP-Pa can be defined in the pixel definition layer PDL. The via OP-Pa and the via OP-60 can not overlap each other, but the disclosure is not limited thereto. For example, in some embodiments, the via OP-Pa and the via OP-60 can overlap each other. The connection electrode CNEa can be disposed in the via OP-Pa. The connection electrode CNEa can be connected to the portion of the connection line CN-ad exposed by the via OP-Pa.

[0272] According to some embodiments described above, the intermediate connection electrode and / or the first electrode can be extended to reduce or remove coupling noise generated between the conductive pattern and the connection electrode.

[0273] The foregoing is a summary of some embodiments of the disclosure and should not be interpreted as limiting thereof. Although some embodiments have been described, those skilled in the art will readily appreciate that various modifications are possible in the embodiments without materially departing from the spirit and scope of the disclosure. It will be understood that the description of features or aspects within each embodiment should generally be considered to extend to other similar features or aspects in other embodiments, unless otherwise described. Thus, unless expressly stated to the contrary, as will be apparent from the description of a particular embodiment, features, characteristics or aspects described in connection with a particular embodiment can be used independently, or in connection with other embodiments, and accordingly the present disclosure is not limited to only one possible construction. Accordingly, it is to be understood that the above description is intended to be illustrative and not restrictive. Many embodiments as well as many changes, modifications, and improvements will occur to those skilled in the art upon the reading of the foregoing description, and such modifications and improvements are intended to be within the scope of the disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made in the present disclosure without departing from the spirit or scope of the disclosure. Thus, it is intended that the present disclosure cover the modifications and variations of this disclosure provided such modification and variations come within the scope of the appended claims and their equivalents.

Claims

1. A display panel, characterized by, The display panel includes: a drive element layer including: a first pixel driver including a first conductive pattern; and a second pixel driver including a second conductive pattern; a light emitting element over the drive element layer and including a first electrode, an intermediate layer over the first electrode, and a second electrode over the intermediate layer; a connection electrode over the drive element layer and electrically connected with the first pixel driver and the second electrode; and a metal layer between the second conductive pattern and the connection electrode in a cross-sectional view.

2. The display panel of claim 1, wherein, The first conductive pattern includes: a 1-1 pattern; and a 2-1 pattern electrically connected with the connection electrode.

3. The display panel of claim 2, wherein, The second conductive pattern includes a 1-2 pattern and a 2-2 pattern.

4. The display panel of claim 3, wherein, The 1-2 pattern and the 2-2 pattern overlap with the metal layer and / or the connection electrode in a plan view.

5. The display panel of claim 3, wherein, The 1-1 pattern and the 1-2 pattern include a source electrode pattern, and / or the 2-1 pattern and the 2-2 pattern include a drain electrode pattern.

6. The display panel of claim 1, wherein, The display panel further includes: an intermediate connection electrode electrically connecting the first pixel driver and the connection electrode with each other, wherein the metal layer is positioned at a same layer as a layer of the intermediate connection electrode.

7. The display panel of claim 1, wherein, The metal layer is connected to the first electrode.

8. The display panel of claim 1, wherein, The display panel further includes: a pixel defining layer over the drive element layer and having an emission opening through the pixel defining layer, the emission opening exposing at least a portion of the first electrode, wherein the connection electrode has a ring shape around the emission opening.

9. The display panel of claim 1, wherein, A bottom surface of the second electrode contacts a top surface of the connection electrode.

10. The display panel of claim 1, wherein, The display panel further includes: a partition over the connection electrode, wherein the second electrode and the connection electrode are connected with each other at an area adjacent to the partition, and wherein the connection electrode includes: a first edge; and a second edge around the first edge and overlapping with the partition.

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