Sub-pixel and display device

Abstract

A sub-pixel that can increase a capacitance of a capacitor and a display device including the sub-pixel are provided. The sub-pixel may include a first capacitor including a first electrode connected to a first power supply line and a second electrode connected to a second node. The second electrode may be directly connected to a gate electrode of the first transistor, a semiconductor layer of the third transistor, and a semiconductor layer of the fourth transistor.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0132771, filed on October 5, 2023, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0003] The disclosure relates generally to a sub-pixel and a display device including the same. BACKGROUND

[0004] As information technology develops, the importance of display devices, which are a medium for connecting users and information, increases. Accordingly, display devices such as liquid crystal display devices, organic light emitting display devices, and inorganic light emitting display devices are increasingly used.

[0005] As display devices are miniaturized, the size of a pixel (or a sub-pixel) for displaying an image in the display device also becomes small. Accordingly, the size of each of circuit elements constituting the pixel also becomes small.

[0006] Among these circuit elements, the capacitance of a capacitor is proportional to the size of an electrode. As the size of the circuit element becomes small, the size of the electrode constituting the capacitor also becomes small, and thus, the capacitance of the capacitor can decrease. Accordingly, there is a need for a structure for increasing the capacitance of the capacitor in a limited area. SUMMARY

[0007] Embodiments provide a sub-pixel having a capacitor with large capacitance and a display device including the same.

[0008] According to an aspect of the disclosure, there is provided a sub-pixel including: a light emitting element; a first transistor connected between a first power line and a first node, the first transistor including a gate electrode connected to a second node; a second transistor connected to a data line, the second transistor including a gate electrode connected to a first sub-gate line, the second transistor receiving a data signal supplied from the data line in response to a first scan signal supplied from the first sub-gate line; a third transistor including a gate electrode connected to a third sub-gate line, the third transistor switching an electrical connection between the first node and the second node in response to a third scan signal supplied from the third sub-gate line; a fourth transistor including a gate electrode connected to a second sub-gate line, the fourth transistor switching an electrical connection between the second node and a third power line in response to a second scan signal supplied from the second sub-gate line; a fifth transistor including a gate electrode connected to an emission control line, the fifth transistor switching an electrical connection between the first node and the light emitting element in response to an emission control signal supplied from the emission control line; and a first capacitor including a first electrode connected to the first power line and a second electrode connected to the second node, wherein the second electrode is directly connected to the gate electrode of the first transistor, a semiconductor layer of the third transistor, and a semiconductor layer of the fourth transistor.

[0009] The semiconductor layer of the third transistor and the semiconductor layer of the fourth transistor can be integrally formed.

[0010] The first sub-gate line to the third sub-gate line and the emission control line can include a first metal layer extending in a first direction. Each of the first electrode of the first capacitor and the second electrode of the first capacitor can include the first metal layer.

[0011] The gate electrode of each of the first transistor to the fifth transistor can include a gate electrode layer. An interlayer insulating layer can be interposed between the gate electrode layer and the first metal layer. The first metal layer can be directly connected to the gate electrode layer through a first contact portion formed in the interlayer insulating layer.

[0012] The first metal layer constituting the first electrode and the second electrode of the first capacitor can extend in the first direction in a region overlapping the gate electrode of the first transistor to face each other when viewed in a plan. The first electrode of the first capacitor and the second electrode of the first capacitor can interdigitate each other along a second direction intersecting the first direction.

[0013] The first power line, the third power line, and the data line can include a second metal layer extending in the second direction. Each of the first electrode of the first capacitor and the second electrode of the first capacitor can include the second metal layer.

[0014] A first via layer can be between the first metal layer and the second metal layer. The second metal layer can be directly connected to the first metal layer at a second contact portion formed through the first via layer.

[0015] At least a portion of the second metal layer constituting the first capacitor can overlap at least a portion of the first metal layer constituting the first capacitor when viewed on a plane.

[0016] The sub-pixel can further include a second capacitor including one electrode connected to the second transistor and another electrode connected to the second node. Each of the one electrode of the second capacitor and the another electrode of the second capacitor can include a third metal layer positioned on the second metal layer.

[0017] Each of the first electrode of the first capacitor and the second electrode of the first capacitor can include the third metal layer.

[0018] A second via layer can be between the second metal layer and the third metal layer. The third metal layer can be directly connected to the second metal layer at a third contact portion formed through the second via layer.

[0019] The third metal layer constituting the first electrode of the first capacitor can be directly connected to the second metal layer constituting the first power line through the third contact portion.

[0020] The third metal layer constituting the second electrode of the first capacitor can be directly connected to the second metal layer constituting the second node through the third contact portion.

[0021] The gate electrode of each of the first to fifth transistors can include a gate electrode layer. The first to third sub-gate lines and the emission control line can include the gate electrode layer extending in a first direction.

[0022] Each of the first electrode of the first capacitor and the second electrode of the first capacitor can include a first metal layer. An interlayer insulating layer can be between the first metal layer and the gate electrode layer. The first metal layer can be directly connected to the gate electrode layer through a first contact portion formed in the interlayer insulating layer.

[0023] Each of the first electrode of the first capacitor and the second electrode of the first capacitor can overlap each of the semiconductor layers of the first to fifth transistors when viewed on a plane.

[0024] According to another aspect of the disclosure, a display device is provided, including a substrate and a plurality of sub-pixels disposed on the substrate. Each of the plurality of sub-pixels can include a pixel circuit layer disposed on the substrate, the pixel circuit layer having a sub-pixel circuit of each of the plurality of sub-pixels, and a light emitting element layer disposed on the pixel circuit layer, the light emitting element layer having a light emitting element of each of the plurality of sub-pixels, wherein the pixel circuit layer includes a semiconductor layer, a gate insulating layer disposed on the semiconductor layer, a gate electrode layer disposed on the gate insulating layer, an interlayer insulating layer disposed on the gate electrode layer, the interlayer insulating layer including a first contact portion, and a first metal layer disposed on the interlayer insulating layer, the first metal layer being directly connected to the gate electrode layer through the first contact portion, the first metal layer constituting a capacitor included in the sub-pixel circuit.

[0025] The sub-pixel circuit can include a first transistor connected between a first power supply line and a first node, the first transistor including a gate electrode connected to a second node, a second transistor connected to a data line, the second transistor including a gate electrode connected to a first sub-gate line, the second transistor receiving a data signal supplied from the data line in response to a first scan signal supplied from the first sub-gate line, a third transistor including a gate electrode connected to a third sub-gate line, the third transistor switching an electrical connection between the first node and the second node in response to a third scan signal supplied from the third sub-gate line, a fourth transistor including a gate electrode connected to a second sub-gate line, the fourth transistor switching an electrical connection between the second node and a third power supply line in response to a second scan signal supplied from the second sub-gate line, a fifth transistor including a gate electrode connected to an emission control line, the fifth transistor switching an electrical connection between the first node and the light emitting element in response to an emission control signal supplied from the emission control line, and the capacitor including a first electrode connected to the first power supply line and a second electrode connected to the second node, wherein the second electrode is directly connected to the gate electrode of the first transistor, a semiconductor layer of the third transistor, and a semiconductor layer of the fourth transistor.

[0026] The gate electrode of each of the first to fifth transistors can include a gate electrode layer. First and second sub-pixels among the plurality of sub-pixels can be positioned adjacent to each other in a first direction. The gate electrode layer can extend in the first direction to be commonly connected to the first and second sub-pixels.

[0027] The display apparatus can further include a gate driving circuit configured to supply a scan signal to the first to third sub-gate lines and to supply an emission control signal to the emission control line. The gate electrode layer can be directly connected to the gate driving circuit. BRIEF DESCRIPTION OF DRAWINGS

[0028] Example embodiments now will be described more fully hereinafter with reference to the accompanying drawings; however, example embodiments can be implemented in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of example embodiments to those skilled in the art.

[0029] In the drawings, the size of some of the elements can be exaggerated for graphically illustrating the present embodiments. It will be understood that when an element is referred to as being "on" another element, it can be directly on the other element or intervening elements can also be present. Like reference numerals refer to like elements throughout.

[0030] Figure 1 is a system block diagram of a display apparatus according to an embodiment of the disclosure.

[0031] Figure 2 is a block diagram illustrating an embodiment of any one of the sub-pixels shown in Figure 1

[0032] Figure 3 is an equivalent circuit diagram illustrating an embodiment of the sub-pixel shown in Figure 2

[0033] Figure 4 is a view illustrating a semiconductor layer and a gate electrode layer of a sub-pixel according to an embodiment of the disclosure.

[0034] Figure 5 is a view illustrating a semiconductor layer, a gate electrode layer, a first contact portion, and a first metal layer of a sub-pixel according to an embodiment of the disclosure.

[0035] Figure 6 is a view illustrating a first metal layer, a second contact portion, and a second metal layer of a sub-pixel according to an embodiment of the disclosure.

[0036] ​​Figure 7 is a view illustrating a second metal layer, a third contact portion, and a third metal layer of a sub-pixel according to an embodiment of the disclosure.

[0037] Figure 8 is a view illustrating a third metal layer, a fourth contact portion, and a fourth metal layer of a sub-pixel according to an embodiment of the disclosure.

[0038] Figure 9 is a view illustrating a semiconductor layer and a gate electrode layer of a sub-pixel according to other embodiments of the disclosure.

[0039] Figure 10 is a view illustrating a semiconductor layer, a gate electrode layer, a first contact portion, and a first metal layer of a sub-pixel according to other embodiments of the disclosure.

[0040] Figure 11 is a plan view illustrating an embodiment of a display panel shown in FIG. Figure 1

[0041] Figure 12 is an exploded perspective view illustrating a portion of a display panel shown in FIG. Figure 11

[0042] Figure 13 is a plan view illustrating an embodiment of any one of the pixels shown in FIG. Figure 12

[0043] Figure 14 is a diagram illustrating an embodiment of a display system according to an embodiment of the disclosure.

[0044] Figure 15 is a perspective view illustrating an application example of a display system shown in FIG. Figure 14

[0045] Figure 16 is a view illustrating a head-mounted display device worn by a user. DETAILED DESCRIPTION

[0046] Hereinafter, exemplary embodiments are described in detail with reference to the accompanying drawings so as to allow those skilled in the art to easily practice the disclosure. The disclosure can be implemented in various different forms and is not limited to the exemplary embodiments described herein.

[0047] For the sake of clarity, portions unrelated to the description will be omitted, and throughout the specification, the same or similar constituent elements will be denoted by the same reference numerals. Therefore, the same or similar elements can be identified using the same reference numerals in different drawings.

[0048] ​​​​Further, the size and thickness of each component shown in the drawings are arbitrarily shown for better understanding and ease of description, but the present disclosure is not limited thereto. The thickness of several portions and regions is exaggerated for the sake of clarity.

[0049] In the description, the expression "equal" can mean "substantially equal". That is, this can mean equal to an extent that can be understood by those skilled in the art. Other expressions can be expressions in which "substantially" is omitted.

[0050] It should be understood that although the terms "first", "second", and so on can be used herein to describe various elements, the elements should not be limited by these terms. The terms are only used to distinguish one element from another. Thus, a "first" element discussed below can also be called a "second" element without departing from the teachings of the present disclosure. As used herein, the singular forms are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0051] The terms "below", "under", "on", and "above" and the like are used to describe relationships of components shown in the drawings. These terms are relative and are described with reference to the directions shown in the drawings.

[0052] Unless otherwise defined, it will be understood that all terms used in the present specification, including technical and scientific terms, have the same meaning as those understood by one of ordinary skill in the art. In addition, terms defined by a general dictionary should not be ideally or overly formally defined unless specifically defined.

[0053] It will also be understood that the terms "include" and / or "comprise", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0054] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0055] Figure 1 is a system block diagram of a display apparatus 100 according to an embodiment of the present disclosure.

[0056] Referring to Figure 1 , the display apparatus 100 according to an embodiment of the present disclosure can include a display panel 110, a gate driving circuit 120, a data driver 130, a voltage generator 140, a controller 150, and a temperature sensor 160, etc.

[0057] The display panel 110 can include a plurality of sub-pixels SP. First to m-th gate lines GL1 to GLm (m is an integer of 1 or more) connected to the plurality of sub-pixels SP can be disposed in the display panel 110. First to n-th data lines DL1 to DLn (n is an integer of 1 or more) connected to the plurality of sub-pixels SP can be disposed in the display panel 110.

[0058] The plurality of sub-pixels SP can be connected (e.g., electrically connected) to the gate driving circuit 120 through the first to m-th gate lines GL1 to GLm. The plurality of sub-pixels SP can be connected (e.g., electrically connected) to the data driver 130 through the first to n-th data lines DL1 to DLn.

[0059] Each of the plurality of sub-pixels SP can include at least one light emitting element configured to generate light. Each of the plurality of sub-pixels SP can generate light of a color (e.g., a specific color or a specific wavelength band) such as red, green, blue, cyan, magenta, or yellow. Two or more sub-pixels of the plurality of sub-pixels SP can constitute one pixel PXL. For example, as shown in FIG. 1B, three sub-pixels SP can constitute one pixel PXL. Figure 1

[0060] The gate driving circuit 120 can be connected (e.g., electrically connected) to the plurality of sub-pixels SP (e.g., the plurality of sub-pixels SP arranged entirely in the first direction DR1) through the first to m-th gate lines GL1 to GLm. The first direction DR1 can be, for example, a direction crossing the display panel 110 from one side (e.g., the left side) to the other side (e.g., the right side) of the display panel 110. The first direction DR1 can be, for example, a row direction.

[0061] The gate driving circuit 120 can output a gate signal (e.g., a gate signal having an on level or an off level) to the first to m-th gate lines GL1 to GLm in response to a gate control signal GCS. In an embodiment, the gate control signal GCS can include a start signal indicating the start of each frame and a horizontal synchronization signal for outputting a gate signal in synchronization with a timing at which a data signal is applied, etc.

[0062] ​In an embodiment, first to mth emission control lines EL1 to ELm connected to the plurality of subpixels SP can be further provided in the display panel 110. The first to mth emission control lines EL1 to ELm can be provided in the display panel 110 while extending in the row direction. The plurality of subpixels SP can be connected (e.g., electrically connected) to the first to mth emission control lines EL1 to ELm. In the above-described embodiment, the gate driving circuit 120 can include an emission control driver configured to control the first to mth emission control lines EL1 to ELm. The emission control driver can operate under the control of the controller 150.

[0063] The gate driving circuit 120 can be provided at one side of the display panel 110. However, embodiments of the present disclosure are not limited thereto. For example, the gate driving circuit 120 can include two or more driving circuits physically separated, and the driving circuits can be provided at one side of the display panel 110 and the other side (e.g., a side of the display panel 110 facing the other side of the display panel 110) of the display panel 110. As such, in some embodiments, the gate driving circuit 120 can be provided in various forms in or at the periphery of the display panel 110.

[0064] The data driver 130 can be connected (e.g., electrically connected) to the plurality of subpixels SP (e.g., the plurality of subpixels SP arranged in the second direction DR2 as a whole) through the first to nth data lines DL1 to DLn. The second direction DR2 can be, for example, a direction crossing the display panel 110 from one side (e.g., a lower side) of the display panel 110 to the other side (e.g., an upper side) of the display panel 110. The second direction DR2 can be, for example, a column direction.

[0065] The data driver 130 can receive the image data DATA and the data control signal DCS from the controller 150. The data driver 130 can operate in response to the data control signal DCS. In an embodiment, the data control signal DCS can include a source start pulse, a source shift clock, and a source output enable signal, etc.

[0066] The data driver 130 can apply a data signal having a gray voltage corresponding to the image data DATA to the first to nth data lines DL1 to DLn by using a voltage (e.g., a gamma voltage Vgamma) from the voltage generator 140. When a gate signal (e.g., a gate signal having an on level) is applied to each of the first to mth gate lines GL1 to GLm, a data signal corresponding to the image data DATA can be applied to the data lines DL1 to DLm. Each of the plurality of sub-pixels SP can receive a data signal applied at a corresponding timing in response to a gate signal (e.g., a gate signal having an on level). Each of the plurality of sub-pixels SP can generate light corresponding to the received data signal. Accordingly, an image can be displayed in the display panel 110.

[0067] In an embodiment, each of the gate driving circuit 120 and the data driver 130 can include a complementary metal-oxide semiconductor (CMOS) circuit element.

[0068] The voltage generator 140 can operate in response to a voltage control signal VCS from the controller 150. The voltage generator 140 can be configured to generate a plurality of voltages and provide the generated voltages to components of the display apparatus 100. For example, the voltage generator 140 can receive an input voltage from outside of the display apparatus 100. The voltage generator 140 can adjust (e.g., lower) a level of the received voltage and regulate the voltage having the adjusted level. The voltage generator 140 can be configured to generate a plurality of voltages.

[0069] The voltage generator 140 can generate, for example, a first power voltage VDD, a second power voltage VSS, and a gamma voltage Vgamma, etc. The generated first power voltage VDD and second power voltage VSS can be applied (e.g., commonly applied) to the plurality of sub-pixels SP. The first power voltage VDD can have a relatively high voltage level. The second power voltage VSS can have a voltage level lower than that of the first power voltage VDD. The generated gamma voltage Vgamma can be provided to the data driver 130. In other embodiments, the first power voltage VDD and / or the second power voltage VSS can be provided by an external device (e.g., a power management integrated circuit (PMIC)) of the display apparatus 100.

[0070] In some embodiments, the voltage generator 140 can further generate another voltage. For example, the voltage generator 140 can generate an initialization voltage applied (e.g., commonly applied) to the plurality of sub-pixels SP. For example, in a sensing operation for sensing electrical characteristics of the transistors and / or one or more light emitting elements of the plurality of sub-pixels SP, a predetermined reference voltage can be applied to the first data line DL1 to the n-th data line DLn, and the voltage generator 140 can generate the reference voltage.

[0071] The controller 150 can be configured to control overall operations of the display apparatus 100. The controller 150 can receive input image data IMG and a control signal CTRL for controlling the display apparatus 100 from the outside. The controller 150 can provide a gate control signal GCS, a data control signal DCS, and a voltage control signal VCS, etc., in response to the received control signal CTRL.

[0072] The controller 150 can convert the input image data IMG to be suitable for the display apparatus 100 or the display panel 110, thereby outputting image data DATA. In an embodiment, the controller 150 can align the input image data IMG in a unit of a row to be suitable for the sub-pixel SP, thereby outputting the image data DATA.

[0073] Two or more components among the data driver 130, the voltage generator 140, and the controller 150 can be mounted in one integrated circuit. As Figure 1 As shown in FIG. 1, the data driver 130, the voltage generator 140, and the controller 150 can be included in a driver integrated circuit DIC. The data driver 130, the voltage generator 140, and the controller 150 can be components functionally divided in one driver integrated circuit DIC. In other embodiments, at least one of the data driver 130, the voltage generator 140, and the controller 150 can be integrated into the driver integrated circuit DIC, and another of the data driver 130, the voltage generator 140, and the controller 150 can be integrated into an integrated circuit different from the driver integrated circuit DIC.

[0074] The temperature sensor 160 can be configured to sense a temperature (e.g., a temperature at a periphery thereof) and generate temperature data TEP indicating the sensed temperature. In some embodiments, the temperature sensor 160 can be disposed in the display panel 110. In some embodiments, the temperature sensor 160 can be disposed adjacent to the display panel 110 and / or the driver integrated circuit DIC. In some embodiments, the display apparatus 100 can include two or more temperature sensors 160.

[0075] The controller 150 can control various operations of the display apparatus 100 in response to the temperature data TEP. In an embodiment, the controller 150 can adjust the brightness of an image output from the display panel 110 in response to the temperature data TEP. For example, the controller 150 can control components such as the data driver 130 and / or the voltage generator 140, thereby adjusting at least one of a data signal, the first power voltage VDD, and the second power voltage VSS input to the display panel 110.

[0076] Figure 2 is a block diagram illustrating an embodiment of any one of the sub-pixels SP shown in FIG. 1. Figure 1

[0077] In Figure 2 , the sub-pixel SPij among the plurality of sub-pixels SP shown in FIG. 1 is exemplarily illustrated. Figure 1

[0078] Referring to Figure 2 , the sub-pixel SPij can include a sub-pixel circuit SPC and a light emitting element LD.

[0079] The light emitting element LD can be connected (e.g., electrically connected) between a first power voltage node VDDN and a second power voltage node VSSN. The first power voltage node VDDN can be a node to which the first power voltage VDD shown in FIG. 1 is applied. The second power voltage node VSSN can be a node to which the second power voltage VSS shown in FIG. 1 is applied. Figure 1 Figure 1

[0080] The light emitting element LD can include a first electrode, a light emitting structure EMS, and a second electrode. The first electrode can be any one of an anode electrode AE and a cathode electrode CE of the light emitting element LD. The second electrode can be the other of the anode electrode AE and the cathode electrode CE of the light emitting element LD. Hereinafter, a case where the first electrode of the light emitting element LD is the anode electrode AE and the second electrode of the light emitting element LD is the cathode electrode CE is described as an example for convenience of description.

[0081] The anode electrode AE of the light emitting element LD can be connected (e.g., electrically connected) to the first power voltage node VDDN through the sub-pixel circuit SPC. The cathode electrode CE of the light emitting element LD can be connected (e.g., electrically connected) to the second power voltage node VSSN. For example, the anode electrode AE of the light emitting element LD can be connected (e.g., electrically connected) to the first power voltage node VDDN through one or more transistors included in the sub-pixel circuit SPC.

[0082] ​​​​The sub-pixel circuit SPC of the sub-pixel SPij can be connected (e.g., electrically connected) to the i-th gate line GLi among the first gate line GL1 to the m-th gate line GLm shown in Figure 1 The sub-pixel circuit SPC of the sub-pixel SPij can be connected (e.g., electrically connected) to the i-th emission control line ELi among the first emission control line EL1 to the m-th emission control line ELm shown in Figure 1 The sub-pixel circuit SPC of the sub-pixel SPij can be connected (e.g., electrically connected) to the j-th data line DLj among the first data line DL1 to the n-th data line DLn shown in Figure 1 The sub-pixel circuit SPC can be configured to control the emission timing and / or the emission luminance of the light emitting element LD according to (or in response to) the signals received through the signal lines.

[0083] The sub-pixel circuit SPC can operate in response to the gate signal received through the i-th gate line GLi. The sub-pixel circuit SPC can operate in response to the emission control signal received through the i-th emission control line ELi.

[0084] The sub-pixel circuit SPC can receive the data signal through the j-th data line DLj. The sub-pixel circuit SPC can store the voltage of (or corresponding to) the data signal in response to the gate signal (e.g., the gate signal having the on level) received through the i-th gate line GLi. The sub-pixel circuit SPC can adjust the timing of the current flowing through the light emitting element LD in response to the emission control signal (e.g., the emission control signal having the on level) applied through the i-th emission control line ELi. The magnitude of the current flowing through the light emitting element LD can vary according to the voltage stored in the sub-pixel circuit SPC. The light emitting element LD can generate light having a luminance corresponding to the data signal.

[0085] Figure 3 is an equivalent circuit diagram illustrating an embodiment of the sub-pixel SPij shown in Figure 2

[0086] Referring to Figure 3 The sub-pixel SPij according to an embodiment of the disclosure can include a sub-pixel circuit SPC and a light emitting element LD.

[0087] The sub-pixel circuit SPC can be connected (e.g., electrically connected) to the i-th gate line GLi (hereinafter simply referred to as the gate line GLi), the i-th emission control line ELi (hereinafter simply referred to as the emission control line ELi), and the j-th data line DLj (hereinafter simply referred to as the data line DLj).

[0088] The gate line GLi can include two or more sub-gate lines. Referring to Figure 3 ​The gate line GLi can include a first sub-gate line SGL1i (or simply referred to as a first sub-gate line SGL1), a second sub-gate line SGL2i (or simply referred to as a second sub-gate line SGL2), and a third sub-gate line SGL3i (or simply referred to as a third sub-gate line).

[0089] The sub-pixel circuit SPC can include two or more switching elements (e.g., transistors) and one or more storage elements (e.g., capacitors). Referring to FIG. 1, the sub-pixel circuit SPC can include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, and a fifth transistor T5. Figure 3 The sub-pixel circuit SPC according to an embodiment of the disclosure can include a first transistor T1 to a fifth transistor T5, and a first capacitor C1 and a second capacitor C2.

[0090] The first transistor T1 can be configured to switch an electrical connection between the first power line PL1 and the first node NODE1. In this document, the expression "switch an electrical connection between A and B" can mean to electrically connect A and B to each other or to electrically disconnect A and B. The first power line PL1 can be a line to which a first power voltage VDD is delivered. The first transistor T1 can include a gate electrode connected (e.g., electrically connected) to the second node NODE2. A current (e.g., a driving current) having a magnitude corresponding to a voltage applied to the second node NODE2 can flow through the first transistor T1. The first power voltage VDD can be applied to a body electrode of the first transistor T1.

[0091] The second transistor T2 can be configured to switch an electrical connection between the data line DLj and the second capacitor C2. A gate electrode of the second transistor T2 can be connected (e.g., electrically connected) to the first sub-gate line SGL1i. An operation timing of the second transistor T2 can be controlled by a first scan signal GW[i] supplied from the first sub-gate line SGL1i. The second transistor T2 can electrically connect the data line DLj to the second capacitor C2 in response to the first scan signal GW[i] having an on level. When the second transistor T2 is turned on, a data signal VDATA can be input to the second capacitor C2.

[0092] The third transistor T3 can be configured to switch an electrical connection between the first node NODE1 and the second node NODE2. A gate electrode of the third transistor T3 can be connected (e.g., electrically connected) to the third sub-gate line SGL3i. An operation timing of the third transistor T3 can be controlled by a third scan signal GC[i] supplied from the third sub-gate line SGL3i. The third transistor T3 can electrically connect the first node NODE1 to the second node NODE2 in response to the third scan signal GC[i] having an on level. When the third transistor T3 is turned on, the first transistor T1 can be diode-connected.

[0093] The fourth transistor T4 can be configured to switch an electrical connection between the second node NODE2 and a third power supply line PL3. A third power supply voltage VREF can be supplied from the third power supply line PL3. The third power supply voltage VREF can be provided by, for example, the voltage generator 140 (see Figure 1 ) The gate electrode of the fourth transistor T4 can be connected (e.g., electrically connected) to a second sub-gate line SGL2i. The operation timing of the fourth transistor T4 can be controlled by a second scan signal GR[i] supplied from the second sub-gate line SGL2i. The fourth transistor T4 can electrically connect the third power supply line PL3 to the second node NODE2 in response to the second scan signal GR[i] having an on level. When the fourth transistor T4 is on, the voltage of the second node NODE2 can be initialized to the third power supply voltage VREF.

[0094] The fifth transistor T5 can be configured to switch an electrical connection between the first node NODE1 and the light emitting element LD. The gate electrode of the fifth transistor T5 can be connected (e.g., electrically connected) to an emission control line ELi. The operation timing of the fifth transistor T5 can be controlled by an emission control signal EM[i] supplied from the emission control line ELi. The fifth transistor T5 can electrically connect the first node NODE1 to the light emitting element LD in response to the emission control signal EM[i] having an on level. When the fifth transistor T5 is on, a current (e.g., a driving current) can flow through the light emitting element LD.

[0095] The first capacitor C1 can be configured to hold a potential difference between the second node NODE2 and the first power supply line PL1. The first capacitor C1 can be connected between the first power supply line PL1 and the second node NODE2. The first capacitor C1 can include a first electrode E1 connected (e.g., electrically connected) to the first power supply line PL1 and a second electrode E2 connected (e.g., electrically connected) to the second node NODE2. The first electrode E1 and the second electrode E2 can be disposed to face each other. The amount of charge to be stored in the first capacitor C1 (or the capacitance of the first capacitor C1) can vary depending on the area in which the first electrode E1 and the second electrode E2 overlap each other. For example, when the area in which the first electrode E1 and the second electrode E2 overlap each other while facing each other is large, the amount of charge to be stored in the first capacitor C1 can be relatively large.

[0096] The second capacitor C2 can be connected between the second transistor T2 and the second node NODE2. The second capacitor C2 can include one electrode connected to the second transistor T2 and the other electrode connected to the second node NODE2. The data signal VDATA or a voltage corresponding thereto can be applied to the one electrode of the second capacitor C2. The third power supply voltage VREF can be applied to the other electrode of the second capacitor C2. When the data signal VDATA is input to the one electrode of the second capacitor C2, the voltage of the second node NODE2 can be changed from the third power supply voltage VREF by a coupling effect of the second capacitor C2.

[0097] Referring to Figure 3 Each of the first transistor T1 to the fifth transistor T5 can be a P-type transistor (e.g., a transistor including a P-type semiconductor). However, embodiments of the disclosure are not limited thereto. For example, at least one of the first transistor T1 to the fifth transistor T5 can be implemented as an N-type transistor (e.g., a transistor including an N-type semiconductor). At least one of the first transistor T1 to the fifth transistor T5 can be a metal oxide semiconductor field effect transistor (MOSFET).

[0098] In an embodiment, each of the first transistor T1 to the fifth transistor T5 can include a semiconductor layer. The semiconductor layer of each of the first transistor T1 to the fifth transistor T5 can include an amorphous silicon semiconductor, a polysilicon semiconductor, and an oxide semiconductor, etc.

[0099] The light emitting element LD can include an anode electrode AE, a cathode electrode CE, and a light emitting structure EMS. The anode electrode AE of the light emitting element LD can be connected (e.g., electrically connected) to the fifth transistor T5. The cathode electrode CE of the light emitting element LD can be connected (e.g., electrically connected) to the second power supply line PL2. The second power supply voltage VSS can be supplied from the second power supply line PL2. The light emitting structure EMS can be disposed between the anode electrode AE and the cathode electrode CE. The data signal VDATA written to the sub-pixel SPij through the data line DLj can be changed to the voltage of the second node NODE2 by a coupling effect of the second capacitor C2. When the emission control signal EM[i] is enabled to an on level (e.g., a low level), the fifth transistor T5 can be turned on. The first transistor T1 can be turned on according to the voltage of the second node NODE2, and a current (e.g., a driving current) having a size corresponding to the voltage of the second node NODE2 can flow through the first transistor T1. Accordingly, a current can flow from the first power supply line PL1 to the second power supply line PL2. The light emitting element LD can emit light having a luminance corresponding to the size of the current (e.g., a driving current) flowing through the light emitting element LD.

[0100] Figure 4is a view showing a semiconductor layer ACT and a gate electrode layer GAT of a sub-pixel SPij and SPi(j+1) according to an embodiment of the disclosure.

[0101] In some embodiments, the semiconductor layer (also referred to herein as an active layer) ACT can be part of the substrate SUB (see Figure 1 ). In some embodiments, the active layer ACT can be formed on the substrate SUB separately from the substrate SUB. For example, in an embodiment in which the substrate SUB according to an embodiment of the disclosure is a silicon substrate, the active layer ACT can be part of the substrate SUB.

[0102] The gate electrode layer GAT can include a low-resistance metal material. The gate electrode layer GAT can be formed as a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or any alloy thereof.

[0103] A gate insulating layer (not shown) configured to insulate the semiconductor layer ACT and the gate electrode layer GAT from each other can be interposed between the semiconductor layer ACT and the gate electrode layer GAT. The gate insulating layer can include an inorganic insulating material. For example, the gate insulating layer can include an inorganic insulating material such as silicon oxide (SiO2), silicon nitride (SiN x ) (x is a positive number), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and / or zinc oxide (ZnO x , which can be ZnO or ZnO2).

[0104] Referring to Figure 4 , a first sub-pixel SPij and a second sub-pixel SPi(j+1) adjacent to each other in a first direction DR1 are shown.

[0105] Each of the first sub-pixel SPij and the second sub-pixel SPi(j+1) can include first to fifth transistors T1 to T5. The first to fifth transistors T1 to T5 can correspond to the first to fifth transistors T1 to T5 of the sub-pixel circuit SPC described above with reference to Figure 3 . Each of the first to fifth transistors T1 to T5 can include the semiconductor layer ACT and the gate electrode layer GAT.

[0106] The gate electrode layer GAT can constitute a gate electrode of each of the first to fifth transistors T1 to T5.

[0107] The semiconductor layer ACT can constitute a semiconductor layer of each of the first to fifth transistors T1 to T5. The semiconductor layer ACT can include a channel region positioned in a region where the semiconductor layer ACT overlaps (e.g., overlaps in a vertical direction) with the gate electrode layer GAT. The semiconductor layer ACT can include a drain region and a source region positioned adjacent to the channel region. The drain region of the semiconductor layer ACT can be connected to a drain electrode of the corresponding transistor. The source region of the semiconductor layer ACT can be connected to a source region of the corresponding transistor.

[0108] The semiconductor layer ACT of the third transistor T3 and the semiconductor layer ACT of the fourth transistor T4 can be connected to each other (e.g., integrally formed).

[0109] The first transistor T1 can include a first (1_1) transistor T1_1 and a second (1_2) transistor T1_2. The first (1_1) transistor T1_1 and the second (1_2) transistor T1_2 can share the semiconductor layer ACT and the gate electrode layer GAT with each other. Thus, the first transistor T1 has the same effect as the length of the channel region is elongated in the semiconductor layer ACT. However, embodiments of the disclosure are not limited as described above, and the first transistor T1 can include one transistor.

[0110] The gate electrode layer GAT can be connected to each other in the first and second sub-pixels SPij and SPi(j+1) disposed adjacent to each other in the first direction DR1. Referring to FIG. 1, the gate electrode layer GAT can be connected to each other in the first and second sub-pixels SP11 and SP12 disposed adjacent to each other in the first direction DR1. Figure 4 In the first direction DR1, the gate electrodes of the second to fifth transistors T2 to T5 disposed adjacent to each other can be connected to each other as the gate electrode layer GAT.

[0111] The body electrode BODY of the first transistor T1 can be positioned between two sub-pixels disposed adjacent to each other. Thus, a space can be efficiently configured. The body electrode BODY can include the semiconductor layer ACT.

[0112] At least a portion (e.g., the gate electrode layer GAT constituting the first transistor T1) of the gate electrode layer GAT positioned at one side (e.g., a side away from the body electrode BODY in the first direction DR1) of the body electrode BODY can protrude toward the body electrode BODY. However, embodiments of the disclosure are not limited thereto. For example, the gate electrode layer GAT constituting the first transistor T1 can have a quadrangular shape without any portion protruding toward the body electrode BODY.

[0113] The first scan signal GW can be input to the gate electrode layer GAT of the second transistor T2. The third scan signal GC can be input to the gate electrode layer GAT of the third transistor T3. The second scan signal GR can be input to the gate electrode layer GAT of the fourth transistor T4. The emission control signal EM can be input to the gate electrode layer GAT of the fifth transistor T5.

[0114] Figure 5 is a view illustrating a semiconductor layer ACT, a gate electrode layer GAT, a first contact portion CNT1, and a first metal layer M1 of a sub-pixel according to an embodiment of the disclosure.

[0115] An interlayer insulating layer ILD can be formed on the gate electrode layer GAT. The first metal layer M1 can be formed on the interlayer insulating layer ILD. In a region in which at least a portion of the interlayer insulating layer ILD is removed, the first metal layer M1 can be connected to (e.g., contact) the gate electrode layer GAT or the semiconductor layer ACT. Referring to Figure 5 At the first contact portion CNT1 included in the interlayer insulating layer ILD, the gate electrode layer GAT and the first metal layer M1 can be connected to each other. Referring to Figure 5 At the first contact portion CNT1 included in the interlayer insulating layer ILD, the semiconductor layer ACT and the first metal layer M1 can be connected to each other.

[0116] The interlayer insulating layer ILD can be formed of an inorganic layer. For example, the interlayer insulating layer ILD can be formed of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer, but embodiments of the disclosure are not limited thereto.

[0117] The first metal layer M1 can be formed as a single layer or a plurality of layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or any alloy thereof, but embodiments of the disclosure are not limited thereto.

[0118] The first metal layer M1 can constitute a signal line extending entirely in the first direction DR1. For example, referring to Figure 5 , the first metal layer M1 can constitute a gate line GLi (see Figure 2 ) and an emission control line ELi (see Figure 2 ). Referring to Figure 5 , the first metal layer M1 can constitute a first sub-gate line SGL1 (see Figure 3 ) to which the first scan signal GW is input, a second sub-gate line SGL2 (see Figure 3 ) to which the second scan signal GR is input, and a third sub-gate line SGL3 (see Figure 3). The first metal layer M1 can constitute an emission control line EL (see Figure 3 ) to which an emission control signal EM is input. The first metal layer M1 constituting the first to third sub-gate lines SGL1 to SGL3 and the emission control line EL can extend in the first direction DR1.

[0119] The first metal layer M1 can constitute the second node NODE2. The first metal layer M1 can be connected to the semiconductor layer ACT of the third transistor T3 (see Figure 4 ) and the fourth transistor T4 (see Figure 4 ). The first metal layer M1 can be connected to the gate electrode layer GAT of the first transistor T1 (see Figure 4 ). For example, the first metal layer M1 can be connected to a drain region formed in the semiconductor layer ACT of the third transistor T3 and the fourth transistor T4.

[0120] The first power supply voltage VDD can be applied to the first metal layer M1. The first power supply voltage VDD can be applied to a source region in the active layer ACT of the first transistor T1 (see Figure 4 ) through the metal layer M1. The first power supply voltage VDD can be applied to the first electrode E1 of the first capacitor C1 through the metal layer M1.

[0121] The first metal layer M1 can constitute the first capacitor C1 in a region in which the first metal layer M1 overlaps (e.g., overlaps in the vertical direction) the semiconductor layer ACT and / or the gate electrode layer GAT of the first transistor T1 (see Figure 4 ). With reference to Figure 5 , the second node NODE2 can constitute the second electrode E2 of the first capacitor C1 in a region in which the first metal layer M1 overlaps (e.g., overlaps in the vertical direction) the semiconductor layer ACT and / or the gate electrode layer GAT of the first transistor T1. To increase the storage capacitance of the first capacitor C1, the first metal layer M1 constituting the first capacitor C1 can have a branched structure in which the first metal layer M1 constituting each electrode extends along the first direction DR1. The metal layer M1 constituting the first electrode E1 of the first capacitor C1 can be interleaved with the second electrode E2 of the first capacitor C1 along the second direction DR2. With reference to Figure 5 , the first metal layer M1 can extend along the first direction DR1 in a region in which the first metal layer M1 overlaps the gate electrode layer GAT of the first transistor T1 in the vertical direction.

[0122] The first metal layer M1 can carry the data signal VDATA. The first metal layer M1 in which the data signal VDATA is written can be connected to the second transistor T2 (see Figure 4The semiconductor layer ACT of the second transistor T2. The region in which the data signal VDATA is written in the semiconductor layer ACT of the second transistor T2 can be a drain region.

[0123] The first metal layer M1 can constitute the first node NODE1. Referring to Figure 5 , the metal layer M1 connected to the drain region in the semiconductor layer ACT of the first transistor T1 (see Figure 4 ) by the first contact portion CNT1 can constitute the first node NODE1.

[0124] The first metal layer M1 can constitute the first capacitor C1. The first electrode E1 of the first capacitor C1 can correspond to the first power voltage VDD be applied to the region of the first metal layer M1. The second electrode E2 of the first capacitor C1 can correspond to the second node NODE2 in the first metal layer M1.

[0125] The first metal layer M1 can constitute the body electrode BODY (see Figure 4 ). The first metal layer M1 can be connected to the semiconductor layer ACT constituting the body electrode BODY through the first contact portion CNT1 on the semiconductor layer ACT.

[0126] Figure 6 is a view illustrating the first metal layer M1, the second contact portion CNT2, and the second metal layer M2 of a sub-pixel according to an embodiment of the disclosure.

[0127] Referring to Figure 6 , the first via layer VIA1 can be interposed between the first metal layer M1 and the second metal layer M2. The first via layer VIA1 can include the second contact portion CNT2 positioned in the region in which at least a portion of the first via layer VIA1 is removed. The second metal layer M2 can be connected to (e.g., contact) the first metal layer M1 at the second contact portion CNT2.

[0128] The first via layer VIA1 can be formed of an organic layer such as an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, or a polyimide resin, but embodiments of the disclosure are not limited thereto. In some embodiments, the first via layer VIA1 can be formed of an inorganic layer such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0129] The second metal layer M2 can be formed as a single layer or a multi-layer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or any alloy thereof, but embodiments of the disclosure are not limited thereto.

[0130] The second metal layer M2 can constitute the first node NODE1. The second metal layer M2 can be connected to the first metal layer M1 by the second contact portion CNT2. Further reference is made to Figure 4 and Figure 5 The first metal layer M1 can be connected to a source region of the semiconductor layer ACT of the third transistor T3. The first metal layer M1 can be connected to a drain region of the semiconductor layer ACT of the first transistor T1. The first metal layer M1 can be connected to a source region of the semiconductor layer ACT of the fifth transistor T5.

[0131] The second metal layer M2 can constitute a signal line extending entirely in the second direction DR2. For example, reference is made to Figure 6 The second metal layer M2 can constitute a power supply line and a data line extending entirely in the second direction DR2. The second metal layer M2 can constitute a first power supply line PL1 to which the first power supply voltage VDD is applied (see Figure 3 ). The second metal layer M2 can constitute a third power supply line PL3 to which the third power supply voltage VREF is applied (see Figure 3 ). The second metal layer M2 can constitute a data line DL to which the data signal VDATA is applied (see Figure 3 ).

[0132] The second metal layer M2 can apply the first power supply voltage VDD to the first metal layer M1 at the second contact portion CNT2. Reference is made to Figure 4 and Figure 5 The first metal layer M1 can transmit the first power supply voltage VDD to a source region of the semiconductor layer ACT of the first transistor T1 at the first contact portion CNT1. The first metal layer M1 to which the first power supply voltage VDD is applied can constitute a first electrode E1 of the first capacitor C1.

[0133] The second metal layer M2 can apply the third power supply voltage VREF to the first metal layer M1 at the second contact portion CNT2. Reference is made to Figure 4 and Figure 5 A source region in the semiconductor layer ACT of the fourth transistor T4 can be connected to the first metal layer M1 such that the third power supply voltage VREF is applied to the source region in the semiconductor layer ACT of the fourth transistor T4.

[0134] The second metal layer M2 can apply the data signal VDATA to the first metal layer M1 at the second contact portion CNT2. Reference is made to Figure 4 and Figure 5 A drain region in the semiconductor layer ACT of the second transistor T2 can be connected to the first metal layer M1 such that the data signal VDATA is applied to the drain region in the semiconductor layer ACT of the second transistor T2.

[0135] The second metal layer M2 can constitute at least a portion of the anode ANODE. Further referring to Figure 3 , the second metal layer M2 can constitute at least a portion of the anode electrode AE of the light emitting element LD.

[0136] The second metal layer M2 can constitute the first capacitor C1. The first electrode E1 of the first capacitor C1 can correspond to a region of the second metal layer M2 to which the first power voltage VDD is applied. The second electrode E2 of the first capacitor C1 can correspond to a region of the second metal layer M2 connected to the second node NODE2. At least a portion of the second metal layer M2 constituting the first capacitor C1 can be positioned while overlapping (e.g., overlapping in a vertical direction) with the first metal layer M1 constituting the first capacitor C1.

[0137] Figure 7 is a view illustrating the second metal layer M2, the third contact portion CNT3, and the third metal layer M3 of a sub-pixel according to an embodiment of the disclosure.

[0138] Referring to Figure 7 , the second via layer VIA2 can be interposed between the second metal layer M2 and the third metal layer M3. The second via layer VIA2 can include the third contact portion CNT3 positioned in a region in which at least a portion of the second via layer VIA2 is removed. The third metal layer M3 can be connected to (e.g., contact) the second metal layer M2 at the third contact portion CNT3.

[0139] The second via layer VIA2 can be formed of an organic layer such as an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, or a polyimide resin, but embodiments of the disclosure are not limited thereto. The second via layer VIA2 can be formed of an inorganic layer such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0140] The third metal layer M3 can be formed as a single layer or a multi-layer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or any alloy thereof, but embodiments of the disclosure are not limited thereto.

[0141] The third metal layer M3 can be connected to the second metal layer M2 at the third contact portion CNT3 such that the first power voltage VDD is applied to the third metal layer M3. The third metal layer M3 can be connected to the second metal layer M2 at the third contact portion CNT3 to constitute the second node NODE2. The third metal layer M3 can be connected to the second metal layer M2 at the third contact portion CNT3 to constitute at least a portion of the anode ANODE.

[0142] The third metal layer M3 can constitute the first capacitor C1. The first electrode E1 of the first capacitor C1 can correspond to the region where the first power supply voltage VDD is applied to the third metal layer M3. The second electrode E2 of the first capacitor C1 can correspond to the region where the third metal layer M3 is connected to the second node NODE2. At least a portion of the third metal layer M3 constituting the first capacitor C1 can be connected to the second metal layer M2 to which the first power supply voltage VDD is applied.

[0143] The third metal layer M3 can form the second capacitor C2. One electrode of the second capacitor C2 can be located at a predetermined node T2 (see...). Figure 8 Connected to the second transistor T2 at (see) Figure 4 The other electrode of the second capacitor C2 may include a third metal layer M3 connected to the second node NODE2.

[0144] Figure 8 This is a view showing the third metal layer M3, the fourth contact portion CNT4, and the fourth metal layer M4 of a sub-pixel according to an embodiment of the present disclosure.

[0145] Reference Figure 8 The third via layer VIA3 may be located between the third metal layer M3 and the fourth metal layer M4. The third via layer VIA3 may include a fourth contact portion CNT4 located in an area where at least a portion of the third via layer VIA3 is removed. The fourth metal layer M4 may be connected to (e.g., in contact with) the third metal layer M3 at the fourth contact portion CNT4.

[0146] The third via layer VIA3 can be formed of an organic layer such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin, but the embodiments disclosed herein are not limited thereto. The third via layer VIA3 can also be formed of an inorganic layer such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0147] The fourth metal layer M4 can be formed as a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or any alloy thereof, but the embodiments disclosed herein are not limited thereto.

[0148] A fourth metal layer M4 can be connected to the third metal layer M3 at the fourth contact portion CNT4, such that a first power supply voltage VDD is applied to the fourth metal layer M4. The fourth metal layer M4 can be connected to the third metal layer M3 at the fourth contact portion CNT4 to form the second node NODE2. The fourth metal layer M4 can be connected to the third metal layer M3 at the fourth contact portion CNT4 to form at least a portion of the anode ANODE.

[0149] The fourth metal layer M4 can constitute the first capacitor C1. A region of the fourth metal layer M4 to which the first electrode E1 of the first capacitor C1 can be applied can correspond to the first power voltage VDD. A region of the fourth metal layer M4 to which the second electrode E2 of the first capacitor C1 can be connected can correspond to the second node NODE2.

[0150] The fourth metal layer M4 can constitute the second capacitor C2. One electrode of the second capacitor C2 can be connected to the second transistor T2 at the predetermined node T2 NODE (see Figure 4 ). The other electrode of the second capacitor C2 can include the fourth metal layer M4 connected to the second node NODE2.

[0151] For a complete Figures 4 to 8 , in the sub-pixel SP (see Figure 1 ) according to an embodiment of the disclosure, the first capacitor C1 can include the first metal layer M1 to the fourth metal layer M4. Accordingly, the capacitance of the first capacitor C1 can be increased.

[0152] Figure 9 is a view showing a semiconductor layer ACT and a gate electrode layer GAT of a sub-pixel according to other embodiments of the disclosure.

[0153] In some embodiments, the semiconductor layer ACT can be part of the substrate SUB (see Figure 1 ). In some embodiments, the active layer ACT can be formed on the substrate SUB separately from the substrate SUB. For example, in an embodiment in which the substrate SUB according to an embodiment of the disclosure is a silicon substrate, the active layer ACT can be part of the substrate SUB.

[0154] A gate insulating layer (not shown) configured to insulate the semiconductor layer ACT and the gate electrode layer GAT from each other can be interposed between the semiconductor layer ACT and the gate electrode layer GAT.

[0155] Referring to Figure 9 , a first sub-pixel SPij and a second sub-pixel SPi(j+1) disposed adjacent to each other in the first direction DR1 are shown.

[0156] Each of the first sub-pixel SPij and the second sub-pixel SPi(j+1) can include the first transistor T1 to the fifth transistor T5. The first transistor T1 to the fifth transistor T5 can correspond to the first transistor T1 to the fifth transistor T5 of the sub-pixel circuit SPC described above with reference to Figure 3 . Each of the first transistor T1 to the fifth transistor T5 can include the semiconductor layer ACT and the gate electrode layer GAT.

[0157] The gate electrode layer GAT can constitute a gate electrode of each of the first to fifth transistors T1 to T5.

[0158] The gate electrode layer GAT can constitute a first sub-gate line SGL1 (see Figure 3 ) to which a first scan signal GW is supplied. The gate electrode layer GAT can constitute a second sub-gate line SGL2 (see Figure 3 ) to which a second scan signal GR is supplied. The gate electrode layer GAT can constitute a third sub-gate line SGL3 (see Figure 3 ) to which a third scan signal GC is supplied. The gate electrode layer GAT can constitute an emission control line EL (see Figure 3 ) to which an emission control signal EM is supplied.

[0159] The gate electrode layer GAT can be directly connected to a gate driving circuit 120 (see Figure 1 ).

[0160] The semiconductor layer ACT can constitute a semiconductor layer of each of the first to fifth transistors T1 to T5. The semiconductor layer ACT can include a channel region positioned in an area where the semiconductor layer ACT overlaps (e.g., overlaps in a vertical direction) the gate electrode layer GAT. The semiconductor layer ACT can include a drain region and a source region positioned adjacent to the channel region.

[0161] The semiconductor layer ACT of the third transistor T3 and the semiconductor layer ACT of the fourth transistor T4 can be connected to each other (e.g., integrally formed).

[0162] The first transistor T1 can include a first (1_1) transistor T1_1 and a second (1_2) transistor T1_2. The first (1_1) transistor T1_1 and the second (1_2) transistor T1_2 can share the semiconductor layer ACT and the gate electrode layer GAT with each other. Accordingly, the first transistor T1 has the same effect as the length of the channel region is elongated in the semiconductor layer ACT. However, embodiments of the disclosure are not limited to the above-described embodiments, and the first transistor T1 can include one transistor.

[0163] The gate electrode layer GAT can be connected to each other in the first sub-pixel SPij and the second sub-pixel SPi(j+1) disposed adjacent to each other in the first direction DR1. Referring to Figure 9 , the gate electrodes of the second to fifth transistors T2 to T5 adjacent to each other in the first direction DR1 can be connected to each other as the gate electrode layer GAT.

[0164] The body electrode BODY of the first transistor T1 can be positioned between two sub-pixels adjacent to each other. The body electrode BODY can include the semiconductor layer ACT.

[0165] The at least part of the gate electrode layer GAT positioned at one side of the body electrode BODY (e.g., the side away from the body electrode BODY in the first direction DR1) (e.g., the gate electrode layer GAT constituting the first transistor T1) can protrude toward the body electrode BODY. However, embodiments of the present disclosure are not limited thereto. For example, the gate electrode layer GAT constituting the first transistor T1 can have a quadrangular shape without any part protruding toward the body electrode BODY.

[0166] The first scan signal GW can be input to the gate electrode layer GAT of the second transistor T2. The third scan signal GC can be input to the gate electrode layer GAT of the third transistor T3. The second scan signal GR can be input to the gate electrode layer GAT of the fourth transistor T4. The emission control signal EM can be input to the gate electrode layer GAT of the fifth transistor T5.

[0167] Figure 10 is a view illustrating a semiconductor layer ACT, a gate electrode layer GAT, a first contact part CNT1, and a first metal layer M1 of a sub-pixel according to other embodiments of the present disclosure.

[0168] An interlayer insulating layer ILD can be formed on the gate electrode layer GAT. The first metal layer M1 can be formed on the interlayer insulating layer ILD. In a region in which at least part of the interlayer insulating layer ILD is removed, the first metal layer M1 can be connected to (e.g., contact) the gate electrode layer GAT or the semiconductor layer ACT. Referring to Figure 10 At the first contact part CNT1, the gate electrode layer GAT and the first metal layer M1 can be connected to each other. Optionally, at the first contact part CNT1 included in the interlayer insulating layer ILD, the semiconductor layer ACT and the first metal layer M1 can be connected to each other.

[0169] The first metal layer M1 can constitute the second node NODE2. The first metal layer M1 can be connected to the semiconductor layers ACT of the third transistor T3 (see Figure 9 ) and the fourth transistor T4 (see Figure 9 ). The first metal layer M1 can be connected to the gate electrode layer GAT of the first transistor T1 (see Figure 9 ). For example, the first metal layer M1 can be connected to a drain region formed in the semiconductor layers ACT of the third transistor T3 and the fourth transistor T4.

[0170] The first power voltage VDD can be applied to the first metal layer M1. The first power voltage VDD can be applied to a source region in the active layer ACT of the first transistor T1 (see Figure 9 ) through the metal layer M1. The first power voltage VDD can be applied to the first electrode E1 of the first capacitor C1 through the metal layer M1.

[0171] With Figure 5 reference to Figure 10 , the first scan signal GW, the second scan signal GR, and the third scan signal GC, and the emission control signal EM can not be input through the first metal layer M1. With Figure 9 reference to Figure 10 , the first capacitor C1 can be formed in an area overlapping the gate electrode layer GAT of the first transistor T1 to the fifth transistor T5. The first metal layer M1 constituting the second node NODE2 can be positioned while overlapping the gate electrode layer GAT of the first transistor T1 to the fifth transistor T5. The first metal layer M1 to which the first power supply voltage VDD is applied can be positioned while overlapping the gate electrode layer GAT of the first transistor T1 to the fifth transistor T5.

[0172] To increase the storage capacitance of the first capacitor C1, the first metal layer M1 constituting the first capacitor C1 can have a branched structure in which the first metal layer M1 constituting each electrode extends along a first direction. The metal layer M1 constituting the first electrode E1 of the first capacitor C1 can be interleaved with the second electrode E2 of the first capacitor C1 along a second direction DR2.

[0173] The first metal layer M1 can deliver the data signal VDATA. The data signal VDATA can be input to a drain region in the semiconductor layer ACT of the second transistor T2 (see Figure 9 ).

[0174] The first metal layer M1 can constitute the first node NODE1. With Figure 9 reference to the first metal layer M1 connected to a drain region in the semiconductor layer ACT of the first transistor T1 through the first contact portion CNT1 can constitute the first node NODE1.

[0175] The first metal layer M1 can constitute the body electrode BODY (see Figure 9 ). The first metal layer M1 can be connected to the semiconductor layer ACT constituting the body electrode BODY through the first contact portion CNT1 on the semiconductor layer ACT.

[0176] Second to fourth metal layers can be further formed on the first metal layer M1. The second to fourth metal layers can be formed identically or similarly to the second to fourth metal layers M2 to M4 described above with reference to Figures 6 to 8 .

[0177] With Figure 9 and Figure 10 reference to, the capacitance of the first capacitor C1 according to embodiments of the disclosure can be further increased.

[0178] Figure 11 is a diagramFigure 1 a plan view of the display panel 110 shown in FIG. 1A.

[0179] Figure 11 The display panel DP shown in FIG. 1A can be applied to Figure 1 the display panel 110 shown in FIG. 1A.

[0180] Referring to Figure 11 , the display panel DP can include a display area DA and a non-display area NDA. The display panel DP can display an image through the display area DA. The non-display area NDA can be disposed at a periphery of the display area DA (e.g., in a bezel area).

[0181] The display panel DP can include a substrate SUB, a plurality of sub-pixels SP disposed (or formed) on the substrate SUB, and a plurality of pads PD disposed (or formed) on the substrate SUB.

[0182] When the display panel DP according to the embodiments of the disclosure is used as a display screen of a head-mounted display (HMD) device, a virtual reality (VR) device, a mixed reality (MR) device, an augmented reality (AR) device, or the like, the display panel DP can be positioned very close to a user's eyes. In the above-described embodiments, it can be necessary to integrate the sub-pixels SP at a relatively high density. To increase the integration of the sub-pixels SP, the substrate SUB according to the embodiments of the disclosure can be provided as a silicon substrate. The sub-pixels SP and / or the display panel DP can be formed on the substrate SUB as a silicon substrate. The display device 100 (see FIG. 1A) including the display panel DP formed on the substrate SUB as a silicon substrate can be referred to as an OLED on silicon (OLEDoS) display device. Figure 1

[0183] The plurality of sub-pixels SP can be disposed in the display area DA on the substrate SUB. Referring to Figure 11 , the sub-pixels SP can be arranged in a matrix form along a first direction DR1 and a second direction DR2 intersecting the first direction DR1. However, the embodiments of the disclosure are not limited thereto. For example, the plurality of sub-pixels SP according to the embodiments of the disclosure can be arranged in a zigzag form along the first direction DR1 and the second direction DR2. For example, the plurality of sub-pixels SP can be disposed in a form. The first direction DR1 can be a row direction, and the second direction DR2 can be a column direction. Two or more sub-pixels of the plurality of sub-pixels SP can constitute one pixel PXL.

[0184] Components for controlling the sub-pixels SP can be disposed in the non-display area NDA on the substrate SUB. For example, such as Figure 1 ​The signal lines shown, from the first gate line GL1 to the m-th gate line GLm and from the first data line DL1 to the n-th data line DLn, can be configured to extend to at least a portion of the non-display area NDA.

[0185] Figure 1 At least one of the gate drive circuit 120, data driver 130, voltage generator 140, controller 150 and temperature sensor 160 shown may be configured (e.g., configured to be integrated) in the non-display area NDA of the display panel DP.

[0186] In an embodiment, Figure 1 The gate drive circuit 120 shown can be formed and disposed in the non-display area NDA of the display panel DP. In another embodiment, the gate drive circuit 120 can be implemented as a separate integrated circuit and mounted in the non-display area NDA.

[0187] In an embodiment, Figure 1 The temperature sensor 160 shown can be disposed in the non-display area NDA to sense the temperature of the display panel DP. The temperature sensor 160 can be disposed at the vertex or in the corresponding area. Two or more temperature sensors 160 can be disposed in the display panel DP.

[0188] The pad PD can be positioned on the substrate SUB within the non-display area NDA. The pad PD can be electrically connected to the sub-pixel SP via signal lines. For example, the pad PD can be connected to the sub-pixel SP via first data lines DL1 to nth data lines DLn.

[0189] The display panel DP can be connected to the display device 100 via pad PD (see...). Figure 1 Other components. In an embodiment, the voltages and signals required for the operation of components included in the display panel DP can be obtained from the pads PD via... Figure 1 The driver integrated circuit DIC shown is provided. For example, the first data line DL1 to the nth data line DLn (see...) Figure 1 The device can be connected to the driver integrated circuit (DIC) via pad PD. For example, the first power supply voltage VDD and the second power supply voltage VSS (see...) Figure 1 The gate can receive data from the driver integrated circuit DIC via the pad PD. In the gate drive circuit 120 (see...) Figure 1 In an embodiment where the device is installed in the display panel DP, the gate control signal GCS can be transmitted from the driver integrated circuit DIC to the gate drive circuit 120 via the pad PD.

[0190] In an embodiment, the circuit board can be electrically connected to the pad PD using a conductive adhesive member such as an anisotropic conductive film. The circuit board can be a flexible printed circuit board (FPCB) or a flexible film having a flexible material. A driver integrated circuit DIC (see Figure 12 ) can be mounted on the circuit board to be electrically connected to the pad PD.

[0191] In an embodiment, the display area DA can have various shapes. For example, the display area DA can have a closed-loop shape including straight sides and / or curved sides. For example, the display area DA can have a shape such as a polygonal shape, a circular shape, a semi-circular shape, and an elliptical shape.

[0192] In an embodiment, the display panel DP can have a flat display surface. In other embodiments, the display panel DP can at least partially have a rounded display surface. In an embodiment, the display panel DP can be bendable, foldable, or rollable. The display panel DP and / or the substrate SUB can include a rigid material or a flexible material.

[0193] Figure 11 is an exploded perspective view showing a portion of the display panel DP shown in Figure 12 .

[0194] In Figure 11 , for the sake of clear and brief description, a portion of the display panel DP is schematically shown, which corresponds to a first pixel PXL1 and a second pixel PXL2 among the pixels PXL shown in Figure 11 . Portions of the display panel DP corresponding to other pixels can also have the same structure as the first pixel PXL1 and the second pixel PXL2.

[0195] Referring to Figure 12 and Figure 12 , the first pixel PXL1 and the second pixel PXL2 can be disposed adjacent to each other in a second direction DR2. Each of the first pixel PXL1 and the second pixel PXL2 can include a plurality of sub-pixels. Referring to Figure 12 , each of the first pixel PXL1 and the second pixel PXL2 can include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. However, embodiments of the disclosure are not limited thereto. For example, each of the first pixel PXL1 and the second pixel PXL2 can include four sub-pixels or include two sub-pixels.

[0196] In Figures 4 to 10In the embodiment, it is shown that the first to third sub-pixels SP1 to SP3 can have a quadrangular shape and have the same size when viewed in a third direction DR3 intersecting (e.g., perpendicular to) the first direction DR1 and the second direction DR2. However, embodiments of the present disclosure are not limited thereto. The first to third sub-pixels SP1 to SP3 can be modified to have various shapes.

[0197] The display panel DP can include a substrate SUB, a pixel circuit layer PCL, a light emitting element layer LDL, a thin film encapsulation layer TFE, an optical function layer OFL, an overcoat layer OC, and a cover window CW.

[0198] In an embodiment, the substrate SUB can include a silicon wafer substrate formed using a semiconductor process. The substrate SUB can include a semiconductor material suitable for forming circuit elements. For example, the semiconductor material can include silicon, germanium, and / or silicon germanium. The substrate SUB can be provided by a bulk wafer, an epitaxial layer, a silicon-on-insulator (SOI) layer, or a semiconductor-on-insulator (SeOI) layer, etc. In other embodiments, the substrate SUB can include a glass substrate. In other embodiments, the substrate SUB can include a polyimide (PI) substrate.

[0199] The pixel circuit layer PCL can be disposed on the substrate SUB. The substrate SUB and / or the pixel circuit layer PCL can include insulating layers and conductive patterns disposed between the insulating layers. The conductive patterns of the pixel circuit layer PCL can be used as at least some of circuit elements and lines, etc. The conductive patterns can include copper, but embodiments of the present disclosure are not limited thereto. The pixel circuit layer PCL can include a gate insulating layer (not shown), an interlayer insulating layer ILD, a gate electrode layer GAT, first to fourth metal layers M1 to M4, and first to third via layers VIA1 to VIA3, which are described above with reference to FIGS. 2A and 2B. Figure 2 are described above with reference to FIGS. 2A and 2B.

[0200] The circuit elements can include sub-pixel circuits SPC (see FIG. 2A) of each of the first to third sub-pixels SP1 to SP3. Figure 2). The sub-pixel circuit SPC can include at least two transistors and at least one capacitor. Each transistor can include a semiconductor portion including a source region, a drain region, and a channel region, and a gate electrode overlapping the semiconductor portion (e.g., the channel region of the semiconductor portion). In an embodiment in which the substrate SUB is provided as a silicon substrate, the semiconductor portion can be included in the substrate SUB, and the gate electrode can be included in the pixel circuit layer PCL as a conductive pattern of the pixel circuit layer PCL. In an embodiment in which the substrate SUB is provided as a glass substrate or a PI substrate, the semiconductor portion and the gate electrode can be included in the pixel circuit layer PCL. The capacitor can include electrodes spaced apart from each other (e.g., facing each other). For example, each capacitor can include electrodes spaced apart from each other in the third direction DR3, with an insulating layer interposed between the electrodes spaced apart from each other.

[0201] The lines of the pixel circuit layer PCL can include signal lines connected to each of the first to third sub-pixels SP1 to SP3, e.g., gate lines, emission control lines, and data lines, etc. These lines can also include lines connected to the first power supply voltage node VDDN shown in FIG. 1A. These lines can also include lines connected to the second power supply voltage node VSSN shown in FIG. 1A. Figure 2 Figure 2 The lines of the pixel circuit layer PCL can include signal lines connected to each of the first to third sub-pixels SP1 to SP3, e.g., gate lines, emission control lines, and data lines, etc. These lines can also include lines connected to the first power supply voltage node VDDN shown in FIG. 1A. These lines can also include lines connected to the second power supply voltage node VSSN shown in FIG. 1A.

[0202] The light-emitting element layer LDL can include anode electrodes AE, a pixel definition layer PDL, light-emitting structures EMS, and cathode electrodes CE.

[0203] The anode electrodes AE can be disposed on the pixel circuit layer PCL. The anode electrodes AE can be connected to (e.g., contact) circuit elements of the pixel circuit layer PCL. The anode electrodes AE can include an opaque conductive material capable of reflecting light. However, embodiments of the present disclosure are not limited thereto. In an embodiment, the anode electrodes AE can include at least one of a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium gallium zinc oxide (IGZO), and indium tin zinc oxide (ITZO). However, the material of the anode electrodes AE is not limited thereto. For example, the anode electrodes AE can include titanium nitride.

[0204] The pixel definition layer PDL can be disposed on the anode electrodes AE. The pixel definition layer PDL can include openings OP exposing at least a portion of each of the anode electrodes AE. The openings OP of the pixel definition layer PDL can correspond to an emission region of each of the first to third sub-pixels SP1 to SP3.

[0205] ​In an embodiment, the pixel definition layer PDL can include an inorganic material. In the above-described embodiment, the pixel definition layer PDL can include an inorganic layer (e.g., a plurality of stacked inorganic layers). For example, the pixel definition layer PDL can include silicon oxide (SiO x ) and / or silicon nitride (SiN x ). In other embodiments, the pixel definition layer PDL can include an organic layer including an organic material. However, the material constituting the pixel definition layer PDL according to an embodiment of the disclosure is not limited as described above.

[0206] The light emitting structure EMS can be disposed on the anode electrode AE exposed by the opening OP of the pixel definition layer PDL. The light emitting structure EMS can include at least one functional layer. The light emitting structure EMS can include, for example, a functional layer such as a light generating layer (or a light emitting layer) configured to generate light (not shown), an electron transport layer configured to transport electrons, and a hole transport layer configured to transport holes.

[0207] In an embodiment, the light emitting structure EMS can at least partially fill the opening OP of the pixel definition layer PDL. In an embodiment, the light emitting structure EMS can be completely disposed on top of the pixel definition layer PDL. For example, the light emitting structure EMS can extend throughout the first to third sub-pixels SP1 to SP3. In the above-described embodiment, at least some of the functional layers in the light emitting structure EMS can be cut off or bent at the boundaries between the first to third sub-pixels SP1 to SP3. However, embodiments of the disclosure are not limited thereto. For example, portions of the light emitting structure EMS corresponding to the first to third sub-pixels SP1 to SP3 can be separated from each other, and each of the portions can be disposed in the opening OP of the pixel definition layer PDL.

[0208] The cathode electrode CE can be disposed on the light emitting structure EMS. The cathode electrode CE can extend throughout the first to third sub-pixels SP1 to SP3. The cathode electrode CE can be provided as a common electrode commonly connected to the first to third sub-pixels SP1 to SP3.

[0209] The cathode electrode CE can have light transmittance. For example, the cathode electrode CE can be a thin metal layer having a thickness to the extent that light emitted from the light emitting structure EMS can be transmitted therethrough. The cathode electrode CE can be formed of a metal material to have a relatively thin thickness, or formed of a conductive material having light transmittance. In an embodiment, the cathode electrode CE can include at least one of various transparent conductive materials including indium tin oxide, indium zinc oxide, indium tin zinc oxide, aluminum zinc oxide, gallium zinc oxide, zinc tin oxide, and gallium tin oxide. However, the material constituting the cathode electrode CE according to an embodiment of the disclosure is not limited as described above. The cathode electrode CE can function as a semi-reflective mirror that allows light emitted from the light emitting structure EMS to be partially transmitted therethrough and allows light emitted from the light emitting structure EMS to be partially reflected therefrom.

[0210] It can be appreciated that any one of the anode electrodes AE, a portion of the light emitting structure EMS, and a portion of the cathode electrode CE, which overlap each other, constitute one light emitting element LD (see FIG. 1B). Figure 13 Each of the light emitting elements LD of the first to third sub-pixels SP1 to SP3 can include one anode electrode AE, a portion of the light emitting structure EMS, and a portion of the cathode electrode CE, which overlap each other. In each of the first to third sub-pixels SP1 to SP3, holes injected from the anode electrode AE and electrons injected from the cathode electrode CE can be transported into the light emitting structure EMS to form an exciton, and light can be generated when the exciton transitions from an excited state to a ground state. The brightness of the light can be determined according to the amount of current flowing through the light emitting structure EMS. The wavelength band of the generated light can be determined according to the configuration of the light emitting structure EMS.

[0211] A thin film encapsulation layer TFE can be disposed on the cathode electrode CE. The thin film encapsulation layer TFE can cover the light emitting element layer LDL and / or the pixel circuit layer PCL. The thin film encapsulation layer TFE can prevent oxygen and / or moisture from penetrating into the light emitting element layer LDL. In an embodiment, the thin film encapsulation layer TFE can include a structure in which at least one inorganic layer and at least one organic layer are alternately stacked. For example, the inorganic layer can include silicon nitride, silicon oxide, or silicon oxynitride (SiOxNy, where 0 < x < 2 and 0 < y < 2), etc. For example, the organic layer can include an organic insulating material such as an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polystyrene resin, a polyphenylene sulfide resin, or benzocyclobutene (BCB). However, the materials of the organic layer and the inorganic layer of the thin film encapsulation layer TFE are not limited as described above. x N y ) etc. For example, the organic layer can include an organic insulating material such as an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polystyrene resin, a polyphenylene sulfide resin, or benzocyclobutene (BCB). However, the materials of the organic layer and the inorganic layer of the thin film encapsulation layer TFE are not limited as described above.

[0212] In order to improve the encapsulation efficiency of the thin film encapsulation layer TFE, the thin film encapsulation layer TFE can further include an inorganic layer including aluminum oxide (AlO xA thin film including aluminum oxide can be positioned on a top surface of the thin film encapsulation layer TFE facing the optical functional layer OFL and / or a bottom surface of the thin film encapsulation layer TFE facing the light emitting device layer LDL. The thin film including aluminum oxide can be formed by an atomic layer deposition (ALD) process. However, embodiments of the present disclosure are not limited thereto. The thin film encapsulation layer TFE can further include a thin film formed of at least one of various materials suitable for improving encapsulation efficiency.

[0213] An optical functional layer OFL can be disposed on the thin film encapsulation layer TFE. The optical functional layer OFL can include a color filter layer CFL and a lens array LA. In an embodiment, the optical functional layer OFL can be attached to the thin film encapsulation layer TFE by an adhesive layer (not shown). For example, the optical functional layer OFL can be separately manufactured to be attached to the thin film encapsulation layer TFE by the adhesive layer. The adhesive layer can also perform a function of protecting lower layers including the thin film encapsulation layer TFE disposed under the adhesive layer.

[0214] A color filter layer CFL can be disposed between the thin film encapsulation layer TFE and the lens array LA. The color filter layer CFL can filter light emitted from the light emitting structure EMS, thereby selectively outputting light having a wavelength band corresponding to each sub-pixel. The color filter layer CFL can include color filters CF respectively corresponding to the first to third sub-pixels SP1 to SP3. Each of the color filters CF can allow light having a wavelength band corresponding to a corresponding sub-pixel to pass therethrough. For example, a color filter corresponding to the first sub-pixel SP1 can allow red light to pass therethrough, a color filter corresponding to the second sub-pixel SP2 can allow green light to pass therethrough, and a color filter corresponding to the third sub-pixel SP3 can allow blue light to pass therethrough. At least some of the color filters CF can be omitted according to light emitted from the light emitting structure EMS in each sub-pixel. In some embodiments, the color filter layer CFL can be omitted. In an embodiment, the color filters CF can overlap (e.g., partially overlap) with each other in a boundary region between the first to third sub-pixels SP1 to SP3. In other embodiments, the color filters CF can be spaced apart from each other in the boundary region between the first to third sub-pixels SP1 to SP3, and a black matrix can be provided between the color filters CF.

[0215] A lens array LA can be disposed on the color filter layer CFL. The lens array LA can include lenses LS respectively corresponding to the first to third sub-pixels SP1 to SP3. Each of the lenses LS can output light emitted from the light emitting structure EMS along an intended path, thereby improving light emitting efficiency. In an embodiment, the lenses can include an organic material. In an embodiment, the lenses LS can include an acrylic material. However, the material of the lenses LS is not limited thereto.

[0216] In an embodiment, at least some of the color filters CF and / or at least some of the lenses LS can not be aligned with the openings OP in the pixel definition layer PDL. For example, at least some of the color filters CF of the color filter layer CFL and at least some of the lenses LS of the lens array LA can be shifted in any one direction parallel to the plane defined by the first direction DR1 and the second direction DR2.

[0217] Specifically, in the central region of the display region DA, the center of the color filter CF and the center of the lens LS can be aligned with or overlap the center of the corresponding opening OP of the pixel definition layer PDL when viewed in the third direction DR3. For example, in the central region of the display region DA, the opening OP of the pixel definition layer PDL can completely overlap the corresponding color filter CF of the color filter layer CFL and the corresponding lens LS of the lens array LA. In the region of the display region DA adjacent to the non-display region NDA, the center of the color filter CF and the center of the lens LS can be shifted from the center of the opening OP of the pixel definition layer PDL when viewed in the third direction DR3. For example, in the region of the display region DA adjacent to the non-display region NDA, the opening OP of the pixel definition layer PDL can partially overlap the corresponding color filter CF of the color filter layer CFL and the corresponding lens LS of the lens array LA. Thus, at the center of the display region DA, light emitted from the light emitting structure EMS can be effectively output in the normal direction of the display surface. At the outer portion of the display region DA, light emitted from the light emitting structure EMS can be effectively output in a direction inclined by a predetermined angle with respect to the normal direction.

[0218] An overcoat layer OC can be disposed on the lens array LA. The overcoat layer OC can cover the optical function layer OFL, the thin film encapsulation layer TFE, the light emitting structure EMS, and / or the pixel circuit layer PCL. The overcoat layer OC can include various materials suitable for protecting the layers disposed under the overcoat layer OC from foreign substances such as dust and moisture.

[0219] A cover window CW can be disposed on the overcoat layer OC. The cover window CW can protect the lower layer disposed under the cover window CW. In some embodiments, the cover window CW can include glass and metal, etc. having light transmittance. However, embodiments of the disclosure are not limited thereto.

[0220] Figure 12 is a plan view showing an embodiment of any one of the pixels shown in Figure 13

[0221] In Figure 12 , for the sake of clear and brief description, the Figure 11 ​The first pixel PXL1 among the first pixel PXL1 and the second pixel PXL2 shown in FIG. 1A can include a first sub-pixel SP1 to a third sub-pixel SP3 arranged in a first direction DR1. Other pixels can have the same structure as the first pixel PXL1. The first pixel PXL1 can include the first sub-pixel SP1 to the third sub-pixel SP3 arranged in the first direction DR1.

[0222] The first sub-pixel SP1 can include a first emission area EMA1 and a non-emission area NEA at a periphery of the first emission area EMA1. The second sub-pixel SP2 can include a second emission area EMA2 and a non-emission area at a periphery of the second emission area EMA2. The third sub-pixel SP3 can include a third emission area EMA3 and a non-emission area at a periphery of the third emission area EMA3.

[0223] The first emission area EMA1 can be an area in which light is emitted from a light emitting structure EMS (see FIG. 1B) corresponding to the first sub-pixel SP1. The second emission area EMA2 can be an area in which light is emitted from the light emitting structure EMS corresponding to the second sub-pixel SP2. The third emission area EMA3 can be an area in which light is emitted from the light emitting structure EMS corresponding to the third sub-pixel SP3. As described with reference to FIG. 1B, each emission area can be understood as an opening OP of the pixel defining layer PDL corresponding to each of the first sub-pixel SP1 to the third sub-pixel SP3. Figure 12 Figure 14

[0224] Figure 14 is a diagram illustrating an embodiment of a display system 1400 according to an embodiment of the disclosure.

[0225] Referring to Figure 14 , the display system 1400 can include a processor 1410 and one or more display devices 1420 and 1430.

[0226] The processor 1410 can perform various tasks and various calculations. In an embodiment, the processor 1410 can include an application processor (AP), a graphics processing unit (GPU), a microprocessor, and a central processing unit (CPU), etc. The processor 1410 can be connected to other components of the display system 1400 through a bus to control the components of the display system 1400.

[0227] In Figure 1 , it is shown that the display system 1400 includes a first display device 1420 and a second display device 1430. The processor 1410 can be connected to the first display device 1420 through a first channel CH1 and to the second display device 1430 through a second channel CH2.

[0228] ​​Through the first channel CH1, the processor 1410 can transmit the first image data IMG1 and the first control signal CTRL1 to the first display device 1420. The first display device 1420 can display an image based on the first image data IMG1 and the first control signal CTRL1. The first display device 1420 can be the same as the display device 100 described with reference to Figure 1 The first image data IMG1 and the first control signal CTRL1 can be provided as the input image data IMG and the control signal CTRL shown in FIG. 1, respectively. Figure 1

[0229] Through the second channel CH2, the processor 1410 can transmit the second image data IMG2 and the second control signal CTRL2 to the second display device 1430. The second display device 1430 can display an image based on the second image data IMG2 and the second control signal CTRL2. The second display device 1430 can be the same as the display device 100 described with reference to Figure 1 The second image data IMG2 and the second control signal CTRL2 can be provided as the image data IMG and the control signal CTRL shown in FIG. 1, respectively. Figure 15

[0230] The display system 1400 can include a computing system for providing an image display function, such as a portable computer, a mobile phone, a smart phone, a tablet personal computer (PC), a smart watch, a watch phone, a portable multimedia player (PMP), a navigation system, or an ultra-mobile computer (UMPC). In addition, the display system 1400 can include at least one of a head-mounted display (HMD) device, a virtual reality (VR) device, a mixed reality (MR) device, and an augmented reality (AR) device.

[0231] Figure 14 is a perspective view showing an application example of the display system 1400 shown in FIG. 1. Figure 15

[0232] Referring to Figure 14 , Figure 14 The display system 1400 shown in FIG. 1 can be applied to a head-mounted display device 1500. The head-mounted display device 1500 can be a wearable electronic device that can be worn on a user's head.

[0233] ​​​The head-mounted display device 1500 can include a head mounting band 1510 and a display device housing case 1520. The head mounting band 1510 can be connected to the display device housing case 1520. The head mounting band 1510 can include a horizontal band and / or a vertical band for fixing the head-mounted display device 1500 to the head of the user. The horizontal band can be configured to surround a side portion of the head of the user, and the vertical band can be configured to surround an upper portion of the head of the user. However, embodiments of the present disclosure are not limited thereto. For example, the head mounting band 1510 can be implemented in the form of a spectacle frame or a helmet, etc.

[0234] The display device housing case 1520 can house the first display device 1420 and the second display device 1430 shown in FIG. 14B. Figure 14 The display device housing case 1520 can further house the processor 1410 shown in FIG. 14A. Figure 16

[0235] Figure 16 is a view showing the head-mounted display device 1500 worn by the user USR.

[0236] Referring to Figure 14 , a first display panel DP1 (see Figure 14 ) of the first display device 1420 and a second display panel DP2 (see ​ ) of the second display device 1430 can be disposed in the head-mounted display device 1500. The head-mounted display device 1500 can further include one or more lenses. For example, the head-mounted display device 1500 can include a left eye lens LLNS and a right eye lens RLNS.

[0237] In the display device housing case 1520, the right eye lens RLNS can be disposed between the first display panel DP1 and the right eye of the user USR. In the display device housing case 1520, the left eye lens LLNS can be disposed between the second display panel DP2 and the left eye of the user USR.

[0238] An image output from the first display panel DP1 can be observed by the right eye of the user USR through the right eye lens RLNS. The right eye lens RLNS can refract light emitted from the first display panel DP1 to face the right eye of the user USR. The right eye lens RLNS can perform an optical function for adjusting a viewing distance between the first display panel DP1 and the right eye of the user USR.

[0239] ​An image output from the second display panel DP2 can be observed by the left eye of the user USR through the left eye lens LLNS. The left eye lens LLNS can refract light emitted from the second display panel DP2 to face the left eye of the user USR. The left eye lens LLNS can perform an optical function for adjusting a viewing distance between the second display panel DP2 and the left eye of the user USR.

[0240] In an embodiment, each of the right eye lens RLNS and the left eye lens LLNS can include an optical lens having a flat cross-section. In an embodiment, each of the right eye lens RLNS and the left eye lens LLNS can include a multi-channel lens including sub-regions having different optical characteristics. In the above-described embodiment, each of the first display panel DP1 and the second display panel DP2 can output an image corresponding to the sub-regions of the multi-channel lens, respectively, and the output images can be observed by the user while passing through the corresponding sub-regions, respectively.

[0241] In the sub-pixel and the display apparatus including the same according to the disclosure, the capacitance of the capacitor can be increased.

[0242] Example embodiments have been disclosed herein and, although a particular terminology is employed, it is understood that the terms are used in a generic and descriptive sense only and not for purposes of limitation. In some instances, features, characteristics, and / or elements described in conjunction with a particular embodiment are not required in all embodiments. Therefore, unless otherwise specifically stated, features, characteristics, and / or elements described in conjunction with a particular embodiment can be used in any combination with features, characteristics, and / or elements described in conjunction with any other embodiment. Accordingly, one of ordinary skill in the art will recognize that the disclosure with respect to a particular embodiment can vary, without departing from the spirit and scope of the disclosure as set forth in the following claims.

Claims

1. A sub-pixel, characterized in that, The sub-pixel includes: a light emitting element; a first transistor connected between a first power supply line and a first node, the first transistor including a gate electrode connected to a second node; a second transistor connected to a data line, the second transistor including a gate electrode connected to a first sub-gate line, the second transistor receiving a data signal supplied from the data line in response to a first scan signal supplied from the first sub-gate line; a third transistor including a gate electrode connected to a third sub-gate line, the third transistor switching an electrical connection between the first node and the second node in response to a third scan signal supplied from the third sub-gate line; a fourth transistor including a gate electrode connected to a second sub-gate line, the fourth transistor switching an electrical connection between the second node and a third power supply line in response to a second scan signal supplied from the second sub-gate line; a fifth transistor including a gate electrode connected to an emission control line, the fifth transistor switching an electrical connection between the first node and the light emitting element in response to an emission control signal supplied from the emission control line; and a first capacitor including a first electrode connected to the first power supply line and a second electrode connected to the second node, wherein the second electrode is directly connected to the gate electrode of the first transistor, a semiconductor layer of the third transistor, and a semiconductor layer of the fourth transistor.

2. The sub-pixel of claim 1, wherein, The semiconductor layer of the third transistor and the semiconductor layer of the fourth transistor are integrally formed.

3. The sub-pixel of claim 1, wherein, The first sub-gate line to the third sub-gate line and the emission control line include a first metal layer extending in a first direction, and wherein each of the first electrode of the first capacitor and the second electrode of the first capacitor includes the first metal layer.

4. The sub-pixel of claim 3, wherein, The gate electrode of each of the first transistor to the fifth transistor includes a gate electrode layer, wherein an interlayer insulating layer is interposed between the gate electrode layer and the first metal layer, and wherein the first metal layer is directly connected to the gate electrode layer through a first contact portion formed in the interlayer insulating layer.

5. The sub-pixel of claim 3, wherein, The first power supply line, the third power supply line, and the data line include a second metal layer extending in a second direction intersecting the first direction, and wherein each of the first electrode of the first capacitor and the second electrode of the first capacitor includes the second metal layer.

6. The sub-pixel of claim 5, wherein, At least a portion of the second metal layer constituting the first capacitor overlaps at least a portion of the first metal layer constituting the first capacitor when viewed in plan.

7. The sub-pixel of claim 1, wherein, The gate electrode of each of the first transistor to the fifth transistor includes a gate electrode layer, and wherein the first sub-gate line to the third sub-gate line and the emission control line include the gate electrode layer extending in a first direction.

8. The sub-pixel of claim 7, wherein, Each of the first electrode of the first capacitor and the second electrode of the first capacitor includes a first metal layer, wherein an interlayer insulating layer is interposed between the first metal layer and the gate electrode layer, and The first metal layer is directly connected to the gate electrode layer through a first contact portion formed in the interlayer insulating layer.

9. A display device, characterized by comprising: The display device includes: a substrate; and a plurality of subpixels provided on the substrate, each of the plurality of subpixels including: a pixel circuit layer provided on the substrate, the pixel circuit layer having a subpixel circuit of each of the plurality of subpixels; and a light emitting element layer provided on the pixel circuit layer, the light emitting element layer having a light emitting element of each of the plurality of subpixels, wherein the pixel circuit layer includes: a semiconductor layer; a gate insulating layer provided on the semiconductor layer; a gate electrode layer provided on the gate insulating layer; an interlayer insulating layer provided on the gate electrode layer, the interlayer insulating layer including a first contact portion; and a first metal layer provided on the interlayer insulating layer, the first metal layer being directly connected to the gate electrode layer through the first contact portion, the first metal layer constituting a capacitor included in the subpixel circuit.

10. The display device according to claim 9, wherein The subpixel circuit includes: a first transistor connected between a first power supply line and a first node, the first transistor including a gate electrode connected to a second node; a second transistor connected to a data line, the second transistor including a gate electrode connected to a first subgate line, the second transistor receiving a data signal supplied from the data line in response to a first scan signal supplied from the first subgate line; a third transistor including a gate electrode connected to a third subgate line, the third transistor switching an electrical connection between the first node and the second node in response to a third scan signal supplied from the third subgate line; a fourth transistor including a gate electrode connected to a second subgate line, the fourth transistor switching an electrical connection between the second node and a third power supply line in response to a second scan signal supplied from the second subgate line; a fifth transistor including a gate electrode connected to an emission control line, the fifth transistor switching an electrical connection between the first node and the light emitting element in response to an emission control signal supplied from the emission control line; and the capacitor including a first electrode connected to the first power supply line and a second electrode connected to the second node, wherein the second electrode is directly connected to the gate electrode of the first transistor, a semiconductor layer of the third transistor, and a semiconductor layer of the fourth transistor.

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