USB interface test circuit and USB test equipment

Abstract

The utility model belongs to the technical field of USB testing, and discloses a USB interface testing circuit and USB testing equipment, and the circuit comprises a control module and M universal testing modules, the first end and the second end of each general test module are correspondingly connected with a computer through a USB socket and connected with tested equipment; the control module is respectively connected with the computer, all the universal test modules and the tested equipment; and the control module is used for controlling the general test module to be in different mode states when receiving an instruction of the computer or the tested equipment so as to carry out simulation test on the tested equipment. The universal test module is controlled to be in different mode states according to the received instruction so as to carry out various corresponding simulation tests on the tested equipment, so that multifunctional tests on the USB equipment are realized, and the test efficiency and accuracy are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of USB testing, and particularly relates to a USB interface test circuit and a USB test device. BACKGROUND

[0002] With the development of technology, the transmission speed of the Universal Serial Bus (USB) is greatly improved; meanwhile, the USB has the characteristics of power supply, plug and play, hot plug and high and low version compatibility.

[0003] However, at present, coarse-grained USB storage device read-write testing is mainly adopted, which cannot meet the requirement of product quality improvement of the USB storage device. Especially in the research and development and production testing of the USB device (for example, the USB storage device), it is difficult to test the electrical connection reliability, the robustness of the firmware program, the stability of high-frequency plug and unplug, the compatibility of the transmission protocol stack (2.0 or 3.x), and the stability of the transmission speed.

[0004] Therefore, the prior art still needs to be improved and enhanced. CONTENT OF THE INVENTION

[0005] The present application provides a USB interface test circuit and a USB test device, which aims to solve the problem that the multifunctional test cannot be realized and the test efficiency is low when the USB device is tested in the prior art.

[0006] In a first aspect, an embodiment of the present application provides a USB interface test circuit, comprising: a control module and M universal test modules;

[0007] The first end and the second end of each universal test module are connected with a computer through a USB socket and a device under test, and the control module is connected with the computer, all the universal test modules and the device under test.

[0008] The control module is used for controlling the universal test modules to be in different mode states to simulate test the device under test when receiving the instruction of the computer or the device under test.

[0009] In some embodiments, each universal test module comprises: an impedance test unit, a voltage test unit, a capacitance test unit and two pulse signal test units.

[0010] The input end and the output end of the impedance test unit, the voltage test unit and the capacitance test unit are all led out in a differential signal line mode, and the impedance test unit, the voltage test unit and the capacitance test unit are connected in sequence.

[0011] 2 pulse signal test units are respectively connected to differential signal output ends of the capacitance test unit, and differential signal input ends of the impedance test unit are connected with the USB socket; the differential signal output ends of the capacitance test unit are connected with the device under test;

[0012] The impedance test unit is used for impedance test, the voltage test unit is used for capacitive reactance test, and the pulse signal test unit is used for voltage anti-interference test.

[0013] In some embodiments, the impedance test unit comprises 2 first impedance control sub-units, N second impedance control sub-units and N third impedance control sub-units.

[0014] All the second impedance control sub-units are connected in parallel with one of the first impedance control sub-units, one end of which is connected with the USB socket as a first input end, and the other end is connected with the voltage test unit as a first output end.

[0015] All the third impedance control sub-units are connected in parallel with another of the first impedance control sub-units, one end of which is connected with the USB socket as a second input end, and the other end is connected with the voltage test unit as a second output end.

[0016] The control module is connected with all the first impedance control sub-units, all the second impedance control sub-units and all the third impedance control sub-units respectively.

[0017] Each first impedance control sub-unit is used for connecting the USB socket and the device under test when in an on state.

[0018] Each second impedance control sub-unit is used for connecting a first preset impedance in series between the first input end and the first output end to form a first parallel impedance.

[0019] Each third impedance control sub-unit is used for connecting a second preset impedance in series between the second input end and the second output end to form a second parallel impedance.

[0020] In some embodiments, the voltage test unit comprises (N+1) first voltage control sub-units and (N+1) second voltage control sub-units.

[0021] All the first voltage control sub-units are connected with a first output end of the impedance test unit, and all the second voltage control sub-units are connected with a second output end of the impedance test unit.

[0022] The first voltage control sub-unit is used for accessing a first power supply from the first output end to provide a first preset voltage.

[0023] The second voltage control sub-unit is configured to access the first power supply from the second output end to provide a second preset voltage.

[0024] In some embodiments, each pulse signal test unit comprises a pulse signal control sub-unit and a pulse signal output sub-unit, wherein the pulse signal output sub-unit is connected to the pulse signal control sub-unit and the device under test respectively.

[0025] The pulse signal control sub-unit is configured to access a second power supply for the device under test.

[0026] The pulse signal output sub-unit is configured to output the pulse signal to the device under test when the pulse signal control sub-unit is in an on state.

[0027] In some embodiments, one of the first impedance control sub-units comprises a first relay and a first switch tube, and the other of the first impedance control sub-units comprises a second relay and a second switch tube.

[0028] Each second impedance control sub-unit comprises a third relay, a third switch tube and a first current-limiting resistor, and each third impedance control sub-unit comprises a fourth relay, a fourth switch tube and a second current-limiting resistor.

[0029] The first power supply is connected in series to the coil of the first relay, the first switch tube and ground, and the contact of the first relay is connected in series between the first input end and the first output end.

[0030] The first power supply is also connected in series to the coil of the second relay, the second switch tube and ground, and the contact of the second relay is connected in series between the second input end and the second output end.

[0031] The first power supply is also connected in series to the coil of the third relay, the third switch tube and ground, and the contact of the third relay is connected in series between the first input end and the first output end after being connected in series with the first current-limiting resistor.

[0032] The first power supply is also connected in series to the coil of the fourth relay, the fourth switch tube and ground, and the contact of the fourth relay is connected in series between the second input end and the second output end after being connected in series with the second current-limiting resistor.

[0033] In some embodiments, each first voltage control sub-unit comprises a fifth switch tube and a sixth switch tube, and each second voltage control sub-unit comprises a seventh switch tube and an eighth switch tube.

[0034] The first end of the fifth switch tube is connected with the first power supply, the third pole of the fifth switch tube and the first end of the sixth switch tube are both connected with the first output end, the second poles of the fifth switch tube and the sixth switch tube are both connected with the control module, and the third pole of the sixth switch tube is grounded.

[0035] The first end of the seventh switch tube is connected with the first power supply, the third pole of the seventh switch tube and the first end of the eighth switch tube are both connected with the second output end, the second poles of the seventh switch tube and the eighth switch tube are both connected with the control module, and the third pole of the eighth switch tube is grounded.

[0036] In some embodiments, the pulse signal control subunit comprises a ninth switch tube, a tenth switch tube, a first diode and a first energy storage capacitor.

[0037] The first end and the second pole of the ninth switch tube, the second pole of the tenth switch tube and the negative pole of the first diode are all connected with the second power supply, the third pole of the ninth switch tube is connected with the positive pole of the first diode, the pulse signal output subunit and one end of the first energy storage capacitor respectively.

[0038] The first end of the tenth switch tube is connected with the third power supply and the control module respectively, the third pole of the tenth switch tube is grounded, and the other end of the first energy storage capacitor is connected with the measured device.

[0039] In some embodiments, the pulse signal output subunit comprises an eleventh switch tube, a first pull-down resistor, a second pull-down resistor, (N+1) voltage division resistors, (N+1) twelfth switch tubes, N second energy storage capacitors and N second diodes.

[0040] All the twelfth switch tubes are connected in series and are connected in parallel with all the voltage division resistors connected in series, one end of which is connected with the pulse signal control subunit and the other end is grounded, the anode and cathode of each second diode are connected with the adjacent two voltage division resistors and the first end of one twelfth switch tube and one end of one second energy storage capacitor respectively.

[0041] The first end of the eleventh switch tube is connected with one end of the first pull-down resistor and the control module respectively, the third pole of the eleventh switch tube is connected with the first end of the first twelfth switch tube and one end of the second pull-down resistor respectively, and the other end of each second energy storage capacitor, the other end of the first pull-down resistor and the other end of the second pull-down resistor are all grounded.

[0042] The embodiment of the present application provides a USB test device, comprising a PCB, wherein the PCB is provided with the USB interface test circuit as described above.

[0043] Compared with the prior art, the USB interface test circuit and the USB test device provided by the present application receive instructions of a computer or a device under test through a control module, control a universal test module to be in different mode states, and perform corresponding multiple simulation tests on the device under test, so that multifunctional tests on the USB device are realized, and the automation efficiency, the production line test coverage, the test capacity and the accuracy are effectively improved, and the manufacturing cost is reduced. BRIEF DESCRIPTION OF DRAWINGS

[0044] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly introduced as follows. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can also be obtained without creative labor on the basis of these drawings.

[0045] Figure 1 A schematic diagram of pins of a USB C socket in the USB interface test circuit provided by the present application;

[0046] Figure 2 A schematic diagram of pins of a USB C plug in the USB interface test circuit provided by the present application;

[0047] Figure 3 A frame schematic diagram of the USB interface test circuit provided by the present application;

[0048] Figure 4 A structural schematic diagram of the USB interface test circuit provided by the present application;

[0049] Figure 5 A structural schematic diagram of a universal test module in the USB interface test circuit provided by the present application;

[0050] Figure 6 A structural schematic diagram of an impedance test unit in the USB interface test circuit provided by the present application;

[0051] Figure 7 A structural schematic diagram of a voltage test unit in the USB interface test circuit provided by the present application;

[0052] Figure 8 A structural schematic diagram of a capacitance test unit in the USB interface test circuit provided by the present application;

[0053] Figure 9A structure schematic diagram of a pulse signal test unit in a USB interface test circuit provided by the application.

[0054] Reference signs: 10: USB interface test circuit; 20: control module; 30: general test module; 40: USB socket; 50: computer; 60: device under test; Dsw: first diode; C L : first energy storage capacitor; Rc3: first pull-down resistor; Rc7: second pull-down resistor; Qsw1: ninth switch tube; Qsw2: tenth switch tube; Qsw3: eleventh switch tube; KS P0 : first relay; QS P0 : first switch tube; KS M0 : second relay; QS M0 : second switch tube. DETAILED DESCRIPTION

[0055] The technical solutions in the embodiments of the application will be clearly and completely described below with reference to the drawings in the embodiments of the application. Obviously, the described embodiments are only part of the embodiments of the application, rather than all the embodiments of the application.

[0056] The components of the embodiments of the application generally described and shown in the accompanying drawings can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but only represents selected embodiments of the application. Based on the embodiments of the application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the application.

[0057] Hereinafter, the terms "include", "have", and their synonymous words used in various embodiments of the application are only intended to indicate specific features, numbers, steps, operations, elements, components, or combinations of the foregoing, and should not be understood as first excluding the presence or possibility of adding one or more other features, numbers, steps, operations, elements, components, or combinations of the foregoing. In addition, the terms "first", "second", "third", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.

[0058] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which various embodiments of the present application belong. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined in various embodiments of the present application.

[0059] As shown in the pin diagram of the USB C socket and plug, Figure 1 and 2 Gnd is the ground wire; D+ and D- are a differential pair, which can be compatible with USB 2.0; RX1- and RX1+, TX1+ and TX1-, RX2- and RX2+, TX2+ and TX2- are four differential pairs, which are used to realize the respective transmission speeds of USB 3.x, USB4; Vbus: a total of four, providing 5V-20V voltage for device charging; SBUS1 and SBUS2 are used in the Alternate Mode (Alternate Mode) and in the earphone mode; CC1 and CC2: (CC: configuration channel) mainly play a communication and configuration role; Vconn (Vin_supply refers to the power supply pin): power supply within the USB C line.

[0060] The present application provides a USB interface test circuit and a USB test device. The USB interface test circuit receives instructions of a computer or a device under test through a control module, controls a general test module to be in different mode states, and performs corresponding multiple simulation tests on the device under test, so as to realize multifunctional testing of the USB device, thereby effectively improving the automation efficiency, the production line test coverage, the testing capability and the accuracy, and also reducing the manufacturing cost.

[0061] The USB interface test circuit design scheme is described below through some specific embodiments.

[0062] Please refer to Figure 3 The embodiment of the present application provides a USB interface test circuit 10, which comprises a control module 20 and M general test modules 30.

[0063] The first end and the second end of each general test module 30 are connected with a computer 50 and a device under test 60 through a USB socket 40, and the control module 20 is connected with the computer 50, all general test modules 30 and the device under test 60.

[0064] The control module 20 is used to control the general test module 30 to be in different mode states when it receives instructions from the computer 50 or the device under test 60, so as to perform simulated tests on the device under test 60.

[0065] Please refer to Figure 4 USB interface test circuit 10 (corresponding to) Figure 4 The USB test controller in the document is based on a USB-C interface, where each differential pair of pins on the USB-C interface contains a USB interface test circuit 10. The input of the general-purpose test module 30 is connected to the USB socket 40, and then via a USB cable to the computer 50. The output of the general-purpose test module 30 is connected to the device under test 60.

[0066] Simultaneously, the control module 20 is also connected to the computer 50 via a first cable, and to the communication interface (e.g., COM port) of the USB device on the device under test 60 via a second cable. The control module 20 (e.g., MCU: Micro Control Unit) is also connected to the power management system.

[0067] The test modes include: impedance test mode, capacitance test mode, voltage test mode, and pulse signal test mode. The number of M values ​​is equal to the number of differential signal pairs of the USB-C port; for example, M = 12, meaning 12 pairs of differential signal pins. The USB interface test circuit 10 can test all pins / wires in the differential signal pairs of the USB-C port except for GND. Both the first and second cables are used to transmit control signals.

[0068] Exemplary, the testing of the device under test 60 in this application includes two modes: production testing and R&D testing. This application mainly uses production testing as an example.

[0069] During production testing, the software program on the PC (computer 50) controls the MCU (control module 20) to execute various test cases on the USB device (device under test 60) via the first signal cable. First, the computer 50 transmits a first control command to the control module 20, and the control module 20 then outputs different control signals to the general-purpose test module 30 according to the first control command.

[0070] Then, the general test module 30 controls itself to be in different mode states according to the control signal, including: impedance test mode, capacitance test mode, voltage test mode and pulse signal test mode, so as to perform corresponding simulation tests on the device under test 60.

[0071] However, in the R&D test, the USB device controls the MCU to perform various test cases through the signal line second cable, such as testing signal short circuit, open circuit, open circuit, high frequency signal injection, high voltage transient signal injection and different impedance conditions. Then, first, the second control command is transmitted to the control module 20 by the device under test 60, and the control module 20 controls the general test module 30 to be in different mode states according to the second control command to simulate the test of the device under test 60.

[0072] It can be understood that the control module 20 controls the general test module 30 to be in different mode states according to the instructions received by the computer 50 or the device under test 60 to simulate the test of the device under test 60, thereby completing the multifunctional test of the USB storage device, improving the production line test coverage, improving the automation efficiency and capacity, and reducing the manufacturing cost. At the same time, the PC interface and the USB DEVICE interface are provided, and the problem of firmware robustness test is solved.

[0073] For example, please refer to Figure 5 In one embodiment, each general test module 30 includes: an impedance test unit, a voltage test unit, a capacitance test unit, and two pulse signal test units.

[0074] The input and output ends of the impedance test unit, the voltage test unit and the capacitance test unit are connected in sequence, and the input and output ends of the impedance test unit, the voltage test unit and the capacitance test unit are connected in sequence. The two pulse signal test units are connected to the differential signal output end of the capacitance test unit (i.e. Figure 5 S_OUT+ and S_OUT- ends in the capacitance test unit, which can form a differential signal line, or be an independent signal line, a power line, and the direction is bidirectional), and the differential signal input end of the impedance test unit (i.e. Figure 5 S_IN+ and S_IN- ends in the capacitance test unit, which can form a differential signal line, or be an independent signal line, a power line, and the direction is bidirectional) is connected with the USB socket 40; and the differential signal output end of the capacitance test unit is connected with the device under test 60.

[0075] The impedance test unit is used for impedance test; the voltage test unit is used for capacitive reactance test; and the pulse signal test unit is used for voltage anti-interference test.

[0076] The input and output ends of the impedance test unit, the voltage test unit and the capacitance test unit are connected in sequence, and the input and output ends of the impedance test unit, the voltage test unit and the capacitance test unit are connected in sequence. The two pulse signal test units are connected to the differential signal output end of the capacitance test unit (i.e.

[0077] Exemplarily, in the production test, after the control module 20 receives the first control instruction, the control module 20 respectively outputs a control signal to the impedance test unit, the voltage test unit, the capacitance test unit and the two pulse signal test units according to the first control instruction.

[0078] Then, the impedance test unit controls itself to output different impedances according to the control signal to perform impedance test on the device under test 60; the voltage test unit controls itself to output different capacitive reactance according to the control signal to perform capacitive reactance test on the device under test 60; and the pulse signal test unit controls itself to be in the open state according to the control signal input by Ctrl_C 1H , Ctrl_C 1L , Ctrl_C 2H and Ctrl_C 2L , and outputs a high-voltage fast signal pulse to the device under test 60 to perform voltage anti-interference test on the device under test 60. Wherein, Ctrl_C 1H and Ctrl_C 2H are high-voltage power on control pins of the pulse signal test unit, and Ctrl_C 1L and Ctrl_C 2L are high-voltage injection control pins of the pulse signal test unit.

[0079] In other embodiments in the present application, the impedance test unit, the voltage test unit, the capacitance test unit, and the two pulse signal test units can each be a general test module 30 to perform corresponding tests.

[0080] It can be understood that the control signal output by the control module 20 controls the four types of test units in the general test module 30 to work singly or in combination to correspondingly implement single four-function tests (impedance test, voltage test, capacitance test and pulse signal test), or tests of any number of functions. The number is not limited in the present application, and can be controlled according to the test functions to be implemented. In the present application, a plurality of simulation function tests are implemented, including but not limited to impedance, capacitive reactance, short circuit, signal high level simulation, signal low level simulation, injection of steep edge high-voltage fast pulse interference signal and common mode noise tests.

[0081] For example, in one embodiment, the impedance test unit includes two first impedance control sub-units, N second impedance control sub-units and N third impedance control sub-units. Wherein, all N in the present application are natural numbers.

[0082] All the second impedance control sub-units are connected in parallel with one of the first impedance control sub-units, one end of which is connected with the USB socket 40 as the first input end, and the other end of which is connected with the voltage test unit as the first output end; all the third impedance control sub-units are connected in parallel with the other of the first impedance control sub-units, one end of which is connected with the USB socket 40 as the second input end, and the other end of which is connected with the voltage test unit as the second output end; the control module 20 is connected with all the first impedance control sub-units, all the second impedance control sub-units and all the third impedance control sub-units respectively.

[0083] Each first impedance control sub-unit is used to connect the USB socket 40 and the device under test 60 when in the on state; each second impedance control sub-unit is used to connect the first preset impedance between the first input end and the first output end to form the first parallel impedance; and each third impedance control sub-unit is used to connect the second preset impedance between the second input end and the second output end to form the second parallel impedance.

[0084] The first input end is one of the differential signal input ends of the impedance test unit (corresponding to the "IN+" pin of the impedance test unit in FIG. 2), the second input end is the other of the differential signal input ends of the impedance test unit (corresponding to the "IN-" pin of the impedance test unit in FIG. 2), the first output end is one of the differential signal output ends of the impedance test unit (corresponding to the "OUT+" pin of the impedance test unit in FIG. 2), and the second output end is the other of the differential signal output ends of the impedance test unit (corresponding to the "OUT-" pin of the impedance test unit in FIG. 2). Figure 5 Figure 5 Figure 5 Figure 5 Figure 6 In FIG. 2, the "S_IN+" end to the "S_OUT+" end of the universal test module 30 is referred to as the first differential signal line of the differential signal line, and the "S_IN-" end to the "S_OUT-" end of the universal test module 30 is referred to as the second differential signal line of the differential signal line.

[0085] For example, when performing impedance testing, the control module 20 outputs control signals to the two first impedance control sub-units, the N second impedance control sub-units and the N third impedance control sub-units respectively to control them to be in the on state in any combination according to the testing requirements, so as to form a direct connection or a first parallel impedance between the first input end and the first output end, and form a direct connection or a second parallel impedance between the second input end and the second output end. The first parallel impedance and the second parallel impedance are equal or unequal in size, i.e., the number of impedance control sub-units in normal operation between the first input end and the first output end, and between the second input end and the second output end, is equal or unequal.

[0086] ​​​​It can be understood that the control signals output by the control module 20 control two first impedance control sub-units, N second impedance control sub-units and N third impedance control sub-units respectively, and combine them to conduct under different conditions, so as to perform impedance testing on the device under test 60, thereby simulating direct-through or different impedance conditions.

[0087] For example, please see Figure 6 In one implementation, one of the first impedance control subunits includes: a first relay KS P0 and the first switching transistor QS P0 Another first impedance control subunit includes: a second relay KS M0 Second switch QS M0 Each second impedance control subunit includes: a third relay, a third switching transistor, and a first current-limiting resistor; each third impedance control subunit includes: a fourth relay, a fourth switching transistor, and a second current-limiting resistor.

[0088] First power supply (corresponding to) Figure 7 V in t +) Connect the first relay KS in series sequentially P0 The coil and the first switching transistor QS P0 Upon reaching the ground, the first relay KS P0 The contacts are connected in series between the first input terminal and the first output terminal; the first power supply is also connected in series with the second relay KS. M0 The coil and the second switching transistor QS M0 Upon reaching the ground, the second relay KS M0 The contacts are connected in series between the second input terminal and the second output terminal.

[0089] The first power supply also connects the coil of the third relay and the third switching transistor in series to ground. The contacts of the third relay are connected in series with the first current-limiting resistor and then in series between the first input terminal and the first output terminal. The first power supply also connects the coil of the fourth relay and the fourth switching transistor in series to ground. The contacts of the fourth relay are connected in series with the second current-limiting resistor and then in series between the second input terminal and the second output terminal.

[0090] Among them, all the switching tubes in this application can be triodes or field effect transistors. For example, NPN triodes or N-MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). Then, when the switching tube is a triode, its control end or the first end is the base, its input end or the second end is the collector, and its output end or the third end is the emitter; while if the switching tube is a field effect transistor, its control end or the first end is the gate, its input end or the second end is the source, and its output end or the third end is the drain. In this application, the four types of test units in all the general test modules 30 are symmetric in the upper and lower two groups. The switches within each group can be combined or combined according to a certain time sequence for control, and the upper and lower two groups can be independently controlled.

[0091] In this application, N third relays are respectively marked as KS P1 -KS Pm , N fourth relays are respectively marked as KS<0000​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​All the third switch tubes and all the fourth switch tubes are turned on. At this time, the MCU controls all the third switch tubes and all the fourth switch tubes to be turned off, i.e. all the first current-limiting resistors and all the second current-limiting resistors are disconnected, so that the first input end and the first output end of the impedance test unit are directly connected, and the second input end and the second output end are directly connected, thereby simulating a zero impedance condition.

[0094] The second control mode, the control module 20 provides a low-level control signal to the first switch tube QS P0 and the second switch tube QS M0 , so that the first switch tube QS P0 and the second switch tube QS M0 are turned off.

[0095] At the same time, the control module 20 outputs a control signal to the control end Ctrl_S Pm of the third switch tube, and then controls the third switch tube to be turned on or turned off, which corresponds to making the coil of the third relay be powered off or powered on, so that the terminals of the third relay are closed or opened, and after a plurality of resistors in the N first current-limiting resistors are connected in parallel (only one resistor can also be connected in the circuit according to the test requirement), a first parallel impedance is formed, and then the first parallel impedance is connected in series in the first differential signal line, i.e. connected in series between the first input end and the first output end of the impedance test unit, thereby simulating different impedance conditions.

[0096] Similarly, the control module 20 outputs a control signal to the control end Ctrl_S Mm of the fourth switch tube, and then controls the fourth switch tube to be turned on or turned off, which corresponds to making the coil of the fourth relay be powered off or powered on, so that the terminals of the fourth relay are closed or opened, and after a plurality of resistors in the N second current-limiting resistors are connected in parallel (similarly, only one resistor can also be connected in the circuit), a second parallel impedance is formed, and then the second parallel impedance is connected in series in the second differential signal line, i.e. connected in series between the second input end and the second output end of the impedance test unit, thereby simulating different impedance conditions.

[0097] Optionally, the first impedance control subunit further comprises (N+1) first freewheeling diodes and (N+1) second freewheeling diodes; the (N+1) first freewheeling diodes are respectively marked as D P0 -D Pn , and the (N+1) second freewheeling diodes are respectively marked as D M0 -D Mn . Wherein, one first freewheeling diode is connected in parallel with the coil of one relay, and the cathode of the first freewheeling diode is connected to the first power supply; similarly, one second freewheeling diode is connected in parallel with the coil of one relay, and the cathode of the second freewheeling diode is connected to the first power supply.

[0098] For example, in one embodiment, the voltage test unit comprises: (N+1) first voltage control sub-units and (N+1) second voltage control sub-units; all the first voltage control sub-units are connected with the first output end of the impedance test unit, and all the second voltage control sub-units are connected with the second output end of the impedance test unit.

[0099] The first voltage control sub-units are used to access the first power supply from the first output end to provide a first preset voltage; and the second voltage control sub-units are used to access the first power supply from the second output end to provide a second preset voltage.

[0100] All the first voltage control sub-units are connected on the first differential signal line, and all the second voltage control sub-units are connected on the second differential signal line. All the first voltage control sub-units and all the second voltage control sub-units are also connected with the control module 20.

[0101] Exemplarily, the control module 20 outputs control signals to each of the first voltage control sub-units and each of the second voltage control sub-units respectively, to control any multiple of the (N+1) first voltage control sub-units to be in the on state to access the first power supply and provide the first preset voltage for the device under test 60, and to control any multiple of the (N+1) second voltage control sub-units to be in the on state to access the first power supply and provide the second preset voltage for the device under test 60.

[0102] The first preset voltage and the second preset voltage can be the same or different, i.e. the voltage of the first differential signal line and the voltage of the second differential signal line can be the same or different, which is controlled according to the test requirements.

[0103] For example, please refer to Figure 8 In one embodiment, each of the first voltage control sub-units comprises: a fifth switch tube and a sixth switch tube; and each of the second voltage control sub-units comprises: a seventh switch tube and an eighth switch tube.

[0104] The first end of the fifth switch tube is connected with the first power supply, the third pole of the fifth switch tube and the first end of the sixth switch tube are both connected with the first output end, the second poles of the fifth switch tube and the sixth switch tube are both connected with the control module 20, and the third pole of the sixth switch tube is grounded.

[0105] The first end of the seventh switch tube is connected with the first power supply, the third pole of the seventh switch tube and the first end of the eighth switch tube are both connected with the second output end, the second poles of the seventh switch tube and the eighth switch tube are both connected with the control module 20, and the third pole of the eighth switch tube is grounded.

[0106] The control module 20 is connected to the control end of all the fifth switch tubes, the control end of all the sixth switch tubes, the control end of all the seventh switch tubes and the control end of all the eighth switch tubes respectively to transmit control signals.

[0107] The (N+1) fifth switch tubes are respectively marked as QH P0 in the present application. Pn The (N+1) sixth switch tubes are respectively marked as QL P0 in the present application. Pn The (N+1) seventh switch tubes are respectively marked as QL M0 in the present application. Mn The (N+1) eighth switch tubes are respectively marked as QL M0 in the present application. Mn .

[0108] The output end of each fifth switch tube is connected to the input end (second end) of one sixth switch tube, and the two diodes are connected in series between the first differential signal line. Similarly, the output end (third end) of each seventh switch tube is connected to the input end of one eighth switch tube, and the two diodes are connected in series between the second differential signal line, thereby simulating short circuit or different high voltage conditions on the line.

[0109] The control module 20 outputs control signals to the control end Ctrl_RH Pn of the fifth switch tube and the control end Ctrl_RL Pn of the sixth switch tube, thereby controlling the fifth switch tube and the sixth switch tube to be turned on or turned off at the same time, so that when any one of the first power supplies forms a first preset voltage, it is connected to the first differential signal line. Similarly, the control module 20 outputs control signals to the control end Ctrl_RH Mn of the seventh switch tube and the control end Ctrl_RL Mn of the eighth switch tube, thereby controlling the seventh switch tube and the eighth switch tube to be turned on or turned off at the same time, so that when any one of the first power supplies forms a second preset voltage, it is connected to the second differential signal line, thereby simulating short circuit or different high voltage conditions on the line.

[0110] For example, please refer to Figure 9 In one embodiment, the capacitance test unit comprises (N+1) thirteenth switch tubes, (N+1) fifth relays, (N+1) third freewheeling diodes and (N+1) first series capacitors.

[0111] The coil of each first relay KS P0 is connected in parallel with a third freewheeling diode, the anode of the third freewheeling diode is connected in series with a first switch tube QS P0 , the cathode of the third freewheeling diode is connected to the first power supply, and the first switch tube QS P0The output end of the first power supply is connected to the ground in sequence through a coil of a fifth relay and a thirteenth switch tube, one end of a contact of the fifth relay is connected to one end of a first series capacitor, the other end of the contact of the fifth relay is connected between the first input end and the first output end, and the other end of the first series capacitor is connected between the second input end and the second output end.

[0112] All the first series capacitors can have the same capacitance, different capacitances or any one of the same capacitance, which is controlled according to the test requirements. The (N+1) thirteenth switch tubes are respectively marked as QS C0 QS Cn The (N+1) fifth relays are respectively marked as K C0 K CN The (N+1) first series capacitors are respectively marked as C0-C n The (N+1) third freewheeling diodes are respectively marked as DC0-DC n .

[0113] Exemplarily, the control module 20 outputs a control signal to a control end Ctrl_C Cn of the thirteenth switch tube, and controls the thirteenth switch tube to be turned on or turned off, so that any multiple capacitors (or only one capacitor is connected to the circuit according to the test requirements) of the (N+1) first series capacitors are connected in parallel between the first differential signal line and the second differential signal line, thereby simulating different capacitive conditions.

[0114] For example, in one embodiment, each pulse signal test unit includes a pulse signal control subunit and a pulse signal output subunit, and the pulse signal output subunit is connected to the pulse signal control subunit and the device under test 60.

[0115] The pulse signal control subunit is configured to connect the device under test 60 to the second power supply, and the pulse signal output subunit is configured to output a pulse signal to the device under test 60 when the pulse signal control subunit is in a turned-on state.

[0116] The pulse signal is a nanosecond pulse control signal, which is a fast electrical signal in a very short time, and can also be referred to as a high-voltage fast pulse interference signal with steep edges, and the pulse width is in the nanosecond (ns or 10^-9 second) level.

[0117] As an example, during pulse signal testing, the control module 20 outputs control signals to the pulse signal control subunit and the pulse signal output subunit respectively, so as to control them to conduct according to the test requirements. When the pulse signal control subunit is conducted, the pulse signal output subunit outputs the pulse signal input by the control module 20 to the corresponding differential signal line to perform pulse signal testing on the device under test 60.

[0118] It can be understood that when the control signal output by the control module 20 controls the pulse signal control subunit and the pulse signal output subunit to conduct the pulse signal to the corresponding differential signal line, the pulse signal is transmitted to the device under test 60 to perform pulse signal testing, thereby simulating the pulse signal test conditions under complex electromagnetic scenarios, as well as the interference simulation test of high voltage signals.

[0119] For example, please see Figure 9 In one implementation, the pulse signal control subunit includes: a ninth switch Qsw1, a tenth switch Qsw2, a first diode Dsw, and a first energy storage capacitor C. L .

[0120] The first and second terminals of the ninth switch Qsw1, the second terminal of the tenth switch Qsw2, and the cathode of the first diode Dsw are all connected to the second power supply (corresponding to...). Figure 9 V in H + (i.e., the high-voltage power output from the power management system) is connected, and the third terminal of the ninth switch Qsw1 is connected to the positive terminal of the first diode Dsw, the pulse signal output subunit, and the first energy storage capacitor C, respectively. L One end is connected.

[0121] The first terminal of the tenth switch Qsw2 is connected to the third power supply (corresponding to...) ​ V in L + (i.e., the low-voltage power output from the power management system) is connected to the control module 20, the third terminal of the tenth switching transistor Qsw2 is grounded, and the first energy storage capacitor C L The other end is connected to the device under test 60.

[0122] Among them, the function of the ninth switch Qsw1 is to isolate the high voltage V. H+ The impact on the circuit system under test.

[0123] Exemplary example, control module 20 outputs a high-level control signal to the control terminal Ctrl_H of the tenth switch Qsw2, controlling the conduction of the tenth switch Qsw2, which in turn controls the conduction of the ninth switch Qsw1, so that the first output terminal of the first differential signal line outputs a high voltage V. H +(Second power supply).

[0124] Optionally, the pulse signal control subunit further comprises a resistor R c0 , c1 , c4 , c5 and R L ; wherein one end of the resistor R c0 is used for inputting a signal (i.e. a control signal) from the MCU to control the tenth switch tube Qsw2.

[0125] For example, in one embodiment, the pulse signal output subunit comprises an eleventh switch tube Qsw3, a first pull-down resistor Rc3, a second pull-down resistor Rc7, (N+1) voltage division resistors, (N+1) twelfth switch tubes, N second energy storage capacitors and N second diodes.

[0126] All the twelfth switch tubes are connected in series and are connected in parallel with all the voltage division resistors connected in series, one end of which is connected with the pulse signal control subunit and the other end is grounded. The anode and cathode of each second diode are respectively connected with the adjacent two voltage division resistors and the first end of a twelfth switch tube and one end of a second energy storage capacitor.

[0127] The first end of the eleventh switch tube Qsw3 is connected with one end of the first pull-down resistor Rc3 and the control module 20, respectively. The third pole of the eleventh switch tube Qsw3 is connected with the first end of the first twelfth switch tube and one end of the second pull-down resistor Rc7, respectively. The other end of each second energy storage capacitor, the other end of the first pull-down resistor Rc3 and the other end of the second pull-down resistor Rc7 are all grounded.

[0128] Among them, the (N+1) voltage division resistors are respectively marked as R d0 -R dn , and the resistances of all the voltage division resistors are the same. The (N+1) twelfth switch tubes are respectively marked as Q d 0-Q d n. The N second energy storage capacitors are respectively marked as C d1 -C dn . The N second diodes are respectively marked as D d1 -D dn .

[0129] For example, when the ninth switch tube Qsw1 and the tenth switch tube Qsw2 are both turned on, at the same time, the control module 20 outputs a high-voltage fast pulse signal (pulse signal, also a transient high-voltage signal) to the control end Ctrl_L of the eleventh switch tube Qsw3 to control the eleventh switch tube Qsw3 to be turned on momentarily and then turned off at high voltage, so as to charge and discharge the first storage capacitor, thereby causing the first output end of the first differential signal line to output a high-voltage V H+ pulse with a front edge of nanoseconds to simulate the pulse signal condition.

[0130] Optionally, the pulse signal output subunit further comprises a resistor R c2 and R c6 ; wherein one end of the resistor R c2 is also used for inputting a signal (i.e. a control signal) from the MCU to control the eleventh switch tube Qsw3.

[0131] The embodiment of the present application provides a USB test device, which comprises a PCB board, and the USB interface test circuit 10 is arranged on the PCB board. It can be understood that the options in the USB interface test circuit 10 are also applicable to the embodiment, and will not be described here again.

[0132] The above merely provides a specific implementation of the present application, but the protection scope of the present application is not limited to this. Any person skilled in the art can easily think of changes or replacements within the technical range disclosed in the present application, which should be covered in the protection scope of the present application.

Claims

1. A USB interface testing circuit, characterized in that, include: The control module and M general-purpose test modules; Each of the general test modules has its first and second ends connected to a computer via a USB socket, and also to the device under test; the control module is connected to the computer, all the general test modules, and the device under test. The control module is used to control the general testing module to be in different mode states when it receives instructions from the computer or the device under test, so as to perform simulated testing on the device under test.

2. The USB interface testing circuit according to claim 1, characterized in that, Each of the general-purpose test modules includes: an impedance test unit, a voltage test unit, a capacitance test unit, and two pulse signal test units; The input and output terminals of the impedance testing unit, the voltage testing unit, and the capacitance testing unit are all led out using differential signal lines, and the impedance testing unit, the voltage testing unit, and the capacitance testing unit are connected in sequence. The two pulse signal test units are respectively connected to the differential signal output terminal of the capacitance test unit, and the differential signal input terminal of the impedance test unit is connected to the USB socket; the differential signal output terminal of the capacitance test unit is connected to the device under test. The impedance testing unit is used to perform impedance testing; the voltage testing unit is used to perform capacitive reactance testing; and the pulse signal testing unit is used to perform voltage anti-interference testing.

3. The USB interface testing circuit according to claim 2, characterized in that, The impedance testing unit includes: 2 first impedance control subunits, N second impedance control subunits, and N third impedance control subunits; After all the second impedance control subunits are connected in parallel with one of the first impedance control subunits, one end is connected to the USB socket as the first input terminal, and the other end is connected to the voltage test unit as the first output terminal. All of the third impedance control subunits are connected in parallel with one of the first impedance control subunits, with one end serving as the second input terminal and connected to the USB socket, and the other end serving as the second output terminal and connected to the voltage test unit. The control module is connected to all the first impedance control subunits, all the second impedance control subunits and all the third impedance control subunits respectively; Each of the first impedance control subunits is used to connect the USB socket and the device under test when it is in the on state; Each of the second impedance control subunits is used to connect a first preset impedance in series between the first input terminal and the first output terminal to form a first parallel impedance; Each of the third impedance control subunits is used to connect a second preset impedance in series between the second input terminal and the second output terminal to form a second parallel impedance.

4. The USB interface testing circuit according to claim 2, characterized in that, The voltage testing unit includes: (N+1) first voltage control subunits and (N+1) second voltage control subunits; All of the first voltage control subunits are connected to the first output terminal of the impedance test unit, and all of the second voltage control subunits are connected to the second output terminal of the impedance test unit; The first voltage control subunit is used to connect a first power supply from the first output terminal to provide a first preset voltage; The second voltage control subunit is used to connect the first power supply from the second output terminal to provide a second preset voltage.

5. The USB interface testing circuit according to claim 2, characterized in that, Each of the pulse signal test units includes: a pulse signal control subunit and a pulse signal output subunit; the pulse signal output subunit is connected to the pulse signal control subunit and the device under test, respectively. The pulse signal control subunit is used to connect the device under test to a second power supply; The pulse signal output subunit is used to output the pulse signal to the device under test when the pulse signal control subunit is in the on state.

6. The USB interface testing circuit according to claim 3, characterized in that, One of the first impedance control subunits includes: a first relay and a first switching transistor; the other first impedance control subunit includes: a second relay and a second switching transistor; Each of the second impedance control subunits includes: a third relay, a third switching transistor, and a first current-limiting resistor; each of the third impedance control subunits includes: a fourth relay, a fourth switching transistor, and a second current-limiting resistor; The first power supply is connected in series with the coil of the first relay and the first switching transistor to ground, and the contacts of the first relay are connected in series between the first input terminal and the first output terminal. The first power supply is also connected in series with the coil of the second relay and the second switching transistor to ground, and the contacts of the second relay are connected in series between the second input terminal and the second output terminal; The first power supply is also connected in series with the coil of the third relay and the third switching transistor to ground. The contacts of the third relay are connected in series with the first current-limiting resistor and then connected in series between the first input terminal and the first output terminal. The first power supply is also connected in series with the coil of the fourth relay and the fourth switching transistor to ground. The contacts of the fourth relay are connected in series with the second current-limiting resistor and then connected in series between the second input terminal and the second output terminal.

7. The USB interface testing circuit according to claim 4, characterized in that, Each of the first voltage control subunits includes: a fifth switch and a sixth switch; each of the second voltage control subunits includes: a seventh switch and an eighth switch; The first terminal of the fifth switch is connected to the first power supply, the third terminal of the fifth switch and the first terminal of the sixth switch are both connected to the first output terminal, the second terminals of the fifth switch and the sixth switch are both connected to the control module, and the third terminal of the sixth switch is grounded. The first terminal of the seventh switch is connected to the first power supply, the third terminal of the seventh switch and the first terminal of the eighth switch are both connected to the second output terminal, the second terminals of the seventh switch and the eighth switch are both connected to the control module, and the third terminal of the eighth switch is grounded.

8. The USB interface testing circuit according to claim 5, characterized in that, The pulse signal control subunit includes: a ninth switch, a tenth switch, a first diode, and a first energy storage capacitor; The first and second terminals of the ninth switch, the second terminal of the tenth switch, and the negative terminal of the first diode are all connected to the second power supply. The third terminal of the ninth switch is connected to the positive terminal of the first diode, the pulse signal output subunit, and one end of the first energy storage capacitor, respectively. The first terminal of the tenth switching transistor is connected to the third power supply and the control module, the third terminal of the tenth switching transistor is grounded, and the other terminal of the first energy storage capacitor is connected to the device under test.

9. The USB interface testing circuit according to claim 5, characterized in that, The pulse signal output subunit includes: an eleventh switching transistor, a first pull-down resistor, a second pull-down resistor, (N+1) voltage divider resistors, (N+1) twelfth switching transistors, N second energy storage capacitors, and N second diodes; All the twelfth switching transistors are connected in series and in parallel with all the voltage divider resistors connected in series. One end of each transistor is connected to the pulse signal control subunit, and the other end is grounded. The anode and cathode of each second diode are respectively connected between two adjacent voltage divider resistors, as well as the first end of one twelfth switching transistor and one end of one second energy storage capacitor. The first terminal of the eleventh switch is connected to one end of the first pull-down resistor and the control module, respectively. The third terminal of the eleventh switch is connected to the first terminal of the first twelfth switch and one end of the second pull-down resistor, respectively. The other end of each second energy storage capacitor, the other end of the first pull-down resistor and the other end of the second pull-down resistor are all grounded.

10. A USB testing device, characterized in that, It includes a PCB board, on which a USB interface test circuit as described in any one of claims 1-9 is provided.

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