Processor interconnection structure, mainboard and server
By setting up signal switchers and controllers in the processor interconnect structure, the problem of inconsistent topology in multi-CPU interconnect structures is solved, enabling flexible switching between dual-path and quad-path structures and improving server performance and resource utilization efficiency.
Patent Information
- Application Number
- CN202423285857.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-30
- Publication Date
- 2025-11-25
- Estimated Expiration
- 2034-12-30
AI Technical Summary
Existing multi-CPU interconnect architectures cannot flexibly switch between dual-socket and quad-socket architectures when topologies are inconsistent, resulting in non-reusability.
By setting up a first signal switcher and a second signal switcher, and having the controller receive the processor's presence signal to control the different interfaces of the signal switchers to conduct, the multiplexing of dual-channel and quad-channel structures can be achieved.
It enables flexible switching between dual-processor and quad-processor CPU interconnect structures within the same architecture, improving the flexibility of server performance and the efficiency of resource utilization.
Smart Images
Figure CN223598232U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of intelligent computing, and particularly relates to a processor interconnection structure, a mainboard and a server. BACKGROUND
[0002] With the increasing demand for server performance, a single central processing unit (CPU) can not be able to complete a data processing task, at which time the data processing task can be completed by interconnection between multiple CPUs.
[0003] The multiple CPU interconnection structure includes a four-way structure, a two-way structure and the like. Different multiple CPU interconnection structures cannot be reused due to inconsistent interconnection topologies. For example, if a two-way structure is to be implemented in a four-way structure, the connection topology of the four-way structure must be changed. The changed topology can implement the two-way structure, but cannot support the four-way structure. CONTENT OF THE UTILITY MODEL
[0004] The present application provides a processor interconnection structure, a mainboard and a server to implement reuse of a two-way and a four-way in a multiple CPU interconnection structure.
[0005] In a first aspect, the present application provides a processor interconnection structure, comprising a controller, a first processor, a second processor, a third processor, a fourth processor, a first signal switcher and a second signal switcher.
[0006] The first processor is connected to the third processor, and the second processor is connected to the fourth processor.
[0007] A first interface of the first signal switcher is connected to the first processor, a second interface of the first signal switcher is connected to a second interface of the second signal switcher, and a third interface of the first signal switcher is connected to the second processor.
[0008] A first interface of the second signal switcher is connected to the third processor, and a third interface of the second signal switcher is connected to the fourth processor.
[0009] The input of the controller is connected with the output of the first processor, the second processor, the third processor and the fourth processor, for receiving the in-place signal output by the first processor, the second processor, the third processor and the fourth processor; the output of the controller is connected with the input of the first signal switcher and the second signal switcher, for controlling the first interface and the second interface of the first signal switcher to be conductive, the first interface and the second interface of the second signal switcher to be conductive, or for controlling the first interface and the third interface of the first signal switcher to be conductive, the first interface and the third interface of the second signal switcher to be conductive. In an implementation, the controller comprises a first AND gate, a first NAND gate and a second AND gate, a third AND gate and a fourth AND gate, a first signal generator and a second signal generator;
[0010] The first processor and the third processor are connected with the input of the first AND gate, and the second processor and the fourth processor are connected with the input of the second AND gate and the input of the first NAND gate;
[0011] The output of the first AND gate is connected with the input of the third AND gate and the input of the fourth AND gate, the first NAND gate is connected with the input of the third AND gate, and the second AND gate is connected with the input of the fourth AND gate;
[0012] The output of the third AND gate is connected with the first signal generator, and the output of the fourth AND gate is connected with the second signal generator.
[0013] In an implementation, the controller comprises a fifth AND gate, a sixth AND gate, a seventh AND gate and a second NAND gate, a third signal generator and a fourth signal generator;
[0014] The first processor, the second processor, the third processor and the fourth processor are connected with the input of the fifth AND gate, the first processor and the third processor are connected with the input of the sixth AND gate, and the second processor and the fourth processor are connected with the input of the second NAND gate;
[0015] The output of the sixth AND gate and the output of the second NAND gate are connected with the seventh AND gate, the output of the seventh AND gate is connected with the input of the third signal generator, and the output of the fifth AND gate is connected with the input of the fourth signal generator.
[0016] In an implementation, the controller is a complex programmable logic device (CPLD).
[0017] In an implementation, the first signal switcher and the second signal switcher are signal switch chips MUX.
[0018] In an implementation, the first signal generator is configured to generate a first signal, and the second signal generator is configured to generate a second signal, the first signal being a low-level signal, and the second signal being a high-level signal.
[0019] In an implementation,
[0020] The first management interface of the second processor is connected with the first management interface of the fourth processor.
[0021] The first interface of the first signal switcher is connected with the second management interface of the first processor, and the third interface of the first signal switcher is connected with the second management interface of the second processor.
[0022] The first interface of the second signal switcher is connected with the second management interface of the third processor, and the third interface of the second signal switcher is connected with the second management interface of the fourth processor.
[0023] In an implementation, the first direct connection interface of the first processor is connected with the first direct connection interface of the third processor, and the first direct connection interface of the second processor is connected with the first direct connection interface of the fourth processor.
[0024] The first interface of the first signal switcher is connected with the second direct connection interface of the first processor, and the third interface of the first signal switcher is connected with the second direct connection interface of the second processor.
[0025] The first interface of the second signal switcher is connected with the second direct connection interface of the third processor, and the third interface of the second signal switcher is connected with the second direct connection interface of the fourth processor.
[0026] In a second aspect, a processor interconnection structure is provided.
[0027] In a third aspect, a server is provided, which comprises the processor interconnection structure according to the first aspect.
[0028] The processor interconnection structure, the motherboard and the server provided in the present application can multiplex the double-path structure and the four-path structure of the processor in the processor interconnection structure by setting the first signal switcher and the second signal switcher, and setting the controller which receives the in-place signal of the processor, generates different signals, and controls the conduction of the link between different interfaces of the signal switcher. BRIEF DESCRIPTION OF DRAWINGS
[0029] The accompanying drawings, which are incorporated herein and constitute part of this specification, illustrate embodiments consistent with the application and, together with the description, further serve to explain the principles of the application.
[0030] Figure 1 A structural diagram of a processor interconnection structure for an exemplary embodiment of the application;
[0031] Figure 2 A structural diagram of a dual-path structure for an exemplary embodiment of the application;
[0032] Figure 3 A structural diagram of a four-path structure for an exemplary embodiment of the application;
[0033] Figure 4 A structural diagram of interconnection between a controller and a processor for an exemplary embodiment of the application;
[0034] Figure 5 A structural diagram of interconnection between a controller and a processor for another exemplary embodiment of the application;
[0035] Figure 6 A structural diagram of a controller for an exemplary embodiment of the application.
[0036] The specific embodiments of the application have been shown by way of example in the above figures, and will be described in more detail hereafter. These figures and this written description are not intended to limit the scope of the inventive concept in any way, but rather to illustrate the inventive concept by reference to specific embodiments. DETAILED DESCRIPTION
[0037] The exemplary embodiments will be described in detail herein with reference to the attached drawings. The description of the exemplary embodiments is intended to apply to any embodiment of the application, unless specified otherwise. Accordingly, when the same, similar or like components are functionally equivalent in the different drawings, they are designated by the same reference numerals.
[0038] With the advent of the era of big data, the performance of servers is also required to be higher and higher. Through the setting of dual-path servers, four-path servers and other structures, the high-performance data processing tasks are realized, and the rational allocation of resources is realized.
[0039] In the processor interconnection structure, the signal interconnection topologies of four-path, dual-path and single-path structures are inconsistent. For example, when two CPUs are matched in the mainboard of a four-path structure to realize a dual-path result, the topology of the four-path structure must be changed, which leads to the inability to flexibly realize the switching of dual-path and four-path structures according to the requirements.
[0040] Based on this, the application provides a processor interconnection structure which can realize multiplexing of dual-path structure and four-path structure.
[0041] The technical solutions of the application and how the technical solutions solve the above technical problems will be described in detail below with specific examples. The following specific examples can be combined with each other, and the same or similar concepts or processes can not be described again in some examples. The embodiments of the application will be described below with reference to the drawings.
[0042] Reference Figure 1 The application provides a processor interconnection structure, comprising: a first processor, a second processor, a third processor, a fourth processor, a first signal switcher and a second signal switcher; the first processor is connected with the third processor, and the second processor is connected with the fourth processor; the first signal switcher is connected with the first processor, the second processor and the second signal switcher; and the second signal switcher is connected with the third processor and the fourth processor.
[0043] It can be understood that, although Figure 1 The processor interconnection structure further comprises a controller connected with the first processor, the second processor, the third processor, the fourth processor, the first signal switcher and the second signal switcher.
[0044] When any of the first processor, the second processor, the third processor and the fourth processor is powered on, an in-position signal is sent to the controller, and the controller sends a control signal to the first signal switcher and the second signal switcher according to the received in-position signal.
[0045] In some embodiments, a first interface of the first signal switcher is connected with the first processor, a second interface of the first signal switcher is connected with a second interface of the second signal switcher, and a third interface of the first signal switcher is connected with the second processor; a first interface of the second signal switcher is connected with the third processor, and a third interface of the second signal switcher is connected with the fourth processor.
[0046] The input end of the controller is connected with the output ends of the first processor, the second processor, the third processor and the fourth processor, for receiving the in-position signals output by the first processor, the second processor, the third processor and the fourth processor; and the output end of the controller is connected with the input ends of the first signal switcher and the second signal switcher, for outputting the control signal based on the in-position signal.
[0047] In some embodiments, the control signal outputted by the output terminal of the controller can control the first interface and the second interface of the first signal switcher to be conductive, the first interface and the second interface of the second signal switcher to be conductive, or control the first interface and the third interface of the first signal switcher to be conductive, the first interface and the third interface of the second signal switcher to be conductive.
[0048] In some embodiments, the controller sends a first signal to the first signal switcher and the second signal switcher after receiving the on signals of the first processor and the third processor, the first interface and the second interface of the first signal switcher are conductive when the first signal switcher receives the first signal, and the first interface and the second interface of the second signal switcher are conductive when the second signal switcher receives the first signal.
[0049] The controller sends a second signal to the first signal switcher and the second signal switcher after receiving the on signals of the first processor, the second processor, the third processor and the fourth processor, the first interface and the third interface of the first signal switcher are conductive when the first signal switcher receives the second signal, and the first interface and the third interface of the second signal switcher are conductive when the second signal switcher receives the second signal.
[0050] As shown in Figure 1 , the link connecting the first signal switcher with the second processor is called L1 link, the link connecting the second signal switcher with the fourth processor is called L2 link, and the link connecting the first signal switcher with the second signal switcher is called L3 link.
[0051] The first interface of each signal switcher is A1, the second interface of each signal switcher is A2, and the third interface of each signal switcher is A3.
[0052] The signal switcher receives the control signal outputted by the controller, and the link between A1 and A2 or the link between A1 and A3 is conductive.
[0053] The controller can realize the two-way connection or four-way connection among the first processor, the second processor, the third processor and the fourth processor in the topology as shown in Figure 1 by controlling the opening and closing of the L1 link, the L2 link and the L3 link.
[0054] In some embodiments, if the first processor and the third processor are powered on, and the second processor and / or the fourth processor are not powered on, i.e. the controller receives the on signals of the first processor and the third processor, but does not receive the on signal of the second processor or does not receive the on signal of the fourth processor or does not receive the on signals of the second processor and the fourth processor, the A1 and A2 of the first signal switcher are connected, and the A1 and A2 of the second signal switcher are connected, so that the second interface A2 of the first signal switcher is connected with the second interface A2 of the second signal switcher, the link connected with the first processor of the first signal switcher, and the link connected with the second processor of the second signal switcher are normally connected, at this time, the double-way interconnection structure between the first processor and the third processor can be realized.
[0055] After the controller receives the on signals of the first processor and the third processor, the first signal is sent to the first signal switcher and the second signal switcher, when the first signal switcher receives the first signal, the first interface and the second interface of the first signal switcher are turned on, and when the second signal switcher receives the first signal, the first interface and the second interface of the second signal switcher are turned on.
[0056] When the A1 and A2 interfaces of the first signal switcher and the second signal switcher are connected, the first signal switcher and the second signal switcher are connected through the L3 link, at this time, the signals output by the first signal switcher and the second signal switcher pass through the L3 link, and since the A1 and A3 of the first signal switcher and the second signal switcher are not turned on at this time, the signals output by the first signal switcher and the second signal switcher do not pass through the L1 and L2 links, at this time Figure 1 The third processor and the fourth processor do not participate in data calculation, i.e. the first processor and the third processor can be abstracted as the double-way structure as shown in Figure 2 It can be understood that in the double-way structure as shown in Figure 2 In the double-way structure as shown in
[0057] In some embodiments, if the first processor, the second processor, the third processor and the fourth processor are powered on, i.e. the controller receives the on signals of the first processor, the second processor, the third processor and the fourth processor, at this time, the four-way structure between the on signals of the first processor, the second processor, the third processor and the fourth processor can be realized.
[0058] The controller sends a second signal to the first signal switcher and the second signal switcher, when the first signal switcher receives the second signal, the first interface and the third interface of the first signal switcher are connected, when the second signal switcher receives the second signal, the first interface and the third interface of the second signal switcher are connected, that is, A1 and A3 of the first signal switcher are connected, A1 and A3 of the second signal switcher are connected, in this way, the link connected with the first processor, the link connected with the first processor, the link connected with the second processor, the link connected with the fourth processor, the link connected with the third processor, and the link connected with the fourth processor are normally connected, realizing four-way structure.
[0059] The controller sends a second signal to the first signal switcher and the second signal switcher, when the first signal switcher receives the second signal, the first interface A1 and the third interface A3 of the first signal switcher are connected, when the second signal switcher receives the second signal, the first interface A and the third interface A3 of the second signal switcher are connected, in the four-way structure formed by the first processor, the second processor, the third processor and the fourth processor, the first signal switcher and the second processor are connected through L1 link, the second signal switcher and the fourth processor are connected through L2 link, at this time, the signals output from the first signal switcher and the second signal switcher pass through L1 or L3 link, since A1 and A2 of the first signal switcher and the second signal switcher are not connected at this time, the signals output from the first signal switcher and the second signal switcher do not pass through L3 link, at this time, Figure 1 The structure in the above formula can be abstracted as Figure 3 The four-way structure in the above formula can be understood as Figure 3 Although not shown in the above formula, but Figure 3 In the above formula, the first signal switcher in the link connected with the first processor and the second processor is connected, and the second signal switcher in the link connected with the third processor and the fourth processor is connected.
[0060] In some embodiments, if Figure 1 In the processor interconnection structure in the above formula, only one processor is powered on, or two or three processors are powered on, but the two or three powered-on processors do not simultaneously include the first processor and the third processor, the powered-on processor can perform data processing alone, without cooperating with other processors to perform data processing, that is, a single-way structure is realized.
[0061] In some embodiments, the first signal switcher and the second signal switcher can be regarded as switches, when receiving the first signal, the link between A1 and A2 is opened, and the link between A1 and A3 is not opened, when receiving the second signal, the link between A1 and A3 is opened, and the link between A1 and A2 is not opened.
[0062] The processor interconnection structure provided in the embodiments of the present application comprises a first signal switcher and a second signal switcher, and a controller, which is configured to receive in-position signals of different processors and turn on different interfaces of the signal switchers, so as to realize a dual-channel structure and a four-channel structure in the processor interconnection structure.
[0063] In some embodiments, the controller can comprise a control gate logic circuit and a signal generator, which is configured to receive and analyze in-position signals of four processors through the control gate logic circuit, and send signals to control the first interface and the second interface of the signal switcher or the first interface and the third interface of the signal switcher to be turned on through the signal generator.
[0064] In some embodiments, as shown in Figure 4 the controller comprises a first AND gate, a first NAND gate and a second AND gate, a third AND gate and a fourth AND gate, a first signal generator and a second signal generator; the first processor and the third processor are connected to the input end of the first AND gate, the second processor and the fourth processor are connected to the input end of the second AND gate, and the second processor and the fourth processor are connected to the input end of the first NAND gate; the output end of the first AND gate is connected to the input end of the third AND gate and the input end of the fourth AND gate, the first NAND gate is connected to the input end of the third AND gate, and the second AND gate is connected to the input end of the fourth AND gate; the output end of the third AND gate is connected to the first signal generator, and the first signal generator is configured to send a first signal; the output end of the fourth AND gate is connected to the second signal generator, and the second signal generator is configured to send a second signal.
[0065] In some embodiments, the in-position signal of the processor is set to 1 when the processor is in position, and the in-position signal of the processor is set to 0 when the processor is not in position.
[0066] In an embodiment, the processor is powered on and outputs an in-position signal, and the output in-position signal is set to 1 and the non-output in-position signal is set to 0; for the first processor and the third processor, if the first processor and the third processor both output the in-position signal, the first processor and the third processor output 1, and the output of the first AND gate is also 1; if there is at least one processor among the first processor and the third processor that does not output the in-position signal, the output of the first AND gate is 0, and the outputs of the third AND gate and the fourth AND gate are also 0; the inputs of the first signal generator and the second signal generator are 0, and at this time, the first signal generator and the second signal generator do not send signals.
[0067] For the second processor and the fourth processor, if both the second processor and the fourth processor output the in-place signal, the second processor and the fourth processor output 1, the output of the second AND gate is also 1, the first NAND gate is 0, if there is at least one processor among the second processor and the fourth processor that does not output the in-place signal, the output of the first AND gate is 0, the output of the third AND gate and the fourth AND gate is also 0, and the output of the second AND gate is 0, the first NAND gate is 1.
[0068] For the first NAND gate, when there is at least one processor among the second processor and the fourth processor that does not output the in-place signal, the output of the AND gate of the first NAND gate is 0, the output of the AND gate of the first NAND gate is input to the NOT gate of the first NAND gate, and the output is 1; when both the second processor and the fourth processor output the in-place signal, the output of the AND gate of the first NAND gate is 1, the output of the AND gate of the first NAND gate is input to the NOT gate of the first NAND gate, and the output is 0.
[0069] When the output of the first AND gate is 1 and the output of the second AND gate is 1, the output of the first NAND gate is 0, the output of the third AND gate is 1, the first signal generator sends the first signal, the first interface and the second interface of the first signal switch are conductive, the first interface and the second interface of the second signal switch are conductive, and a double-path structure is realized. When the output of the first AND gate is 1 and the output of the second AND gate is 0, the output of the first NAND gate is 1, the second signal generator sends the second signal, the first interface and the third interface of the first signal switch are conductive, and the first interface and the third interface of the second signal switch are conductive, and a four-path structure is realized.
[0070] It can be understood that the first signal generator sends the first signal only when the output of the third AND gate is 1, and the first signal generator does not send the first signal when the output of the third AND gate is 0; the second signal generator sends the second signal only when the output of the fourth AND gate is 1, and the second signal generator does not send the second signal when the output of the fourth AND gate is 0.
[0071] In some embodiments, the first signal generator and the second signal generator can be one signal generator, which sends the first signal according to the input of the third AND gate and sends the second signal according to the output of the fourth AND gate. It can be understood that the third AND gate and the fourth AND gate are considered to have output only when the output is 1, and the third AND gate and the fourth AND gate cannot be 1 at the same time.
[0072] In some embodiments, the in-place signal of the processor can be set to 0 when the processor is in place, and the in-place signal is 1 when the processor is not in place. At this time, the first signal generator sends the first signal only when the output of the third AND gate is 0, and the first signal generator does not send the first signal when the output of the third AND gate is 1; the second signal generator sends the second signal only when the output of the fourth AND gate is 0, and the second signal generator does not send the second signal when the output of the fourth AND gate is 1.
[0073] In some embodiments, as shown in Figure 5 The controller includes a fifth AND gate, a sixth AND gate, a seventh AND gate, and a second NAND gate, a third signal generator and a fourth signal generator; the first processor, the second processor, the third processor and the fourth processor are connected to the input end of the fifth AND gate, the first processor and the third processor are connected to the input end of the sixth AND gate, the second processor and the fourth processor are connected to the input end of the second NAND gate; the output end of the sixth AND gate and the output end of the second NAND gate are connected to the seventh AND gate, the output end of the seventh AND gate is connected to the input end of the third signal generator, the third signal generator is used to send the first signal, the output end of the fifth AND gate is connected to the input end of the fourth signal generator, and the fourth signal generator is used to send the second signal.
[0074] In some embodiments, the first processor, the second processor, the third processor and the fourth processor are connected to the input end of the fifth AND gate, when the first processor, the second processor, the third processor and the fourth processor all output in-place signals, that is, the output of the first processor, the second processor, the third processor and the fourth processor is 1, the output of the fifth AND gate is 1, and the fourth signal generator sends the second signal, when there is at least one processor whose output is 0 among the first processor, the second processor, the third processor and the fourth processor, the output of the fifth AND gate is 0, and the fourth signal generator does not send the second signal.
[0075] In some embodiments, if the first processor and the third processor both output in-place signals, the first processor and the third processor output 1, and the output of the sixth AND gate is also 1, if there is at least one processor whose output is not in-place signal among the first processor and the third processor, the output of the sixth AND gate is 0, and the output of the seventh AND gate is also 0, and the input of the third signal generator is 0, at this time, the third signal generator does not send the first signal.
[0076] If the second processor and the fourth processor both output in-place signals, the second NAND gate is 0, if there is at least one processor whose output is not in-place signal among the second processor and the fourth processor, the second NAND gate is 1.
[0077] It can be understood that the seventh AND gate outputs 1, and the third signal generator sends the first signal, when the seventh AND gate outputs 0, the third signal generator does not send the first signal; the fifth AND gate outputs 1, and the fourth signal generator sends the second signal, when the fifth AND gate outputs 0, the fourth signal generator does not send the second signal.
[0078] When the first AND gate and the second NAND gate output 1, the fifth AND gate outputs 0, the seventh AND gate outputs 1, the third signal generator sends the first signal, and the dual-path structure is realized. The first interface and the second interface of the first signal switch are turned on, and the first interface and the second interface of the second signal switch are turned on. When the fifth AND gate outputs 1, the second NAND gate outputs 0, the fifth AND gate outputs 1, the fourth signal generator sends the second signal, the first interface and the third interface of the first signal switch are turned on, and the first interface and the third interface of the second signal switch are turned on to realize the four-path structure.
[0079] In some embodiments, the in-seat signal of the processor is set to 0 when the processor is in the seat, and the in-seat signal is set to 1 when the processor is not in the seat. At this time, the third signal generator sends the first signal only when the seventh AND gate outputs 0, and the third signal generator does not send the first signal when the seventh AND gate outputs 1. The fourth signal generator sends the second signal only when the fifth AND gate outputs 0, and the fourth signal generator does not send the second signal when the fifth AND gate outputs 1.
[0080] In some embodiments, the third signal generator and the fourth signal generator can be one signal generator, which sends the first signal according to the input of the seventh AND gate and sends the second signal according to the output of the fifth AND gate. It can be understood that the fifth AND gate or the seventh AND gate outputs 1 only to be considered as output, and the fifth AND gate and the seventh AND gate cannot be 1 at the same time.
[0081] In some embodiments, the controller includes a first OR gate and a third signal generator, the first processor, the second processor, the third processor, and the fourth processor are connected to the input end of the first OR gate, the output end of the first OR gate is connected to the third signal generator, and the in-seat signal of the processor is set to 0 when the processor is in the seat, and the in-seat signal is set to 1 when the processor is not in the seat.
[0082] At this time, different processors are powered on according to different requirements. If a dual-path structure is required, the first processor and the third processor are powered on. At this time, the outputs of the first processor and the third processor are 0, the outputs of the second processor and the fourth processor are 1, the output of the first OR gate is 1, and the third signal generator directly sends the first signal.
[0083] If a four-path structure is required, the first processor, the second processor, the third processor, and the fourth processor are powered on. At this time, the outputs of the first processor, the second processor, the third processor, and the fourth processor are 0, the output of the first OR gate is 0, and the third signal generator directly sends the second signal.
[0084] And in the four processors, if the four processors are not simultaneously on, the output of the first OR gate is 1, the first signal is sent by the third signal generator, that is, the first interface and the second interface of the signal switcher are turned on, if the first processor and the third processor are not simultaneously on at this time, a dual-path structure can be formed, if the first processor and the third processor are not simultaneously on, although the first interface and the second interface of the signal switcher are turned on, each processor separately performs data processing; only when the four processors are simultaneously on, the output of the first OR gate is 0, the second signal is sent by the third signal generator, the first interface and the third interface of the signal switcher are turned on, forming a four-path structure.
[0085] In the controller structure, the corresponding processor needs to be powered on according to the demand, if the powered-on processor is wrong, the BIOS (Basic Input / Output System) in the topology of the processor interconnection structure will not be loaded, that is, at this time, although the processor is powered on, the powered-on processor has no in-place signal, that is, the output to the first OR gate is 1, for example, in a dual-path structure, the first processor and the second processor are powered on, at this time, the BIOS in the topology of the processor interconnection structure will not be loaded, and the dual-path structure cannot be realized.
[0086] In some embodiments, the controller is a complex programmable logic device (CPLD).
[0087] As shown in Figure 6 , the CPLD has six ports, which are connected with the first processor, the second processor, the third processor, the fourth processor, the first signal switcher and the second signal switcher, the in-place signals of the first processor, the second processor, the third processor and the fourth processor are input to the CPLD through the ports connected with the CPLD, and the CPLD internal logic outputs the control signal, that is, the first signal or the second signal, to the first signal switcher and the second signal switcher through the ports connected with the first signal switcher and the second signal switcher according to the in-place signals of the processors.
[0088] In some embodiments, the first signal switcher and the second signal switcher are signal switching chips (MUX).
[0089] It can be understood that the MUX needs to meet the transmission protocol requirements between the processors.
[0090] In some embodiments, the first signal is a low-level signal, and the second signal is a high-level signal.
[0091] The first interface and the second interface of the first signal switcher are conductive when the first signal switcher receives a low-level signal, and the first interface and the second interface of the second signal switcher are conductive when the second signal switcher receives a low-level signal. At this time, the first signal switcher and the second signal switcher are considered to be directly conductive, and the signal output by the first signal switcher can directly reach the second signal switcher, and the signal output by the second signal switcher can directly reach the second signal switcher. The first interface and the third interface of the first signal switcher are conductive, and the first interface and the third interface of the second signal switcher are conductive when the first signal switcher and the second signal switcher receive a high-level signal. At this time, the first signal switcher and the second signal switcher are considered to be indirectly conductive, and the signal output by the first signal switcher can reach the second signal switcher through the second processor and the third processor, and the signal output by the second signal switcher can reach the second signal switcher through the second processor and the third processor.
[0092] In some embodiments, the first management interface of the second processor is connected with the first management interface of the fourth processor; the first interface of the first signal switcher is connected with the second management interface of the first processor, and the third interface of the first signal switcher is connected with the second management interface of the second processor; the first interface of the second signal switcher is connected with the second management interface of the third processor, and the third interface of the second signal switcher is connected with the second management interface of the fourth processor.
[0093] In some embodiments, the connection between the processors in the processor interconnection structure is realized through the management interface of each processor, the transmission speed of the management interface is less than that of the direct connection interface of the processor, the processors are connected through the management interface, and the interaction between the processors is transmitted through the management interface, so that the occupation of the bandwidth of the direct connection interface of the processor can be avoided.
[0094] As shown in Figure 1 , I1 and I2 in each processor can be considered as the first management interface and the second management interface, respectively.
[0095] In some embodiments, the first direct connection interface of the first processor is connected with the first direct connection interface of the third processor, and the first direct connection interface of the second processor is connected with the first direct connection interface of the fourth processor; the first interface of the first signal switcher is connected with the second direct connection interface of the first processor, and the third interface of the first signal switcher is connected with the second direct connection interface of the second processor; the first interface of the second signal switcher is connected with the second direct connection interface of the third processor, and the third interface of the second signal switcher is connected with the second direct connection interface of the fourth processor.
[0096] In some embodiments, the connection between the processors in the processor interconnection structure is realized through the direct connection interface of each processor.
[0097] AsFigure 1 As shown, I1 and I2 in each processor can be regarded as a first direct interface and a second direct interface, respectively.
[0098] In some embodiments, based on the processor interconnection structure of the above-mentioned embodiments, a mainboard is further provided, and the mainboard comprises the processor interconnection structure of the above-mentioned embodiments.
[0099] In some embodiments, based on the processor interconnection structure of the above-mentioned embodiments, a server is further provided, and the mainboard comprises the processor interconnection structure of the above-mentioned embodiments.
[0100] The processor can be a central processing unit (CPU), and can also be other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), etc. The general-purpose processor can be a microprocessor or any conventional processor, etc. The steps of the method disclosed in the present application can be directly embodied as execution completed by a hardware processor, or executed by a combination of hardware and software modules in the processor.
[0101] The embodiments or implementations in the specification are described in a progressive manner, and each embodiment focuses on the difference from other embodiments. The same or similar parts between the embodiments can be mutually referred to.
[0102] It should be noted that the terms “one embodiment”, “an embodiment”, “exemplary embodiment”, “some embodiments”, etc. in the specification mean that the described embodiments can include a specific feature, structure or characteristic, but not necessarily every embodiment includes the specific feature, structure or characteristic. In addition, such phrases do not necessarily refer to the same embodiment. In addition, when a specific feature, structure or characteristic is described in combination with an embodiment, it is within the knowledge of those skilled in the art to realize such feature, structure or characteristic in combination with other embodiments described explicitly or implicitly.
[0103] Generally, the terms should be understood at least partly by the use in the context. For example, at least partly according to the context, the term “one or more” used in the specification can be used to describe any feature, structure or characteristic in the singular sense, or can be used to describe a combination of features, structures or characteristics in the plural sense. Similarly, at least partly according to the context, terms such as “a” or “said” can be understood as conveying singular usage or conveying plural usage.
[0104] It should be readily understood that "on," "over," and "above" in the present disclosure are to be interpreted in the broadest context, such that "on" means not only "directly on" but also includes the meaning of "on" with intervening features or layers therebetween, and "over" or "above" includes not only the meaning of "over" or "above" but also the meaning of "over" or "above" with no intervening features or layers therebetween (i.e., directly on).
[0105] In addition, spatially relative terms, such as "beneath", "below", "lower", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
[0106] Finally, it should be noted that the above-described embodiments are merely intended for describing and illustrating, not limiting, the technical solutions of the present application; even though the present application has been described in detail with reference to the above-described embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the above-described embodiments, or equivalently replace some or all of the technical features thereof; and such modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.
Claims
1. A processor interconnect structure, characterized in that, It includes a controller, a first processor, a second processor, a third processor, a fourth processor, a first signal switcher, and a second signal switcher; The first processor is connected to the third processing unit, and the second processor is connected to the fourth processor. The first interface of the first signal switcher is connected to the first processor, the second interface of the first signal switcher is connected to the second interface of the second signal switcher, and the third interface of the first signal switcher is connected to the second processor. The first interface of the second signal switch is connected to the third processor, and the third interface of the second signal switch is connected to the fourth processor; The input terminal of the controller is connected to the output terminals of the first processor, the second processor, the third processor, and the fourth processor, and is used to receive the presence signals output by the first processor, the second processor, the third processor, and the fourth processor. The output terminal of the controller is connected to the input terminals of the first signal switch and the second signal switch, and is used to control the first interface and the second interface of the first signal switch to be turned on, and the first interface and the second interface of the second signal switch to be turned on, according to the presence signal, or to control the first interface and the third interface of the first signal switch to be turned on, and the first interface and the third interface of the second signal switch to be turned on.
2. The processor interconnect structure according to claim 1, characterized in that, The controller includes a first AND gate, a first NAND gate, a second AND gate, a third AND gate, a fourth AND gate, a first signal generator, and a second signal generator; The first processor and the third processor are both connected to the input of the first AND gate, the second processor and the fourth processor are connected to the input of the second AND gate, and the second processor and the fourth processor are connected to the input of the first NAND gate. The output of the first AND gate is connected to the input of the third AND gate and the input of the fourth AND gate; the first NAND gate is connected to the input of the third AND gate; and the second AND gate is connected to the input of the fourth AND gate. The output of the third AND gate is connected to the first signal generator, and the output of the fourth AND gate is connected to the second signal generator.
3. The processor interconnect structure according to claim 1, characterized in that, The controller includes a fifth AND gate, a sixth AND gate, a seventh AND gate, a second NAND gate, a third signal generator, and a fourth signal generator; The first processor, the second processor, the third processor, and the fourth processor are all connected to the input of the fifth AND gate; the first processor and the third processor are all connected to the input of the sixth AND gate; and the second processor and the fourth processor are connected to the input of the second NAND gate. The output of the sixth AND gate, the output of the second NAND gate, and the seventh AND gate are connected. The output of the seventh AND gate is connected to the input of the third signal generator, and the output of the fifth AND gate is connected to the input of the fourth signal generator.
4. The processor interconnect structure according to claim 1, characterized in that, The controller is a complex programmable logic device (CPLD).
5. The processor interconnect structure according to any one of claims 1-4, characterized in that, The first signal switcher and the second signal switcher are signal switching chips (MUX).
6. The processor interconnect structure according to claim 2, characterized in that, The first signal generator is used to emit a first signal, and the second signal generator is used to emit a second signal. The first signal is a low-level signal, and the second signal is a high-level signal.
7. The processor interconnect structure according to any one of claims 1-4, characterized in that, The first management interface of the first processor is connected to the first management interface of the third processor, and the first management interface of the second processor is connected to the first management interface of the fourth processor; The first interface of the first signal switcher is connected to the second management interface of the first processor, and the third interface of the first signal switcher is connected to the second management interface of the second processor. The first interface of the second signal switch is connected to the second management interface of the third processor, and the third interface of the second signal switch is connected to the second management interface of the fourth processor.
8. The processor interconnect structure according to any one of claims 1-4, characterized in that, The first direct connection port of the first processor is connected to the first direct connection port of the third processor, and the first direct connection port of the second processor is connected to the first direct connection port of the fourth processor; The first interface of the first signal switcher is connected to the second direct connection port of the first processor, and the third interface of the first signal switcher is connected to the second direct connection port of the second processor. The first interface of the second signal switcher is connected to the second direct connection port of the third processor, and the third interface of the second signal switcher is connected to the second direct connection port of the fourth processor.
9. A motherboard, characterized in that, Includes the processor interconnect structure as described in any one of claims 1-8.
10. A server, characterized in that, Includes the processor interconnect structure as described in any one of claims 1-8.