Image sensor pixel unit, signal processing device and electronic equipment

Abstract

The embodiment of the utility model discloses an image sensor pixel unit, a signal processing device and electronic equipment. The image sensor pixel unit comprises a photodiode, a charge transfer module, a reset transistor, a mode control transistor, a first output module and a second output module, one end of the photodiode is grounded, and the other end is connected with the mode control transistor and the charge transfer module; one end of the charge transfer module is connected with the photodiode, and the other end is connected with the reset transistor and the first output module; the source end of the reset transistor is connected with a power supply signal, the drain end is connected with the charge transfer module and the first output module, and the gate end receives a reset signal; the source end of the mode control transistor is connected with the other end of the photodiode, the drain end of the mode control transistor is connected with the second output module, and the grid end of the mode control transistor receives a mode control signal. According to the embodiment of the invention, the dynamic range of the image sensor is widened on the premise that the number of the photodiodes is not increased.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of sensors, and in particular to an image sensor pixel unit, a signal processing device and an electronic device. BACKGROUND

[0002] Image sensors have been widely applied in the fields of digital cameras, mobile phones, medical treatment, automobiles, unmanned aerial vehicles and machine recognition, and the rapid development of the manufacturing technology of complementary metal oxide semiconductor (CMOS) image sensors has made people have higher requirements for the output image quality of image sensors. The CMOS image sensor can be divided into two categories according to the signal acquisition mode: one mode is to set the exposure time of the pixel to measure the voltage signal change; the second mode is to set the voltage change of the pixel to measure the exposure time, and this kind of image sensor is called a pulse sequence image sensor. In the working process of the pixel, random reset noise will be brought by resetting the pixel each time, and noise and errors will also be introduced in the transmission path of the pixel signal from the pixel to the column-level circuit. CONTENT OF THE INVENTION

[0003] The present disclosure provides an image sensor pixel unit, a signal processing device and an electronic device.

[0004] In one aspect of the present disclosure, an image sensor pixel unit is provided, comprising: a photodiode, a charge transfer module, a reset transistor, a mode control transistor, a first output module and a second output module.

[0005] One end of the photodiode is grounded, and the other end is connected with the mode control transistor and the charge transfer module;

[0006] One end of the charge transfer module is connected with the photodiode, and the other end is connected with the reset transistor and the first output module;

[0007] The source end of the reset transistor is connected with a power supply signal, the drain end is connected with the charge transfer module and the first output module, and the gate end receives a reset signal;

[0008] The source end of the mode control transistor is connected with the other end of the photodiode, the drain end is connected with the second output module, and the gate end receives a mode control signal;

[0009] One end of the first output module is connected with the charge transfer module and the drain end of the reset transistor, and the other end outputs a first signal;

[0010] One end of the second output module is connected with the drain end of the mode control transistor, and the other end outputs a second signal.

[0011] Optionally, the charge transfer module comprises a first capacitor, a second capacitor, a first switch transistor and a second switch transistor.

[0012] One end of the first capacitor is grounded, and the other end is connected with the photodiode through the first switch transistor and connected with the second capacitor through the second switch transistor.

[0013] One end of the second capacitor is grounded, and the other end is connected with the drain end of the reset transistor and connected with the first capacitor through the second switch transistor.

[0014] Optionally, the first output module comprises a source follower transistor and a readout transistor.

[0015] The source end of the source follower transistor is connected with a power supply signal, the drain end is connected with the readout transistor, and the gate end is connected with the charge transfer module.

[0016] The drain end of the readout transistor is connected with the drain end of the source follower transistor, the source end outputs the first signal as a first output end of a pixel unit, and the gate end receives a row selection signal.

[0017] Optionally, the second output module comprises a comparator and a pulse readout control circuit.

[0018] The negative input end of the comparator is connected with the drain end of the mode control transistor, the positive input end receives a reference signal, and the output end is connected with the input end of the pulse readout control circuit.

[0019] The input end of the pulse readout control circuit is connected with the output end of the comparator, and the output end outputs the second signal.

[0020] Optionally, the pulse readout control circuit comprises a first logic circuit, a second logic circuit and a third switch transistor.

[0021] The first input end of the first logic circuit is connected with the output end of the comparator, the second input end of the first logic circuit receives an enable signal, the output end is connected with the second logic circuit and the gate end of the third switch transistor, and the first logic circuit outputs a third signal to the third switch transistor and the second logic circuit.

[0022] The first input end of the second logic circuit is connected with the output end of the first logic circuit, the second input end of the second logic circuit receives the enable signal, and the output end outputs the second signal.

[0023] The source terminal of the third switch transistor is connected with a power signal, the drain terminal thereof is used as a request output terminal, and the gate terminal thereof is connected with an output terminal of the first logic circuit.

[0024] Optionally, the first logic circuit comprises a NOT gate, a first NAND gate, a second NAND gate and a third NAND gate.

[0025] An input terminal of the NOT gate receives the enable signal, and an output terminal of the NOT gate is connected with a second input terminal of the second NAND gate.

[0026] A first input terminal of the first NAND gate is connected with an output terminal of the comparator, a second input terminal of the first NAND gate is connected with an output terminal of the second NAND gate, and an output terminal of the first NAND gate is connected with a first input terminal of the second NAND gate and a second input terminal of the third NAND gate.

[0027] A first input terminal of the third NAND gate is connected with the output terminal of the comparator, and an output terminal thereof is connected with the second logic circuit and the gate terminal of the third switch transistor.

[0028] Optionally, the second logic circuit comprises a fourth NAND gate, a fifth NAND gate and a fourth switch transistor.

[0029] A first input terminal of the fourth NAND gate is connected with the output terminal of the first logic circuit, a second input terminal of the fourth NAND gate is connected with an output terminal of the fifth NAND gate, and an output terminal of the fourth NAND gate is connected with a first input terminal of the fifth NAND gate and a drain terminal of the fourth switch transistor.

[0030] A second input terminal of the fifth NAND gate receives the enable signal.

[0031] The gate terminal of the fourth switch transistor receives the enable signal, and a source terminal thereof is used as an output terminal of the second logic circuit.

[0032] Optionally, the photodiode, the charge transfer module, the reset transistor, the mode control transistor and the first output module are prepared on a first chip, and the second output module is prepared on a second chip; the first chip is arranged on an upper layer of the second chip, and copper interconnection is arranged between the first chip and the second chip.

[0033] In another aspect of the embodiments of the present disclosure, a signal processing device is provided, comprising: a pixel array composed of n columns and m rows of the image sensor pixel units according to any one of the embodiments described above, a timing exposure circuit, a pulse coding circuit and a dual-mode data fusion module; m and n are integers greater than 1 respectively.

[0034] The pixel array is connected with the timing exposure circuit and the pulse coding circuit;

[0035] One end of the timing exposure circuit is connected with the pixel array, and the other end is connected with the dual-mode data fusion module;

[0036] One end of the pulse coding circuit is connected with the pixel array, and the other end is connected with the dual-mode data fusion module;

[0037] The input end of the dual-mode data fusion module is connected with the timing exposure circuit and the pulse coding circuit, and the output end outputs image information of the pixel array.

[0038] Optionally, the timing exposure circuit is arranged at a first position on a second chip, and the pulse coding circuit and the dual-mode data fusion module are arranged at a second position on the second chip; a distance between the first position and the second position is greater than a preset distance.

[0039] Optionally, the timing exposure circuit is arranged on a second chip, and the pulse coding circuit and the dual-mode data fusion module are arranged on a third chip.

[0040] Optionally, the timing exposure circuit comprises a row driving control module, a column readout module and a first coding module;

[0041] The row driving control module is connected with image sensor pixel units in the pixel array row by row;

[0042] n input ends of the column readout module are connected with the image sensor pixel units in the pixel array column by column, and an output end is connected with the first coding module;

[0043] An input end of the first coding module is connected with the column readout module, and an output end is connected with the dual-mode data fusion module and is used for outputting a first coding signal.

[0044] Optionally, the pulse coding circuit comprises a row arbitration module, a column address encoder, a row address encoder and a second coding module;

[0045] The row arbitration module is connected with the image sensor pixel units in the pixel array row by row, and is connected with the row address encoder;

[0046] n input ends of the column address encoder are connected with the image sensor pixel units in the pixel array column by column, and an output end is connected with the second coding module;

[0047] An input end of the row address encoder is connected with the row arbitration module, and an output end is connected with the second coding module;

[0048] The input end of the second encoding module is connected with the row arbitration module, the row address encoder and the column address encoder, the output end is connected with the dual-mode data fusion module, and is configured to output a pulse encoding signal.

[0049] In yet another aspect of the embodiments of the present disclosure, an electronic device is provided, including a processor and a memory connected with the processor in communication, and further including the image sensor pixel unit according to any one of the embodiments described above or the signal processing apparatus according to any one of the embodiments described above;

[0050] The memory stores computer-executable instructions;

[0051] The processor executes the computer-executable instructions stored in the memory to control the image sensor pixel unit or the signal processing apparatus.

[0052] Optionally, the electronic device is incorporated into any one of the following: an image data acquisition device, an audio / video player, a navigation device, an entertainment device, a communication device, a roadside traffic facility, a device in a motor vehicle, an industrial detection device, a flight device, a medical device, and a security device.

[0053] Based on the image sensor pixel unit, the signal processing apparatus and the electronic device provided in the embodiments of the present disclosure, the image sensor pixel unit includes a photodiode, a charge transfer module, a reset transistor, a mode control transistor, a first output module and a second output module; one end of the photodiode is grounded, and the other end is connected with the mode control transistor and the charge transfer module; one end of the charge transfer module is connected with the photodiode, and the other end is connected with the reset transistor and the first output module; the source end of the reset transistor is connected with a power supply signal, the drain end is connected with the charge transfer module and the first output module, and the gate end receives a reset signal; the source end of the mode control transistor is connected with the other end of the photodiode, the drain end is connected with the second output module, and the gate end receives a mode control signal; one end of the first output module is connected with the drain end of the reset transistor and the charge transfer module, and the other end outputs a first signal; one end of the second output module is connected with the drain end of the mode control transistor, and the other end outputs a second signal. The image sensor pixel unit provided in the embodiments of the present disclosure outputs the first signal through the first output module and outputs the second signal through the second output module, so as to combine the pulse sequence imaging and the global timing exposure imaging in one pixel unit, and to widen the dynamic range of the image sensor without increasing the number of photodiodes.

[0054] The technical solutions of the present disclosure will be further described in detail below with reference to the drawings and embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0055] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0056] The present disclosure can be more clearly understood and appreciated from the following detailed description, taken in conjunction with the following drawings of which:

[0057] Figure 1 is a structural schematic diagram of an image sensor pixel unit provided by an exemplary embodiment of the present disclosure;

[0058] Figure 2 is a circuit schematic diagram of a charge storage module in an image sensor pixel unit provided by another exemplary embodiment of the present disclosure;

[0059] Figure 3 is a circuit schematic diagram of a second output module in an image sensor pixel unit provided by yet another exemplary embodiment of the present disclosure;

[0060] Figure 4 is a structural schematic diagram of a pulse readout control circuit in an image sensor pixel unit provided by still another exemplary embodiment of the present disclosure;

[0061] Figure 5 is a circuit schematic diagram of a pulse readout control circuit in an image sensor pixel unit provided by yet another exemplary embodiment of the present disclosure;

[0062] Figure 6 is a structural schematic diagram of a signal processing device provided by an exemplary embodiment of the present disclosure;

[0063] Figure 7 is a structural schematic diagram of a signal processing device provided by another exemplary embodiment of the present disclosure;

[0064] Figure 8 is a signal timing diagram corresponding to a signal processing device provided by an exemplary embodiment of the present disclosure;

[0065] Figure 9 is a structural schematic diagram of an electronic device according to an application embodiment of the present disclosure. DETAILED DESCRIPTION

[0066] Various exemplary embodiments of the present disclosure will now be described in detail below with reference to the accompanying drawings. Note that the relative arrangement, numerical expressions, and numerical values of components and steps set forth in these embodiments do not limit the scope of the present disclosure unless otherwise specifically stated.

[0067] Those skilled in the art can understand that the terms "first", "second", and the like in the embodiments of the present disclosure are only used to distinguish different steps, devices, or modules, and do not represent any specific technical meaning, nor do they represent a necessary logical sequence between them.

[0068] It should also be understood that, in the embodiments of the present disclosure, "multiple" can refer to two or more, and "at least one" can refer to one, two or more.

[0069] It should also be understood that, for any component, data or structure mentioned in the embodiments of the present disclosure, one or more can be generally understood without explicit limitation or in the context of the opposite implication.

[0070] In addition, the term "and / or" in the present disclosure is only a description of the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B can represent the three cases of A alone, A and B together, and B alone. In addition, the character " / " in the present disclosure generally represents an "or" relationship between the front and rear associated objects.

[0071] It should also be understood that the description of the embodiments of the present disclosure emphasizes the differences between the embodiments, and the same or similar parts can be referred to each other, and for the sake of brevity, will not be repeated.

[0072] At the same time, it should be understood that, for the convenience of description, the size of each part shown in the drawings is not drawn according to the actual proportional relationship.

[0073] The following description of at least one example embodiment is merely illustrative in nature and is in no way intended to limit the present disclosure, its application or uses.

[0074] Techniques, methods, and devices known to those of ordinary skill in the relevant art can not be discussed in detail, but should be considered part of the specification where appropriate.

[0075] It should be noted that: similar signs and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further discussed in the subsequent drawings.

[0076] The embodiments of the present disclosure can be applied to terminal devices, computer systems, servers and other electronic devices, which can operate with many other general or special computing system environments or configurations. Examples of well-known terminal devices, computing systems, environments and / or configurations suitable for use with terminal devices, computer systems, servers and other electronic devices include, but are not limited to: personal computer systems, server computer systems, thin clients, thick clients, handheld or laptop devices, microprocessor-based systems, set-top boxes, programmable consumer electronics, network personal computers, small computer systems, large computer systems and distributed cloud computing technology environments including any of the above systems, etc.

[0077] Electronic devices such as terminal devices, computer systems, servers, and the like can be described in the general context of computer system-executable instructions, such as program modules, being executed by a computer system. Generally, program modules can include routines, programs, objects, components, logic, data structures, and the like that perform particular tasks or implement particular abstract data types. Computer systems / server can be practiced in distributed cloud computing environments with remote processing devices that are linked through a communications network. In a distributed cloud computing environment, program modules can be located in local and / or remote computer system storage media including memory storage devices.

[0078] Conventional image sensors reflect the intensity of light by recording the cumulative value of photoelectric signals at a fixed time, and the range of light intensity between the maximum light intensity and the minimum light intensity that the sensor can distinguish is the dynamic range of the sensor. In the process of implementing the present disclosure, the inventors found that the main ways to widen the dynamic range of the image sensor at present include increasing the number of photodiodes to realize the separate sensing of strong and weak light, or adjusting the exposure time to expose the weak light signal for a longer time and expose the strong light signal for a shorter time, or increasing multiple signal conversion readout channels to realize different gains for strong and weak signals. These methods all need to increase the hardware cost to improve the dynamic range, and the improvement effect of the dynamic range is directly related to the hardware cost, for example, if the dynamic range is to be increased by ten times, the exposure time needs to be increased by ten times, or the photosensitive area needs to be increased by ten times, which causes a large hardware cost and a large decrease in frame rate. In view of the above problems, the present disclosure provides an image sensor pixel unit to widen the dynamic range of the image sensor without increasing hardware.

[0079] Figure 1 is a structural schematic diagram of an image sensor pixel unit provided by an exemplary embodiment of the present disclosure. As shown in the figure, the image sensor pixel unit (hereinafter referred to as a pixel unit) of the embodiment includes a photodiode 11, a charge transfer module 12, a first output module 13, a second output module 14, a reset transistor 15, and a mode control transistor 16. Figure 1

[0080] The photodiode 11 is grounded at one end and connected with the mode control transistor 16 and the charge transfer module 12 at the other end.

[0081] The photodiode 11 is used to receive a light signal to generate photoelectric charges within an exposure time.

[0082] Optionally, the photodiode provided by the embodiment can be a pin-photodiode (PPD).

[0083] ​The charge transfer module 12 is connected with the photodiode 11 at one end and connected with the reset transistor 15 and the first output module 13 at the other end.

[0084] The charge transfer module 12 is configured to store the photoelectric charges generated by the photodiode 11 when the exposure time length is reached, and input the stored photoelectric charges into the first output module according to the control of the row selection signal RS.

[0085] In the embodiment, the charge transfer module is configured to store the photoelectric charges which do not reach the exposure threshold within the exposure time length, and input all the photoelectric charges accumulated within the exposure time length into the first output module according to the control of the row selection signal RS when the exposure time length is reached, so as to generate the first signal corresponding to the timed exposure.

[0086] The source end of the reset transistor 15 is connected with the power supply signal Vdd, the drain end is connected with the charge transfer module 12 and the first output module 13, and the gate end receives the reset signal RST.

[0087] When the reset transistor 15 is turned on according to the reset signal received by the gate end, the photodiode 11 is controlled to perform the reset.

[0088] Optionally, when the reset signal RST is high, the reset transistor 15 is turned on, and at this time, the pixel unit is in the reset stage, at this time, the first switch signal and the second switch signal simultaneously control the first switch transistor and the second switch transistor to be turned on, and the reset transistor, the first switch transistor and the second switch transistor jointly turn on the path between the photodiode and the power supply signal Vdd, so that all the photoelectric charges in the photodiode are transferred to the power supply end, and the reset of the photodiode is realized.

[0089] The source end of the mode control transistor 16 is connected with the other end of the photodiode 11, the drain end is connected with the second output module 14, and the gate end receives the mode control signal SS.

[0090] The mode control transistor 16 is configured to connect the photodiode 11 with the comparator 141 and be turned on according to the control of the mode control signal SS.

[0091] In the embodiment, the timing of the mode control signal SS always keeps high during the pulse imaging stage, so that the photoelectric charges accumulated by the photodiode can reach the threshold value at any time during the pulse imaging stage, and the photoelectric charges can be output to the second output module 14 through the mode control transistor 16.

[0092] One end of the first output module 13 is connected with the charge transfer module 12 and the drain end of the reset transistor 15, and the other end outputs the first signal.

[0093] The first output module 13 is configured to generate and output the first signal according to the photoelectric charges received from the charge transfer module 12. In the embodiment, the first output module 13 realizes the timed exposure output of the pixel unit, and can better collect image information in a weak light environment.

[0094] The second output module 14 is connected to the drain end of the mode control transistor 16 at one end and outputs the second signal at the other end.

[0095] The second output module 14 is configured to output the second signal in response to the amount of photoelectric charges generated in the photodiode reaching the exposure threshold. In the embodiment, the second output module realizes the quantitative exposure of the pixel unit, and reflects the light intensity by recording the time length when the amount of photoelectric charges accumulated in the photodiode reaches the exposure threshold, so as to accurately reflect the strong light information received by the pixel unit.

[0096] Therefore, the first output module and the second output module are used to ensure that the same pixel unit can not only guarantee the imaging performance in dark light, but also accurately reflect the strong light information received by the pixel unit, thereby widening the dynamic range of the image sensor using the pixel unit of the embodiment of the present disclosure.

[0097] The image sensor pixel unit provided by the above embodiment of the present disclosure includes a photodiode, a charge transfer module, a reset transistor, a mode control transistor, a first output module and a second output module. One end of the photodiode is grounded, and the other end is connected to the mode control transistor and the charge transfer module. One end of the charge transfer module is connected to the photodiode, and the other end is connected to the reset transistor and the first output module. The source end of the reset transistor is connected to a power supply signal, the drain end is connected to the charge transfer module and the first output module, and the gate end receives a reset signal. The source end of the mode control transistor is connected to the other end of the photodiode, the drain end is connected to the second output module, and the gate end receives a mode control signal. One end of the first output module is connected to the drain end of the reset transistor and the charge transfer module, and the other end outputs the first signal. One end of the second output module is connected to the drain end of the mode control transistor, and the other end outputs the second signal. The image sensor pixel unit provided by the embodiment of the present disclosure outputs the first signal through the first output module and outputs the second signal through the second output module, realizes the combination of the pulse sequence imaging and the global timed exposure imaging in one pixel unit, and widens the dynamic range of the image sensor without increasing the number of photodiodes.

[0098] Figure 2 is a circuit schematic diagram of the charge storage module in the image sensor pixel unit provided by another exemplary embodiment of the present disclosure. As Figure 2As shown, the charge transfer module 12 includes a first capacitor 121, a second capacitor 122, a first switching transistor 123, and a second switching transistor 124.

[0099] One end of the first capacitor 121 is grounded, and the other end is connected to the photodiode 11 through the first switching transistor 123, and to the second capacitor 122 through the second switching transistor 124. The first capacitor 121 receives and stores photoelectric charge in response to the first switching transistor 123 being turned on according to the control of the first switching signal GS. Optionally, the first switching transistor 123 is turned on when the first switching signal GS is high, and turned off when the first switching signal GS is low.

[0100] One end of the second capacitor 122 is grounded, and the other end is connected to the drain terminal of the reset transistor 15, and also connected to the first capacitor 121 through the second switching transistor 124. In response to the second switching transistor 124 being turned on according to the control of the second switching signal TX, the second capacitor 122 reads the photoelectric charge stored in the first capacitor 121 into the second capacitor 122. Optionally, when the second switching signal TX is high, the second switching transistor 124 is turned on; when the second switching signal TX is low, the second switching transistor 124 is turned off.

[0101] In this embodiment, the first switching transistor 123 implements global exposure control. When performing global timed exposure, according to the control of the first switching signal GS, all the photoelectric charge accumulated in the photodiode during the exposure cycle is transferred to the first capacitor 121 for storage. In addition, the timing of the first switching signal GS corresponding to all pixel units in the pixel array composed of pixel units provided in this embodiment is unified. That is, when the exposure cycle is reached, a high-level first switching signal GS is provided to all pixel units in the pixel array, so that the photoelectric charge in all photodiodes in the pixel array is transferred to the corresponding first capacitor for storage. When outputting by row, a high-level signal is provided row by row according to the second switching signal TX, so that the pixel units in the pixel array output the first signal row by row.

[0102] like Figure 2 As shown, the first output module 13 in the pixel unit provided in this embodiment includes a source follower transistor 131 and a readout transistor 132.

[0103] The source terminal of the source follower transistor 131 is connected to the power supply signal Vdd, the drain terminal is connected to the readout transistor 132, and the gate terminal is connected to the charge transfer module 12. The source follower transistor 131 is used to follow the change in photoelectric charge stored in the charge transfer module 12 to obtain the first signal.

[0104] The drain terminal of the readout transistor 132 is connected to the drain terminal of the source follower transistor. The source terminal serves as the first output terminal of the pixel unit, outputting a first signal Vout. The gate terminal receives the row selection signal. In response to the readout transistor being turned on according to the control of the row selection signal, the readout transistor 132 outputs the first signal Vout through its first output terminal.

[0105] The functions, connections, and implementations of the source follower transistor and readout transistor in this embodiment are the same as those in the existing 3T pixel unit, and will not be repeated here.

[0106] Figure 3 This is a circuit diagram of a second output module in an image sensor pixel unit provided in yet another exemplary embodiment of this disclosure. (See diagram for reference.) Figure 3 As shown, the second output module 14 includes a comparator 141 and a pulse readout control circuit 142.

[0107] The negative input terminal of comparator 141 is connected to the drain terminal of mode control transistor 16, the positive input terminal receives the reference signal Vth, and the output terminal is connected to the input terminal of pulse readout control circuit 142. Comparator 141 is used to determine whether the photoelectric charge has reached the exposure threshold. In response to the photoelectric charge reaching the exposure threshold, the output signal of comparator 141 is triggered to flip, and the flipped output signal is input to the pulse readout control circuit.

[0108] The input terminal of the pulse readout control circuit 142 is connected to the output terminal of the comparator 141, and the output terminal outputs a second signal. The pulse readout control circuit 142 sends a pulse request signal to the external arbitration module based on the flipped output signal, and outputs the second signal in response to the high-level enable signal fed back by the external arbitration module.

[0109] Optionally, the negative input terminal of comparator 141 is connected to the drain terminal of mode control transistor 16, and the positive input terminal of comparator 141 receives the reference signal Vth. The signal output by comparator 141 is determined based on the comparison between the signal output by the photodiode through the mode control transistor and the reference signal. After the photodiode is reset, the output signal is the power supply voltage (high level). As the photoelectric charge accumulates, the output signal gradually decreases. When the exposure threshold is reached, the output signal is less than the reference signal Vth. Therefore, in this embodiment, when the photodiode is reset, the reference signal Vth (e.g., set to 1 / 2 of the power supply signal) is less than the power supply signal. At this time, the signal at the positive input terminal of the comparator is less than the signal at the negative input terminal, and a low-level signal is output. When the accumulated photoelectric charge of the photodiode reaches the exposure threshold, the signal input to the negative input terminal of the comparator is less than the reference signal. At this time, the signal output by the comparator is flipped, and a high-level signal is output.

[0110] Figure 4Fig. 1 is a structural schematic diagram of a pulse readout control circuit in an image sensor pixel unit provided by another exemplary embodiment of the present disclosure. As shown in Fig. 1, the pulse readout control circuit 142 includes a first logic circuit 41, a second logic circuit 42, and a third switch transistor 43. Figure 4 The first input end of the first logic circuit 41 is connected with the output end of the comparator 141, the second input end of the first logic circuit 41 receives the enable signal ACK, and the output end is connected with the gate end of the second logic circuit 42 and the third switch transistor 43; the first logic circuit 41 outputs the third signal Z to the third switch transistor 43 and the second logic circuit 42.

[0111] The first logic circuit 41 is configured to receive the output signal COMP OUT of the comparator 141 and the enable signal ACK, and output the third signal Z to the third switch transistor 43 and the second logic circuit 42, so as to control whether the third switch transistor 43 is turned on.

[0112] In the embodiment, the first logic circuit is configured to output the third signal Z as a high level when the output signal COMP OUT and the enable signal ACK are both low levels; output the third signal Z as a low level when the output signal COMP OUT is a high level and the enable signal ACK is a low level in the pulse request phase (so as to control the third switch transistor 43 to be turned on and output the pulse request signal); output the third signal Z as a high level when the enable signal ACK is a high level and the output signal COMP OUT is also a high level in the request enable phase; and output the third signal Z as a high level when the output signal COMP OUT is a high level and the enable signal is a low level after the pulse readout control circuit 142 completes outputting the second signal. That is, the first logic circuit 41 is configured to output the low level signal only in the pulse request phase in which the pulse readout control circuit 142 is executed, so as to control the third switch transistor 43 to be turned on and output the pulse request signal.

[0113] The source end of the third switch transistor 43 is connected with the power supply signal Vdd, the drain end thereof is used as a request output end, and the gate end thereof is connected with the output end of the first logic circuit 41. The source end of the third switch transistor 43 is connected with the power supply signal Vdd, the drain end thereof is used as the request output end, and the gate end thereof receives the third signal Z; in response to the third signal Z being a low level, the third switch transistor 43 is turned on, and outputs the high level pulse request signal REQ through the request output end.

[0114] The first input end of the second logic circuit 42 is connected with the output end of the first logic circuit 41, the second input end of the second logic circuit 42 receives the enable signal ACK, and the output end outputs the second signal Vspike.

[0115] The first input end of the second logic circuit 42 is connected with the output end of the first logic circuit 41, the second input end of the second logic circuit 42 receives the enable signal ACK, and the output end outputs the second signal Vspike.

[0116] The second logic circuit 42 is used to receive the third signal Z and the enable signal ACK. In response to the enable signal being high and the third signal being high, it outputs the second signal Vspike. In this embodiment, the second logic circuit 42 outputs the high-level second signal Vspike only when both the third signal Z and the enable signal ACK are high.

[0117] Figure 5 This is a circuit diagram of a pulse readout control circuit in a pixel unit of an image sensor provided in another exemplary embodiment of this disclosure. For example... Figure 5 As shown, the first logic circuit 41 in the pulse readout control circuit 142 includes: NOT gate 411, first NAND gate 412, second NAND gate 413 and third NAND gate 414.

[0118] The input of NOT gate 411 receives the enable signal ACK, and the output of NOT gate 411 is connected to the second input of the second NAND gate 413.

[0119] The first input terminal of the first NAND gate 412 is connected to the output terminal of the comparator and receives the output signal COMP OUT of the comparator. The second input terminal of the first NAND gate 412 is connected to the output terminal of the second NAND gate 413. The output terminal of the first NAND gate 412 is connected to the first input terminal of the second NAND gate 413 and the second input terminal of the third NAND gate 414.

[0120] Optionally, the output signal of the first NAND gate 412 can be denoted as Q1.

[0121] The first input terminal of the third NAND gate 414 is connected to the output terminal of the comparator to receive the output signal COMP OUT of the comparator. The output terminal is connected to the gate terminal of the second logic circuit 42 and the third switching transistor 43. The output terminal is used to output the third signal Z.

[0122] like Figure 5 As shown, the second logic circuit 42 includes: a fourth NAND gate 421, a fifth NAND gate 422, and a fourth switching transistor 423;

[0123] The first input terminal of the fourth NAND gate 421 is connected to the output terminal of the first logic circuit 41 to receive the third signal Z. The second input terminal of the fourth NAND gate 421 is connected to the output terminal of the fifth NAND gate 422. The output terminal of the fourth NAND gate 421 is connected to the first input terminal of the fifth NAND gate 422 and the drain terminal of the fourth switching transistor 423.

[0124] Optionally, the output signal of the fourth NAND gate 421 can be denoted as Q2.

[0125] The second input of the fifth NAND gate 422 receives the enable signal ACK.

[0126] The gate terminal of the fourth switch transistor 423 receives an enable signal ACK, and the source terminal of the fourth switch transistor 423 serves as an output terminal of the second logic circuit and outputs a second signal Vspike through the source terminal of the fourth switch transistor 423 in response to the enable signal ACK being high.

[0127] COMP OUT ACK Q1 Z REQ Q2 Vspike Reset 0 0 1 1 0 0 0 Pulse request 1 0 1 0 1 1 0 Request allow 1 1 0 1 0 1 1 Output end 1 0 0 1 0 0 0

[0128] Table 1

[0129] Table 1 shows the truth values of the pulse readout control circuit at various stages during operation. First, after the pixel unit is reset, the voltage Vpd on the photodiode is at a high potential close to the power supply voltage VDD, the output signal COMPOUT of the comparator is low, and the requested enable signal ACK is also low. According to the circuit logic, the signal Q1 obtained by passing the COMP OUT through a NAND gate is high, the third signal Z is high, the third switch transistor is off, and the pulse request signal REQ is low. When Vpd reaches a preset threshold during exposure, COMP OUT will flip to high, and Q1 will remain high before the enable signal ACK is received, and the third signal Z will change to low to turn on the third switch transistor, and the pulse request signal REQ will become high, sending a high pulse request signal REQ to the peripheral circuit, and Q2 will become high, waiting for the enable signal ACK to output the second signal Vspike (pulse signal). When the pulse request signal REQ is enabled, the enable signal ACK changes to high, Q1 becomes low, the third signal Z becomes high, the third switch transistor is off, and the pulse request signal REQ is no longer sent. The enable signal ACK controls the fourth switch transistor to be turned on, and the second signal Vspike is high. After the output is completed, the pulse request signal REQ changes to low, and the output signal COMP OUT will remain high before the pixel is reset, so that Q1 remains low, the third signal Z remains high, and the pixel unit will not send the pulse request signal REQ before the next reset. Before the next pixel unit is reset, Q2 will also remain low, so that the output of the pixel unit is still low even if other pixel units in the same row output later, avoiding repeated output of the pulse signal.

[0130] In some optional embodiments, the photodiode 11, the charge transfer module 12, the reset transistor 15, the mode control transistor 16, and the first output module 13 are prepared on a first chip, and the second output module 14 is prepared on a second chip; the first chip is arranged on the upper layer of the second chip, and copper interconnection is provided between the first chip and the second chip.

[0131] The embodiment meets the requirement of the pixel unit for light sensing by preparing the light sensing part in the pixel unit in the first chip in the upper layer, and improves the integration of the chip and compresses the area occupied by the pixel array in the sensor by the chip stacking technology.

[0132] Optionally, the pixel unit can be divided into two main parts: a light sensing unit (including the photodiode 11, the charge transfer module 12, the reset transistor 15, the mode control transistor 16 and the first output module 13) and a pulse generation and readout control unit (including a comparator and a pulse readout control circuit), wherein the light sensing unit is prepared on the top wafer (top chip), the pulse generation and readout unit is prepared on the bottom wafer (bottom chip), and the two wafers are stacked by the copper interconnection hybrid bonding process, so that the two working modes can be realized on the limited pixel area.

[0133] Figure 6 is a structural schematic diagram of the signal processing device provided by an example embodiment of the present disclosure. As shown in Figure 6 the device provided by the embodiment includes a pixel array 61 composed of n columns and m rows of image sensor pixel units (hereinafter referred to as pixel units) provided by any of the above embodiments, a timed exposure circuit 62, a pulse encoding circuit 63 and a dual-mode data fusion module 64. m and n are each an integer greater than 1.

[0134] The pixel array 61 is connected with the timed exposure circuit 62 and the pulse encoding circuit 63, and is configured to output a first signal row by row according to the control of the timed exposure circuit.

[0135] The structure of the pixel unit included in the pixel array in the embodiment can refer to any of the above embodiments. Optionally, when the light sensing unit and the pulse generation and readout control unit in the pixel unit are prepared on different wafers, the pixel array is distributed on the two wafers, the light sensing unit of each pixel unit in the pixel array is prepared on the upper wafer, and the pulse generation and readout control unit of each pixel unit in the pixel array is prepared on the lower wafer.

[0136] The timed exposure circuit 62 is connected with the pixel array 61 at one end and with the dual-mode data fusion module 64 at the other end. The timed exposure circuit 62 is configured to control the image sensor pixel units in the pixel array 61 to output a first signal row by row according to an exposure period, and output or input the dual-mode data fusion module 64 after processing the first signal into a first encoded signal.

[0137] In the embodiment, the timing exposure circuit receives n first signals output by the pixel units in the pixel array row by row in an exposure period, encodes the n first signals read each time, and outputs the first encoded signals as image information obtained by timing exposure, or inputs the n first encoded signals into the dual-mode data fusion module.

[0138] The pulse encoding circuit 63 is connected to the pixel array 61 at one end and to the dual-mode data fusion module 64 at the other end. The pulse encoding circuit 63 is configured to record and process row address information row addr, column address information col addr and exposure time information timestamp of the image sensor pixel unit reaching the exposure threshold when the photoelectric charge accumulated in the image sensor pixel unit reaches the exposure threshold in the exposure period, and output or input the pixel address encoding and pulse encoding signals obtained by processing into the dual-mode data fusion module 64.

[0139] In the embodiment, the pulse encoding circuit is used to realize asynchronous reading of the pixel units. The exposure time information represents the time length between the time when the pixel unit is reset and the time when the photoelectric charge reaches the exposure threshold. The exposure time information can represent the intensity of light. The stronger the light intensity, the shorter the exposure time length. The weaker the light intensity, the longer the exposure time length. After obtaining the pulse encoding signal and the pixel address encoding, the embodiment can directly output them as output signals, which can represent the image information collected in a strong light environment. Alternatively, the pixel address encoding and the pulse encoding signal are input into the dual-mode data fusion module.

[0140] The input end of the dual-mode data fusion module 64 is connected to the timing exposure circuit 62 and the pulse encoding circuit 63, and the output end outputs the image information of the pixel array 61. The dual-mode data fusion module 64 is configured to determine the image information corresponding to the pixel array based on the first encoded signal, the pixel address encoding and the pulse encoding signal.

[0141] Alternatively, the dual-mode data fusion module outputs the image information through a chip digital signal interface arranged on the chip.

[0142] In the embodiment, the pulse imaging data (generated by the pulse encoding circuit) and the global timing exposure data (generated by the timing exposure circuit) are generated in one exposure cycle. The pulse encoding circuit and the timing exposure circuit can directly input the generated signals to the outside of the chip, or can input the generated signals to the dual-mode data fusion module. The dual-mode data fusion module synthesizes the signals output by the timing exposure circuit and the pulse encoding circuit, and realizes the fusion of the strong light information that can be more accurately expressed by the pulse data on the basis of the global timing exposure data, to synthesize a high dynamic image for output. The embodiment retains two data output modes of independent dual-mode data separate output and fusion output. The data amount of the independent dual-mode data separate output is relatively large, the data amount of the fusion output is relatively small, and the data amount of the fusion output is a standard image output data format, which is better compatible with subsequent data processing chips.

[0143] In some optional embodiments, the timing exposure circuit 62 is arranged at the first position on the second chip, and the pulse encoding circuit 63 and the dual-mode data fusion module 64 are arranged at the second position on the second chip.

[0144] In the embodiment, most of the circuits included in the timing exposure circuit 62 work in an analog voltage domain. The analog circuit has a high requirement for the accuracy of signals. Therefore, to avoid the disturbance of signals of the digital circuit module to the analog circuit signals, the distance between the first position and the second position is greater than a preset distance. For example, the first position is the lower left corner of the second chip, and the second position is the upper right corner of the second chip. Thus, the analog power supply is ensured to have a physical distance as small as possible from the chip interface to the internal module circuit, to avoid the intersection with the digital circuit, to ensure the accuracy of the analog signals, and to further ensure the imaging performance of the global timing exposure mode in dark light.

[0145] Optionally, the pulse generation and readout control unit in each pixel unit in the pixel array is prepared at the middle position of the second chip, and the photosensitive unit in each pixel unit in the pixel array is prepared on the first chip. The scale of the array of the pulse generation and readout control unit is consistent with the scale of the array of the photosensitive unit. When the chips are stacked, the two arrays are located at the same horizontal position, and each photosensitive unit in the array and the pulse generation and readout control unit at the corresponding position are connected one by one through the inter-chip copper interconnection process. The first chip is stacked on the upper layer of the second chip, the integration of the chip is improved through the chip stacking, the area occupied by the chip is compressed, and the volume of the image sensor is further reduced, so that the image sensor is more portable.

[0146] In some other optional embodiments, the timing exposure circuit 62 is arranged on the second chip, and the pulse encoding circuit 63 and the dual-mode data fusion module 64 are arranged on the third chip.

[0147] In order to avoid the signal of the digital circuit module from disturbing the analog circuit signal, the timing exposure circuit, the pulse encoding circuit and the dual-mode data fusion module are arranged on different chips in the embodiment, and the pixel array is still arranged on the first chip and the second chip. By arranging the analog circuit and the digital circuit on different chips, the analog circuit and the digital circuit are prevented from crossing, and the accuracy of the analog signal is ensured.

[0148] Figure 7 is a structural schematic diagram of a signal processing device provided by another exemplary embodiment of the present disclosure. As shown in Figure 7 The timing exposure circuit 62 in the device provided by the embodiment includes a row drive control module 621, a column readout module 622 and a first encoding module 623.

[0149] The row drive control module 621 is connected with the image sensor pixel units in the pixel array 61 row by row. The row drive control module 621 is configured to provide the image sensor pixel units in the pixel array 61 with a row selection signal RS, a second switch signal TX and a reset signal RST row by row, and provide the pixel array with a first switch signal GS and a mode control signal SS.

[0150] The n input ends of the column readout module 622 are connected with the image sensor pixel units in the pixel array 61 column by column, and the output end is connected with the first encoding module 623. The column readout module 622 is configured to read and process the first signal output by the pixel array 61 row by row, and send the obtained fourth signal to the first encoding module.

[0151] The input end of the first encoding module 623 is connected with the column readout module 622, and the output end is connected with the dual-mode data fusion module 64 and is configured to output a first encoding signal. The first encoding module 623 is configured to encode the fourth signal to obtain the first encoding signal.

[0152] Optionally, the first encoding signal can be a digital signal or a pulse signal, etc.

[0153] The light-receiving unit array in the pixel array in the embodiment is used to receive light signals and convert them into electrical signals, and the control signals required by the light-receiving unit array are all provided by the row driving control module, which can include but is not limited to reset signals RST, second switch signals TX (which control the transfer of electric charges), first switch signals (which control global exposure) GS, mode control signals SS, and row selection signals RS, etc. In addition, since the timing exposure circuit is arranged in the lower chip (the second chip), the first switch signals GS and the mode control signals SS are global signals of the pixel array, and all rows are controlled by the same signal, while the row selection signals RS, the second switch signals TX, and the reset signals RST are independent control signals for each row. A low dropout regulator (LDO) and a charge pump can also be arranged around the row driving control module 621. The main function of the low dropout regulator is to provide stable and low-noise power supply signals for the analog circuit modules such as the light-receiving unit array. The main function of the charge pump is to provide a higher voltage signal than the power supply voltage and a lower negative voltage signal than the ground. The high voltage signal is mainly used to improve the transfer efficiency of the photo-generated charges in the light-receiving unit, and the negative voltage signal is mainly used to suppress the leakage current in the light-receiving unit. The output signals of the low dropout regulator and the charge pump are also connected to the light-receiving unit array through the inter-chip copper interconnection lines. Since the low dropout regulator and the charge pump are common structures in sensor devices in the prior art, their specific structures are not described in detail in the embodiment.

[0154] In the global timing exposure mode, the first signal Vout generated by the light-receiving unit after timing exposure is output row by row under the control of the row driving control module. The selected Vout signal is first output to the bottom end of the light-receiving unit array in the first chip, and then transmitted to the column readout circuit module on the second chip through the inter-chip copper interconnection lines. The main function of the column readout circuit module is to convert the first signal Vout into a digital signal and output it to the first encoding module through a parallel-to-serial conversion circuit. A reference voltage and bias voltage generation module and a slope voltage generation module are also arranged around the column readout circuit module. The reference voltage generation module mainly uses the principle of bandgap reference to generate several temperature-independent voltage signals and current signals for the bias voltage generation module and the slope voltage generation module. The bandgap voltage reference is a circuit used to provide a stable reference voltage or current. It uses the characteristics of semiconductor materials to achieve a stable reference voltage output through a suitable circuit structure. Based on the characteristics of the bandgap reference, temperature-independent voltage signals and current signals are provided.

[0155] The bias voltage generation module mainly utilizes the reference current signal to generate a column readout bias voltage for the column readout circuit module, so as to ensure that the column readout signal is obtained under a fixed current bias. The slope voltage generation module is mainly used for generating a signal voltage which linearly increases with a fixed slope over a fixed period, and the signal voltage is required for realizing single slope ADC analog-digital conversion. The row driving control module, the low dropout linear regulator, the charge pump, the reference voltage and bias voltage generation module, the slope voltage generation module, and the part of the column readout circuit except the parallel-serial conversion circuit are all analog circuit modules working in the analog power voltage domain.

[0156] As shown in Figure 7 The pulse encoding circuit 63 in the device provided by the embodiment includes a row arbitration module 631, a column address encoder 632, a row address encoder 633, and a second encoding module 634.

[0157] The row arbitration module 631 is connected with the image sensor pixel units in the pixel array 61 row by row, and is connected with the row address encoder 633. The row arbitration module 631 receives the pulse request signals row by row from the image sensor pixel units in the pixel array 61, and feeds back an enable signal according to the priority of the image sensor pixel units. The image sensor pixel units output a second signal according to the enable signal ACK.

[0158] The n input ends of the column address encoder 632 are connected with the image sensor pixel units in the pixel array 61 column by column, and the output end is connected with the second encoding module 634. The column address encoder 632 records and encodes the column address information of the image sensor pixel units sending the second signal according to the received second signal, and obtains the column address encoding col addr.

[0159] The input end of the row address encoder 633 is connected with the row arbitration module 631, and the output end is connected with the second encoding module 634. The row address encoder 633 records and encodes the row address information of the image sensor pixel units receiving the enable signal ACK according to the enable signal ACK sent by the row arbitration module 631, and obtains the row address encoding row addr. The row address encoder 633 records the time information timestamp of receiving the enable signal ACK and sends it to the second encoding module.

[0160] In the embodiment, the column address encoder can determine the column address corresponding to the pixel units reaching the exposure threshold in the exposure period, and the row address encoder can determine the row address corresponding to the pixel units reaching the exposure threshold in the exposure period. Based on the row address and the column address, the specific pixel units reaching the exposure threshold can be located, and based on the exposure time information, the light intensity information of the corresponding position of the pixel units is represented, the maximum light intensity that the sensor can distinguish is improved, and the dynamic range of the sensor is expanded.

[0161] The input end of the second encoding module 634 is connected with the row arbitration module 631, the row address encoder 633 and the column address encoder 632, and the output end is connected with the dual-mode data fusion module 64 and is used for outputting a pulse encoding signal. The second encoding module 634 is used for processing the column address encoding and the row address encoding to obtain pixel address encoding, and obtaining the pulse encoding signal based on time information.

[0162] In the embodiment, the pulse generation and readout control unit in the pixel unit is used for detecting the exposure signal of the pixel in real time in the pulse imaging stage, and when the exposure signal of the corresponding pixel unit reaches the set threshold, the pulse generation and readout control unit will send a pulse request signal REQ to the row arbitration module. After receiving the pulse request signal REQ, the row arbitration module will determine which row of the pulse request signal REQ has the highest priority (the priority is determined based on the time sequence, and the pulse request signal REQ sent first has higher priority), and then sends an enable signal ACK to the pixel unit of the row with the highest priority. The row arbitration module will determine the priority according to the time sequence of the arrival of the pulse request signal REQ. In most cases, only one row of pixel units in the pixel array will output the pulse request signal REQ within a certain time. In this case, the row outputting the pulse request signal REQ is the row with the highest priority. If more than one row of pixel units in the pixel array outputs the pulse request signal REQ within a certain time, the row with the highest priority is the row with the earliest output time. After the row with the highest priority is read, the row with the second highest priority is the row with the second earliest output time, and so on. When a row of pixel units sends the pulse request signal REQ and receives the enable signal, all pixels in the row will output their second signals Vspike to the column buffer. Some of the pixel units reach the exposure threshold, and the second signals Vspike output by these pixel units are high. Some pixel units do not reach the exposure threshold, and the second signals Vspike output by these pixel units are low.

[0163] After the second signals Vspike are output to the column buffer, the column address encoder detects which column of the second signals Vspike is high, encodes the address information of the columns and outputs the address information to the second encoding module. At the same time, the row address encoder also encodes the row address of the row receiving the enable signal and outputs the address information to the second encoding module. The clock records the time when the row arbitration module sends the enable signal and outputs the time to the second encoding module. Based on the time of pulse generation timestamp, the row address encoding and the column address encoding, the second encoding module can accurately reflect the strong light information received by the pixel array.

[0164] In some optional embodiments, the dual-mode data fusion module 64 buffers the pixel address code and the pulse code signal to a buffer space in response to the pixel address code and the pulse code signal output by the pulse coding circuit 63 in one exposure period.

[0165] In response to the timing exposure circuit 62 controlling the first row of image sensor pixel units in the pixel array to output n first coded signals, the corresponding column address information is determined according to the row address information and the pixel address code corresponding to the n first coded signals, the corresponding k pulse coded signals of the first row of image sensor pixel units are determined based on the column address information and the row address information, the first signals corresponding to the pixel address code are replaced by the k pulse coded signals, and the image information corresponding to one row of the pixel array is determined based on the replaced pulse coded signals and the un-replaced first coded signals.

[0166] In the embodiment, in the case that the light intensity at the positions corresponding to some pixel units is relatively strong, the pulse coded signal is generated by the pulse coding circuit, and the pixel address code corresponding to the pixel unit is stored, and after the exposure period is reached, all the pixel units in the pixel array output the first signal, which is a timing exposure. The timing exposure can collect more detailed content in a weak light environment, but cannot correctly express the light intensity signal for the part with relatively strong light intensity. Therefore, the first signal corresponding to the pixel address code is replaced by the pulse coded signal in the embodiment, so that the dynamic range of the obtained image information is larger, and the effect is good for both weak light and strong light. After the exposure in two modes is completed in one exposure period, the sensor provided in the embodiment of the application performs fusion coding processing on the dual-mode data, so as to realize single-frame high dynamic range imaging.

[0167] In some optional embodiments, the dual-mode data fusion module 64 is further configured to, after the timing exposure circuit controls the first row of image sensor pixel units in the pixel array to output n first coded signals, determine whether there is an image sensor pixel unit outputting a second signal in the first row of sensor pixels, replace the first coded signal corresponding to the image sensor pixel unit with a pulse coded signal when there is an image sensor pixel unit outputting a second signal, and determine the image information corresponding to one row of the pixel array based on the replaced pulse coded signal and the un-replaced first coded signal.

[0168] In this embodiment, first, in the pulse imaging stage, the second encoding module encodes and caches the real-time generated pulse signal (corresponding to the second signal), and records the row and column address and time information of each pulse signal. In the pulse imaging stage, the timing exposure circuit and the dual-mode data fusion module are in standby state. After the pulse imaging stage and the global exposure end, the global exposure signal (corresponding to the first signal) of the pixel unit is read out row by row, and after analog-to-digital conversion (ADC), the first encoding module will judge whether there is an overexposed signal in the row signal, that is, the signal code value reaches the upper limit (for example, 0-255 represents the brightness of the image, and the brightness greater than 255 cannot be represented by the first signal). If there is an overexposed signal, query the pulse encoding circuit whether the address of the overexposed signal corresponds to the pixel unit that generates a pulse signal in the same frame exposure period of the pulse imaging stage. If the pulse signal is queried, the dual-mode data fusion module calculates the actual light intensity information according to the pulse signal and replaces the original overexposed first signal. After the replacement is completed, the dual-mode data fusion module outputs the fused and encoded row signal. If there is no overexposed signal in the row signal, the global exposure signal can be directly used to express the light intensity information and output. After the output of a row of signal processing is completed, the next row of signal is processed in the same way, and the cycle is formed. Together with the column readout circuit of the chip, a pipeline type signal output form is formed, and the chip does not need to integrate a whole frame data cache unit on the chip, thereby improving the system efficiency of the chip.

[0169] Figure 8 is the signal timing diagram corresponding to the signal processing device provided by an example embodiment of the present disclosure. As shown in Figure 8 , one exposure period of the signal device provided by the present embodiment mainly includes five working stages: the first reset stage, the pulse imaging stage, the second reset stage, the global timing exposure stage and the global exposure signal row-by-row readout stage.

[0170] In the first reset stage, all the reset signals RST in the pixel array are high, all the second switch signals TX are high, the first switch signal GS is high, and the mode control signal SS is high. At this time, the reset transistor, the first switch transistor and the second switch transistor are all turned on, and the reset signal can be connected to the photodiode through these transistors to reset the photodiode. After the reset is completed, the reset signal RST, the second switch signal TX and the first switch signal GS are all changed to low, and the mode control signal SS remains high (the pulse imaging stage remains high in the pulse imaging stage), entering the pulse imaging stage. At this time, the photodiode of the light sensing unit is only connected to the corresponding comparator, and in the exposure process, the voltage on the photodiode gradually decreases with the accumulation of photoelectric charge, and when it falls to the preset threshold, the comparator is triggered to flip. According to the logical function description of the pulse readout control circuit in the above embodiment, the pixel unit triggering the pulse will first send a pulse request signal REQ to the row arbitration module, and the row arbitration module will send an enable signal ACK to the row after confirming the request. At the same time, the row and column address encoder of the chip records the row address information of the pixel unit triggering the pulse, and the clock in the chip records the time of triggering the pulse. Figure 8The REQ, ACK, timestamp, rowaddr, and col addr shown in the middle are only examples of one pulse trigger. In the pulse imaging stage, different pixel units at different positions will trigger pulses at different times depending on the actual light intensity information, and these pulse information are all output and recorded according to the above logic. After the pulse imaging stage lasts for a period of time, the mode control signal SS is lowered to a low level, at which time the pulse imaging stage ends (for example, at a frame rate of 60 frames per second, the duration of the pulse imaging stage can be set to 1 millisecond), and then enters the second reset stage. All reset signals RST in the pixel array are high, all second switch signals TX are high, all row selection signals RS are high, and the first switch signal GS is high, so that the photodiode is reset and the photoelectric charge accumulated on the photodiode in the pulse imaging stage is emptied. After the reset is completed, the reset signal RST, the second switch signal TX, the row selection signal RS, and the first switch signal GS are all lowered to a low level, and all pixel units simultaneously enter the global timing exposure stage. During the global exposure time, the photodiode continuously collects photo-generated charges. After the global exposure time is reached, the row-by-row output of the exposure signal begins. First, the first switch signal GS is raised to a high level, and the photoelectric charge collected by all pixel units in the exposure time is transferred to the first capacitor. Then, the row-by-row correlated double sampling of the pixel signal is performed. During the correlated double sampling, for each row of pixel units, first, the reset signal RST and the row selection signal RS of the row of pixel units are activated to reset the second capacitor and read out the reset signal to the timing exposure circuit (column readout module). Then, the reset signal of the row of pixel units is lowered to a low level, the second switch signal TX of the row of pixel units is activated, the photoelectric charge collected during exposure is transferred from the first capacitor to the second capacitor, and the voltage signal converted from the photoelectric charge in the second capacitor is read out to the timing exposure circuit (column readout module). In the column readout module, first, the reset signal and the voltage signal obtained during exposure are differentially operated to suppress reset noise and noise introduced in the column readout module. Then, the column readout module performs analog-to-digital conversion on the differential result, and outputs the analog-to-digital conversion result of each row (in the figure, RnCm represents the global exposure signal analog-to-digital conversion result of the nth row and the mth column).

[0171] Optionally, after the exposure of the two modes is completed in one exposure period, the signal processing device provided by the present application performs fusion encoding processing on the encoded signals output by the two modes through a dual-mode data fusion module, thereby realizing single-frame high dynamic range imaging.

[0172] The signal processing device provided in the embodiment achieves high dynamic range, global exposure, and imaging processing without motion blur. In the global timing exposure phase, all pixel units in the pixel array start exposure at the same time and end exposure at the same time, all pixel units perform the same length of exposure, and the exposure signals are converted into analog-to-digital signals by the column readout module in a certain order after exposure. In the pulse imaging phase, all pixel units in the pixel array start exposure at the same time, and any pixel unit sends a pulse request signal to the row arbitration module when the exposure amount reaches a preset threshold, and outputs a second signal after receiving the permission signal fed back by the row arbitration module. The peripheral circuit (pulse encoding circuit) records the time when the pixel unit outputs the pulse request signal, and determines the address of the pixel unit generating the pulse according to the pulse request signal output by the pixel unit and the second signal. In the pulse imaging phase, the earlier the pixel unit outputs the pulse request signal, the stronger the light intensity received by the pixel unit. The pulse imaging phase is provided with a maximum exposure time (the maximum exposure time can be determined according to the maximum light intensity that can be represented by the first signal output by the timing exposure circuit, and the maximum exposure time corresponds to the maximum light intensity), and the pulse imaging phase ends when the maximum exposure time is reached. Therefore, in the pulse imaging phase, only some pixel units that receive strong light intensity will trigger pulse output. In the signal processing device provided in the embodiment, the global timing exposure signal can accurately depict weak light signals, and the pulse signal can quickly and accurately express strong light signals, thereby achieving high dynamic range imaging.

[0173] In addition, the embodiment of the present disclosure further provides an electronic device, comprising:

[0174] a processor, and a memory connected with the processor in communication, and further comprising the image sensor pixel unit or the signal processing device of any one of the above embodiments;

[0175] the memory stores computer execution instructions;

[0176] the processor executes the computer execution instructions stored in the memory to control the image sensor pixel unit or the signal processing device.

[0177] The electronic device provided in the present disclosure can be included in any one of the following: an image data acquisition device, an audio / video player, a navigation device, an entertainment device, a communication device, a roadside traffic facility, a device in a motor vehicle, an industrial detection device, a flight device, a medical device, a security device, and the like.

[0178] The electronic device provided by the present disclosure can be applied to any one of the following: an image data acquisition device, an audio / video player, a navigation device, an entertainment device, a communication device, a roadside traffic facility, a device in a motor vehicle, an industrial detection device, a flight device, a medical device, a security device, etc.

[0179] Figure 9 A structural schematic diagram of an application embodiment of the electronic device of the present disclosure is shown in FIG. 1. Hereinafter, an electronic device according to an embodiment of the present disclosure will be described with reference to FIG. 1. Figure 9 The electronic device can be any one or both of the first device and the second device, or a single device independent of them, which can communicate with the first device and the second device to receive the acquired input signals therefrom.

[0180] As shown in FIG. 1, the electronic device includes one or more processors and a memory. Figure 9

[0181] The processor can be a central processing unit (CPU) or other form of processing unit having data processing and / or instruction execution capabilities, and can control other components in the electronic device to perform desired functions.

[0182] The memory can store one or more computer program products, and can include various forms of computer readable storage media, such as volatile memory and / or non-volatile memory. The volatile memory may, for example, include random access memory (RAM), cache memory, etc. The non-volatile memory may, for example, include read-only memory (ROM), hard disk, flash memory, etc. One or more computer program products can be stored on the computer readable storage medium, and the processor can execute the computer program products to implement the image sensor pixel unit or signal processing apparatus of various embodiments of the present disclosure described above and / or other desired functions.

[0183] In one example, the electronic device can further include an input device and an output device, which are interconnected through a bus system and / or other forms of connection mechanism (not shown).

[0184] In addition, the input device can further include, for example, a keyboard, a mouse, etc.

[0185] The output device can output various information, including determined distance information, direction information, etc., to the outside. The output device can include, for example, a display, a speaker, a printer, a communication network and a remote output device connected thereto, etc.

[0186] Of course, in order to simplify, Figure 9 ​Only some of the components of the electronic device related to the present disclosure are shown in the figure, and components such as a bus, an input / output interface, and the like are omitted. In addition to this, the electronic device can include any other appropriate components according to a specific application.

[0187] In addition to the above-mentioned method and device, an embodiment of the present disclosure can be a computer program product including computer program instructions that, when executed by a processor, cause the processor to perform an image sensor pixel unit or a signal processing apparatus according to various embodiments of the present disclosure described in the above parts of the specification.

[0188] The computer program product can be written in any combination of one or more programming languages, including an object-oriented programming language such as Java, C++, etc., and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code can be executed entirely on the user computing device, partially on the user device, as a stand-alone software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0189] In addition, an embodiment of the present disclosure can also be a computer readable storage medium having stored thereon computer program instructions, which, when executed by a processor, cause the processor to perform an image sensor pixel unit or a signal processing apparatus according to various embodiments of the present disclosure described in the above parts of the specification.

[0190] The computer readable storage medium can take any combination of one or more readable media. The readable medium can be a readable signal medium or a readable storage medium. The readable storage medium may, for example, include but is not limited to an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or apparatus, or any combination of the above. More specific examples (non-exhaustive list) of readable storage media include an electrical connection having one or more wires, a portable disc, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any appropriate combination of the above.

[0191] The above describes the basic principles of the present disclosure in conjunction with specific embodiments, but it should be noted that the advantages, benefits, effects and the like mentioned in the present disclosure are merely examples and are not limiting, and these advantages, benefits, effects and the like cannot be considered as necessary for each embodiment of the present disclosure. In addition, the above specific details are merely for the purpose of example and understanding, and are not limiting, and the above details do not limit the present disclosure to be necessarily implemented with the above specific details.

[0192] Each embodiment in the specification is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between each embodiment can be mutually referred to. For system embodiments, since they basically correspond to method embodiments, the description is relatively simple, and the relevant parts can be referred to the part of the method embodiment.

[0193] The block diagrams of the devices, apparatuses, equipment, systems involved in the present disclosure are merely exemplary examples and are not intended to require or imply the connection, arrangement, configuration shown in the block diagram. As those skilled in the art will recognize, these devices, apparatuses, equipment, systems can be connected, arranged, configured in any manner. Words such as "include", "contain", "have" and the like are open-ended words, which mean "including but not limited to", and can be used interchangeably. The words "or" and "and" used herein mean the word "and / or", and can be used interchangeably unless the context clearly indicates otherwise. The word "such as" used herein means the phrase "such as but not limited to", and can be used interchangeably.

[0194] The methods and apparatuses of the present disclosure can be implemented in many ways. For example, the methods and apparatuses of the present disclosure can be implemented by software, hardware, firmware, or any combination of software, hardware, firmware. The above order of steps for the method is merely for illustration, and the steps of the method of the present disclosure are not limited to the above specific description, unless otherwise specifically described. In addition, in some embodiments, the present disclosure can also be implemented as programs recorded in recording media, which include machine-readable instructions for implementing the method according to the present disclosure. Therefore, the present disclosure also covers the recording media storing the programs for executing the method according to the present disclosure.

[0195] It should also be noted that in the apparatuses, equipment and methods of the present disclosure, each component or step can be decomposed and / or recombined. These decompositions and / or recombinations should be considered as equivalent solutions of the present disclosure.

[0196] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein can be applied to other aspects without departing from the scope of the disclosure. Thus, the present disclosure is not intended to be limited to the aspects shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0197] The above description has been presented to enable any person skilled in the art to make or use the disclosure. Furthermore, the purpose of the above description is not intended to limit the embodiments of the present disclosure to the form disclosed herein. Although various example aspects and embodiments have been discussed above, those of ordinary skill in the art will appreciate a variety of modifications, alternatives, permutations, additions, and sub-combinations of the described aspects and embodiments.

Claims

1. A pixel unit for an image sensor, characterized in that, The application relates to a pixel circuit, which comprises a photodiode, a charge transfer module, a reset transistor, a mode control transistor, a first output module and a second output module. One end of the photodiode is grounded, and the other end is connected with the mode control transistor and the charge transfer module. One end of the charge transfer module is connected with the photodiode, and the other end is connected with the reset transistor and the first output module. The source end of the reset transistor is connected with a power supply signal, the drain end is connected with the charge transfer module and the first output module, and the gate end receives a reset signal. The source end of the mode control transistor is connected with the other end of the photodiode, the drain end is connected with the second output module, and the gate end receives a mode control signal. One end of the first output module is connected with the charge transfer module and the drain end of the reset transistor, and the other end outputs a first signal. One end of the second output module is connected with the drain end of the mode control transistor, and the other end outputs a second signal. The charge transfer module comprises a first capacitor, a second capacitor, a first switch transistor and a second switch transistor.

2. The pixel cell of claim 1, wherein, One end of the first capacitor is grounded, the other end is connected with the photodiode through the first switch transistor, and is connected with the second capacitor through the second switch transistor. One end of the second capacitor is grounded, the other end is connected with the drain end of the reset transistor, and is connected with the first capacitor through the second switch transistor. The first output module comprises a source follower transistor and a readout transistor.

3. The pixel cell of claim 1, wherein, The source end of the source follower transistor is connected with a power supply signal, the drain end is connected with the readout transistor, and the gate end is connected with the charge transfer module. The drain end of the readout transistor is connected with the drain end of the source follower transistor, the source end outputs the first signal as a first output end of a pixel unit, and the gate end receives a row selection signal. The second output module comprises a comparator and a pulse readout control circuit.

4. The pixel cell of claim 1, wherein, The negative input end of the comparator is connected with the drain end of the mode control transistor, the positive input end receives a reference signal, and the output end is connected with the input end of the pulse readout control circuit. The input end of the pulse readout control circuit is connected with the output end of the comparator, and the output end outputs the second signal. The pulse readout control circuit comprises a first logic circuit, a second logic circuit and a third switch transistor.

5. The pixel cell of claim 4, wherein, The first input end of the first logic circuit is connected with the output end of the comparator, the second input end of the first logic circuit receives an enable signal, the output end is connected with the second logic circuit and the gate end of the third switch transistor, outputs a third signal to the third switch transistor and the second logic circuit; The first input end of the second logic circuit is connected with the output end of the first logic circuit, the second input end of the second logic circuit receives the enable signal, and the output end outputs the second signal; The source end of the third switch transistor is connected with a power supply signal, the drain end is a request output end, and the gate end is connected with the output end of the first logic circuit. ​ 6. The pixel cell of claim 5, wherein, The first logic circuit comprises a NOT gate, a first NAND gate, a second NAND gate and a third NAND gate; The input end of the NOT gate receives the enable signal, and the output end of the NOT gate is connected with the second input end of the second NAND gate; The first input end of the first NAND gate is connected with the output end of the comparator, the second input end of the first NAND gate is connected with the output end of the second NAND gate, and the output end of the first NAND gate is connected with the first input end of the second NAND gate and the second input end of the third NAND gate; The first input end of the third NAND gate is connected with the output end of the comparator, and the output end is connected with the second logic circuit and the gate end of the third switch transistor.

7. The pixel cell of claim 5, wherein, The second logic circuit comprises a fourth NAND gate, a fifth NAND gate and a fourth switch transistor; The first input end of the fourth NAND gate is connected with the output end of the first logic circuit, the second input end of the fourth NAND gate is connected with the output end of the fifth NAND gate, and the output end of the fourth NAND gate is connected with the first input end of the fifth NAND gate and the drain end of the fourth switch transistor; The second input end of the fifth NAND gate receives the enable signal; The gate end of the fourth switch transistor receives the enable signal, and the source end of the fourth switch transistor serves as the output end of the second logic circuit.

8. The pixel cell of any of claims 1-7, wherein, The photodiode, the charge transfer module, the reset transistor, the mode control transistor and the first output module are prepared on a first chip, and the second output module is prepared on a second chip; the first chip is arranged on the upper layer of the second chip, and copper interconnection is provided between the first chip and the second chip.

9. A signal processing device, characterized by Comprise: a pixel array composed of n columns and m rows of image sensor pixel units according to any one of claims 1-8, a timing exposure circuit, a pulse coding circuit and a dual-mode data fusion module; m and n are integers greater than 1; The pixel array is connected with the timing exposure circuit and the pulse coding circuit; One end of the timing exposure circuit is connected with the pixel array, and the other end is connected with the dual-mode data fusion module; One end of the pulse coding circuit is connected with the pixel array, and the other end is connected with the dual-mode data fusion module; The input end of the dual-mode data fusion module is connected with the timing exposure circuit and the pulse coding circuit, and the output end outputs the image information of the pixel array.

10. The apparatus of claim 9, wherein, The timing exposure circuit is arranged at a first position on a second chip, and the pulse coding circuit and the dual-mode data fusion module are arranged at a second position on the second chip; the distance between the first position and the second position is greater than a preset distance.

11. The apparatus of claim 9, wherein, The timing exposure circuit is arranged on a second chip, and the pulse coding circuit and the dual-mode data fusion module are arranged on a third chip.

12. The apparatus of any of claims 9-11, wherein, The timing exposure circuit comprises a row drive control module, a column readout module and a first coding module; The row drive control module is connected with the image sensor pixel units in the pixel array row by row; The n inputs of the column readout module are connected with the image sensor pixel units in the pixel array column by column, and the output is connected with the first encoding module; The input of the first encoding module is connected with the column readout module, the output is connected with the dual-mode data fusion module, and is used for outputting a first encoding signal.

13. The apparatus of any of claims 9-11, wherein, The pulse encoding circuit comprises a row arbitration module, a column address encoder, a row address encoder and a second encoding module; The row arbitration module is connected with the image sensor pixel units in the pixel array row by row, and is connected with the row address encoder; The n inputs of the column address encoder are connected with the image sensor pixel units in the pixel array column by column, and the output is connected with the second encoding module; The input of the row address encoder is connected with the row arbitration module, and the output is connected with the second encoding module; The input of the second encoding module is connected with the row arbitration module, the row address encoder and the column address encoder, the output is connected with the dual-mode data fusion module, and is used for outputting a pulse encoding signal.

14. An electronic device, comprising: The image sensor pixel unit or the signal processing device is connected with the processor in communication, and the memory stores computer execution instructions. The memory stores computer execution instructions. The processor executes the computer execution instructions stored in the memory to control the image sensor pixel unit or the signal processing device.

15. The apparatus of claim 14, wherein, The electronic device is included in any one of the following: image data acquisition equipment, audio / video player, navigation device, entertainment device, communication device, roadside traffic facility, device in motor vehicle, industrial detection device, flight device, medical device, security device.

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