Pixel unit circuit for dynamic vision sensor

Abstract

The invention discloses a pixel unit circuit for a dynamic vision sensor. The pixel unit circuit comprises a photodiode, an IV conversion circuit, a switched capacitor amplifier, a comparison circuit and a pixel readout logic circuit, the switched capacitor amplifier comprises a first capacitor, a second capacitor, an operational amplifier and a reset switch tube, the first capacitor is connected between the output end of the IV conversion circuit and the inverted input end of the operational amplifier, the in-phase input end of the operational amplifier is connected with a reference power supply, and the output end of the operational amplifier serves as the output end of the switched capacitor amplifier; the operational amplifier is connected with the comparison circuit, the second capacitor is connected between the inverted input end and the output end of the operational amplifier, the drain electrode and the source electrode of the reset switch tube are connected with the inverted input end and the output end of the operational amplifier respectively, and the substrate of the reset switch tube is connected with the output end of the switched capacitor amplifier; the comparison circuit is used for outputting event signals; and the pixel read-out logic circuit is used for reading out the event signal and is connected with the grid electrode of the reset switch tube.

Description

Technical Field

[0001] This invention relates to the field of electronic circuit technology, and more specifically to a pixel unit circuit for a dynamic vision sensor. Background Technology

[0002] Dynamic Vision Sensors (DVS), also known as Event-based Vision Sensors (EVS), are widely used in object tracking, deblurring, and 3D detection. DVS mimics the information processing mechanism of the biological retina, independently detecting changes in light intensity at the pixel level. When the light intensity change exceeds a preset threshold, it generates an event stream containing information about pixel position, time, and polarity (brightening or darkening). This event-driven asynchronous mechanism allows DVS to efficiently capture dynamic scene information while ignoring static backgrounds, significantly reducing data redundancy. Currently, in DVS, a current path exists between the substrate and source terminals of the reset switch of the switched-capacitor amplifier used to detect changes in ambient light. When the ambient light intensity remains unchanged, the switched-capacitor amplifier is in its refractory period, the reset switch is off, and a voltage difference exists between the substrate and the connected power supply. At this time, charge leaks through the substrate-source path to the power supply, forming a leakage current. This causes the output voltage of the switched-capacitor amplifier to gradually decrease until it falls below a preset threshold, triggering the subsequent threshold comparator and generating false events, affecting the reliability of the DVS output data. Summary of the Invention

[0003] This invention provides a pixel unit circuit for a dynamic vision sensor to solve the technical problem of periodic false events caused by leakage current in the switched capacitor amplifier of current dynamic vision sensors.

[0004] To address the aforementioned problems, this invention provides a pixel unit circuit for a dynamic vision sensor, comprising a photodiode, an IV conversion circuit, a switched-capacitor amplifier, a comparator circuit, and a pixel readout logic circuit connected in sequence; wherein, The photodiode is used to receive ambient light and generate photocurrent; The IV conversion circuit is used to convert the photocurrent to generate a photovoltage; The switched-capacitor amplifier is used to sample and amplify the photovoltage. The switched-capacitor amplifier includes a first capacitor, a second capacitor, an operational amplifier, and a reset switch. The first capacitor is connected between the output terminal of the IV conversion circuit and the inverting input terminal of the operational amplifier. The non-inverting input terminal of the operational amplifier is connected to a reference power supply. The output terminal of the operational amplifier serves as the output terminal of the switched-capacitor amplifier and is connected to the comparator circuit. The second capacitor is connected between the inverting input terminal and the output terminal of the operational amplifier. The drain and source of the reset switch are respectively connected to the inverting input terminal and the output terminal of the operational amplifier, and the substrate of the reset switch is connected to the output terminal of the switched-capacitor amplifier. The comparison circuit is used to compare the amplified photovoltage with a preset voltage threshold and output an event signal; The pixel readout logic circuit is connected to the output of the comparison circuit to read out the event signal. The output of the pixel readout logic circuit is connected to the gate of the reset switch in the switched capacitor amplifier to reset the output of the switched capacitor amplifier after the event signal is read out.

[0005] The further technical solution is as follows: the IV conversion circuit includes a transimpedance amplifier, a second MOS transistor, and a third MOS transistor. The inverting input terminal of the transimpedance amplifier is connected to the cathode of the photodiode and the source of the third MOS transistor. The gate of the third MOS transistor is connected to its drain and then to the source of the second MOS transistor. The drain and gate of the second MOS transistor are respectively connected to the power supply VCC and the output terminal of the transimpedance amplifier. The output terminal of the transimpedance amplifier serves as the output terminal of the IV conversion circuit and is connected to the first capacitor. The non-inverting input terminal of the transimpedance amplifier is connected to the power supply Vd. The anode of the photodiode is grounded.

[0006] The further technical solution is as follows: the pixel unit circuit further includes a first level conversion circuit and a second level conversion circuit, wherein, The first level conversion circuit is connected between the output of the comparator circuit and the input of the pixel readout logic circuit to perform level conversion on the event signal; The second level conversion circuit is connected between the output of the pixel readout logic circuit and the gate of the reset switch in the switched capacitor amplifier.

[0007] The further technical solution is as follows: the first level conversion circuit includes a fifth NMOS transistor, a fifth PMOS transistor, a sixth NMOS transistor, and a sixth PMOS transistor, wherein, The sources of the fifth and sixth PMOS transistors are both connected to the power supply VDD. The gate of the fifth NMOS transistor is connected to the gate of the fifth PMOS transistor and serves as the input terminal of the first level conversion circuit, which is connected to the output terminal of the comparator circuit. The drain of the fifth NMOS transistor is connected to the drain of the fifth PMOS transistor, the gate of the sixth NMOS transistor, and the gate of the sixth PMOS transistor. The drain of the sixth NMOS transistor is connected to the drain of the sixth PMOS transistor and serves as the output terminal of the first level conversion circuit, which is connected to the input terminal of the pixel readout logic circuit. The sources of the fifth and sixth NMOS transistors are both grounded.

[0008] Its further technical solution is as follows: the second level conversion circuit includes a first NMOS transistor, a first PMOS transistor, a second NMOS transistor, a second PMOS transistor, a third NMOS transistor, a third PMOS transistor, a fourth NMOS transistor, and a fourth PMOS transistor, wherein, The sources of the first, second, third, and fourth PMOS transistors are all connected to the power supply VDD. The gate of the first NMOS transistor is connected to the gates of the first PMOS transistor and the third NMOS transistor, and serves as the input terminal of the second level conversion circuit, connected to the output terminal of the pixel readout logic circuit. The drain of the first NMOS transistor is connected to the drain of the first PMOS transistor and connected to the gate of the second NMOS transistor. The drain of the second NMOS transistor is connected to the drain of the second PMOS transistor and the gate of the third PMOS transistor. The gate of the second PMOS transistor is connected to the drain of the third NMOS transistor and the third PMOS transistor, and connected to the gates of the fourth NMOS transistor and the fourth PMOS transistor. The drain of the fourth NMOS transistor is connected to the drain of the fourth PMOS transistor, and serves as the output terminal of the second level conversion circuit, connected to the gate of the reset switch in the switched capacitor amplifier. The sources of the first, second, third, and fourth NMOS transistors are all grounded.

[0009] The further technical solution is as follows: the pixel unit circuit further includes a voltage follower circuit, the voltage follower circuit includes a first MOS transistor, the gate of the first MOS transistor is connected to the output terminal of the IV conversion circuit, the drain and source of the first MOS transistor are respectively connected to power supply VCC and ground, and the source of the first MOS transistor serves as the output terminal of the voltage follower circuit, the first capacitor is connected between the output terminal of the voltage follower circuit and the inverting input terminal of the operational amplifier; the comparison circuit includes a first comparator and a second comparator, one input terminal of the first comparator and the second comparator are both connected to the output terminal of the switched capacitor amplifier, the other input terminal of the first comparator and the second comparator respectively receive a high preset voltage threshold and a low preset voltage threshold, and the output terminal of the first comparator and the second comparator serves as the output terminal of the comparison circuit, used to output a bright event signal and a dark event signal.

[0010] Its further technical solution is as follows: the pixel readout logic circuit includes an event holding module, an event storage module, a restart logic module, and a reset logic module, wherein, The event holding module is connected to the output of the comparison circuit and is used to receive and temporarily store event signals from the comparison circuit. The event storage module is connected to the output of the event holding module, and is used to store the event signal and output the event signal synchronously after storage; The restart logic module is connected to the output of the event storage module and is used to determine whether there is an event to be read in the event storage module. The reset logic module is connected to the output of the restart logic module and the event holding module, and is used to reset the event holding module when there is an event to be read. It is also connected to the gate of the reset switch transistor, and is used to reset the output of the switched capacitor amplifier after an event to be read is read.

[0011] The further technical solution is as follows: the event holding module includes a latch circuit, the latch circuit includes two first D latches, the data input terminals of the two first D latches are connected to the output terminal of the comparison circuit for receiving the event signal, the clock input terminals of the two first D latches are connected to the output terminal of the reset logic module, and the data output terminal of one of the first D latches and the inverted output terminal of the other first D latch serve as the output terminal of the event holding module and are connected to the event storage module.

[0012] The further technical solution is as follows: the event storage module includes two second D latches and a bus readout circuit. The bus readout circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. The data input terminals of the two second D latches are connected to the output terminals of the event holding module. The clock input terminals of the two second D latches receive external sampling signals. The data output terminals of the two second D latches are both connected to the gates of the first transistor and the second transistor. The source of the first transistor is connected to the source of the second transistor. The drains of the first transistor and the second transistor are respectively connected to the sources of the third transistor and the fourth transistor. The gates of the third transistor and the fourth transistor receive external column select signals. The drains of the third transistor and the fourth transistor serve as the output terminals of the bus readout circuit for synchronously outputting the event signals. The inverted output terminals of the two second D latches are connected to the restart logic module.

[0013] The further technical solution is as follows: The restart logic module includes a first NAND gate and a third D latch, wherein the two input terminals of the first NAND gate are connected to the inverted output terminals of two second D latches, the output terminal of the first NAND gate is connected to the clock input terminal of the third D latch, the data input terminal of the third D latch receives an external restart signal, and the inverted output terminal of the third D latch serves as the output terminal of the restart logic module and is connected to the reset logic module; the reset logic module includes an OR gate and a second NAND gate, wherein the two input terminals of the OR gate are connected to the output terminal of the event holding module, the output terminal of the OR gate is connected to one input terminal of the second NAND gate, the other input terminal of the second NAND gate is connected to the output terminal of the restart logic module, and the output terminal of the second NAND gate serves as the output terminal of the reset logic module, outputting a reset signal to the event holding module and the switched capacitor amplifier.

[0014] Compared with existing technologies, the pixel unit circuit of this invention for a dynamic vision sensor utilizes a photodiode to receive ambient light and generate photocurrent. This photocurrent is then converted to photovoltage by an IV conversion circuit. The photovoltage is sampled and amplified by a switched-capacitor amplifier and passed through a comparator circuit to generate and output an event signal. Once an event signal is generated, the pixel readout logic circuit outputs the event signal and a reset signal to the gate of the final reset switch of the switched-capacitor amplifier. At this time, the second capacitor is short-circuited, and the output of the operational amplifier is forced to the reset level, thereby resetting the output signal. This ensures that the switched-capacitor amplifier can respond to the next event in a timely manner, ensuring the independence and accuracy of each signal acquisition. Because the substrate of the reset switch transistor of the switched-capacitor amplifier is directly connected to the output terminal of the switched-capacitor amplifier, the substrate potential changes dynamically with the output signal, thereby eliminating voltage differences, effectively suppressing the generation of substrate leakage current, reducing the interference of charge injection on the output signal, significantly reducing the frequency of periodic false events, and improving the reliability of the output data of the dynamic vision sensor. Attached Figure Description

[0015] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a schematic circuit block diagram of a pixel unit circuit for a dynamic vision sensor provided in an embodiment of the present invention.

[0017] Figure 2 yes Figure 1 The diagram shows the specific circuit diagram of the switched capacitor amplifier in the pixel unit circuit.

[0018] Figure 3 yes Figure 1 The diagram shows the specific circuit diagram of the IV conversion circuit in the pixel unit circuit shown.

[0019] Figure 4 yes Figure 1 The diagram shows the specific circuit diagram of the first level conversion circuit in the pixel unit circuit shown.

[0020] Figure 5 yes Figure 1 The diagram shows the specific circuit diagram of the second level conversion circuit in the pixel unit circuit shown.

[0021] Figure 6 yes Figure 1 The diagram shows the specific circuit diagram of the pixel readout logic circuit in the pixel unit circuit shown.

[0022] Figure 7 yes Figure 1 The diagram shows the timing waveform of the pixel unit circuit. Detailed Implementation

[0023] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0024] It should be understood that, when used in this specification and the appended claims, the terms “comprising” and “including” indicate the presence of the described features, integrals, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, operations, elements, components and / or collections thereof.

[0025] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used in this specification and the appended claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes such combinations.

[0026] Reference Figures 1 to 6 , Figures 1 to 6A specific embodiment of the pixel unit circuit for a dynamic vision sensor according to the present invention is shown. In the embodiment shown in the figures, the pixel unit circuit for the dynamic vision sensor includes a photodiode D11, an IV conversion circuit 10, a voltage follower circuit 20, a switched-capacitor amplifier 30, a comparator circuit 40, and a pixel readout logic circuit 50 connected in sequence. The photodiode D11 is used to receive ambient light and generate a photocurrent; the IV conversion circuit 10 is used to convert the photocurrent to generate a photovoltage; the voltage follower circuit 20 is used to buffer the photovoltage output by the IV conversion circuit 10; the switched-capacitor amplifier 30 is used to sample and amplify the photovoltage; the comparator circuit 40 is used to compare the amplified photovoltage with a preset voltage threshold and output an event signal; the pixel readout logic circuit 50 is connected to the output terminal of the comparator circuit 40 and is used to read out the event signal, and the output terminal of the pixel readout logic circuit 50 is connected to the switched-capacitor amplifier 30 to perform a sampling and amplification of the photovoltage after the event signal is read out. The output of the switched-capacitor amplifier 30 is reset. Specifically, the switched-capacitor amplifier 30 includes a first capacitor C1, a second capacitor C2, an operational amplifier U2, and a reset switch Q15. The reset switch Q15 is a PMOS transistor. The first capacitor C1 is connected between the output terminal of the voltage follower circuit 20 and the inverting input terminal of the operational amplifier U2. The non-inverting input terminal of the operational amplifier U2 is connected to the reference power supply V. The output terminal of the operational amplifier U2 serves as the output terminal of the switched-capacitor amplifier 30 and is connected to the comparator circuit 40. The second capacitor C2 is connected between the inverting input terminal and the output terminal of the operational amplifier U2. The gate of the reset switch Q15 is connected to the output terminal of the pixel readout logic circuit 50. The drain and source of the reset switch Q15 are respectively connected to the inverting input terminal and the output terminal of the operational amplifier U2, and the substrate of the reset switch Q15 is connected to the output terminal of the switched-capacitor amplifier 30. Testing revealed that the leakage current of the reset switch Q15 in the switched capacitor amplifier 30 of this invention can be as low as 2.01 fA, while the leakage current of the switched capacitor amplifier in the traditional pixel unit circuit typically reaches 1.6 PA. The background noise frequency of the switched capacitor amplifier of this invention can be reduced from 86 Hz in the traditional switched capacitor amplifier in the pixel unit circuit to 1.4 Hz. It can be seen that the design of the switched capacitor amplifier 30 of this invention effectively suppresses the generation of substrate leakage current and reduces the interference of charge injection on the output signal.

[0027] Based on the above design, the amplification factor of the switched-capacitor amplifier 30 is determined by the ratio of the first capacitor C1 to the second capacitor C2, allowing for precise gain control. Simultaneously, the linear characteristics of the capacitors ensure the accuracy of signal amplification. The switched-capacitor amplifier 30 achieves high-precision amplification and periodic reset of the input signal through alternating switching between operating and reset states. In operating state, the switched-capacitor amplifier 30 integrates and amplifies the input photovoltage, providing a stable signal for subsequent circuits. When the pixel readout logic circuit 50 outputs signal NRST=0 to the gate of the reset switch Q15, the switched-capacitor amplifier 30 enters the reset state. At this time, the second capacitor C2 is short-circuited, and the output of the operational amplifier U2 is forcibly pulled to the reset level, thereby resetting the output signal and enabling it to respond promptly to the next event, ensuring the independence and accuracy of each signal acquisition. Furthermore, the substrate of the reset switch Q15 is directly connected to the output terminal of the switched capacitor amplifier 30, which allows the substrate potential to change dynamically with the output signal. This effectively suppresses the generation of substrate leakage current, reduces the interference of charge injection on the output signal, significantly reduces the frequency of periodic false events, improves the reliability of the output data of the dynamic vision sensor, and the circuit structure is relatively simple.

[0028] like Figure 3 As shown, the IV conversion circuit 10 includes a transimpedance amplifier U1, a second MOSFET Q2, and a third MOSFET Q3. The inverting input of the transimpedance amplifier U1 is connected to the cathode of the photodiode D11 and the source of the third MOSFET Q3. The gate of the third MOSFET Q3 is connected to its drain and then to the source of the second MOSFET Q2. The drain and gate of the second MOSFET Q2 are connected to the power supply VCC and the output of the transimpedance amplifier U1, respectively. The output of the transimpedance amplifier U1 serves as the output of the IV conversion circuit 10. Through the voltage follower circuit 20, it is connected to the first capacitor C1 of the switched capacitor amplifier 30. The non-inverting input of the transimpedance amplifier U1 is connected to the power supply Vd. In this embodiment, the power supply Vd can be 1.2V. The anode of the photodiode D11 is grounded. Understandably, the IV conversion circuit 10 converts the photocurrent generated by the photodiode D11 into a logarithmic voltage signal. A feedback resistor can be connected between the output and inverting input of the transimpedance amplifier U1, and a feedback capacitor can also be connected in parallel. Based on the above design, a third MOS transistor Q3 is added to the feedback path of the transimpedance amplifier U1, which increases the overall resistance of the feedback path and improves the gain. Without reducing the sensitivity, the capacitor size in the switched capacitor amplifier 30 can be reduced, thereby reducing the overall size of the pixel unit circuit.

[0029] Furthermore, in some embodiments, the voltage follower circuit 20 includes a first MOSFET Q9, the gate of which is connected to the output terminal of the IV conversion circuit 10, the drain and source of which are connected to the power supply VCC and ground respectively, and the source of which serves as the output terminal of the voltage follower circuit 20 and is connected to the first capacitor C1 of the switched capacitor amplifier 30.

[0030] In this embodiment, the comparison circuit 40 is used to determine the event threshold. It compares the amplified optical voltage with a high preset voltage threshold VH and a low preset voltage threshold VL, respectively, and outputs a bright event signal CON and a dark event signal NCON. Specifically, if the optical voltage is greater than the high preset voltage threshold VH, a brightening event (i.e., bright event signal CON) is output; if it is less than the low preset voltage threshold VL, a darkening event (i.e., dark event signal NCON) is output. Figure 1 As shown, the comparison circuit 40 includes a first comparator A1 and a second comparator A2. One input terminal of the first comparator A1 and the second comparator A2 are both connected to the output terminal of the switched capacitor amplifier 30. The other input terminals of the first comparator A1 and the second comparator A2 respectively receive a high preset voltage threshold VH and a low preset voltage threshold VL. The output terminals of the first comparator A1 and the second comparator A2 serve as the output terminals of the comparison circuit 40, used to output a bright event signal CON and a dark event signal NCON.

[0031] Continue to refer to Figure 1 , Figure 4 and Figure 5 Furthermore, in some embodiments, the pixel unit circuit further includes a first level conversion circuit 60 and a second level conversion circuit 70. The first level conversion circuit 60 is connected between the output of the comparator circuit 40 and the input of the pixel readout logic circuit 50 to perform level conversion on the event signal. The second level conversion circuit 70 is connected between the output of the reset logic module 54 and the gate of the reset switch transistor Q15 in the switched capacitor amplifier 30. As can be seen from the above, the pixel unit circuit for a dynamic vision sensor of the present invention includes an analog section composed of a photodiode D11, an IV conversion circuit 10, a voltage follower circuit 20, a switched capacitor amplifier 30, and a comparator circuit 40, and a digital section composed of the pixel readout logic circuit 50. In the present invention, the first level conversion circuit 60 and the second level conversion circuit 70 can separate the voltage domains of the front-end analog section and the digital section, reducing the power supply voltage of the digital section and thus reducing power consumption.

[0032] Preferably, in this embodiment, the first level conversion circuit 60 is a high-level to low-level circuit, which can not only separate the voltage domains of the analog and digital parts of the front end, but also be used for waveform shaping of the brightening and darkening events output by the analog part. Figure 4 As shown, the first level conversion circuit 60 includes a fifth PMOS transistor Q31, a fifth NMOS transistor Q32, a sixth PMOS transistor Q33, and a sixth NMOS transistor Q34. The sources of the fifth PMOS transistor Q31 and the sixth PMOS transistor Q33 are both connected to the power supply VDD. The gate of the fifth PMOS transistor Q31 is connected to the gate of the fifth NMOS transistor Q32 and serves as the input terminal of the first level conversion circuit 60, which is connected to the output terminal of the comparator circuit 40. The drain of the fifth PMOS transistor Q31 is connected to the drain of the fifth NMOS transistor Q32, the gate of the sixth PMOS transistor Q33, and the gate of the sixth NMOS transistor Q34. The drain of the sixth PMOS transistor Q33 is connected to the drain of the sixth NMOS transistor Q34 and serves as the output terminal of the first level conversion circuit 60, which is connected to the input terminal of the pixel readout logic circuit 50. The sources of the fifth NMOS transistor Q32 and the sixth NMOS transistor Q34 are both grounded. In this embodiment, the first level conversion circuit 60 is composed of multiple NMOS transistors and PMOS transistors, which can smoothly convert a high level to a low level.

[0033] Specifically, such as Figure 5As shown, in this embodiment, the second level conversion circuit 70 is a low-level to high-level circuit, including a first PMOS transistor Q21, a first NMOS transistor Q22, a second PMOS transistor Q23, a second NMOS transistor Q24, a third PMOS transistor Q25, a third NMOS transistor Q26, a fourth PMOS transistor Q27, and a fourth NMOS transistor Q28. The sources of the first PMOS transistor Q21, the second PMOS transistor Q23, the third PMOS transistor Q25, and the fourth PMOS transistor Q27 are all connected to the power supply VDD. The gate of the first PMOS transistor Q21 is connected to the gates of the first NMOS transistor Q22 and the third NMOS transistor Q26, and serves as the input terminal of the second level conversion circuit 70, connected to the output terminal of the pixel readout logic circuit 50. The drain of the first PMOS transistor Q21 is connected to the first... The drain of NMOS transistor Q22 is connected to the gate of the second NMOS transistor Q24. The drain of the second NMOS transistor Q24 is connected to the drain of the second PMOS transistor Q23 and the gate of the third PMOS transistor Q25. The gate of the second PMOS transistor Q23 is connected to the drain of the third PMOS transistor Q25 and the third NMOS transistor Q26, and is also connected to the gates of the fourth PMOS transistor Q27 and the fourth NMOS transistor Q28. The drain of the fourth PMOS transistor Q27 is connected to the drain of the fourth NMOS transistor Q28 and serves as the output terminal of the second level conversion circuit 70, connected to the gate of the reset switch transistor Q15 in the switched capacitor amplifier 30. The sources of the first NMOS transistor Q22, the second NMOS transistor Q24, the third NMOS transistor Q26, and the fourth NMOS transistor Q28 are all grounded. In this embodiment, the second level conversion circuit 70, composed of multiple NMOS transistors and PMOS transistors, can achieve a smooth transition from low to high level.

[0034] In some embodiments, the pixel readout logic circuit 50 includes an event holding module 51, an event storage module 52, a restart logic module 53, and a reset logic module 54. The output of the comparison circuit 40 is connected to the event holding module 51 via the first level conversion circuit 60. The event holding module 51 receives and temporarily stores event signals from the comparison circuit 40. The event storage module 52 is connected to the output of the event holding module 51 and stores the event signals, then synchronously outputs the stored event signals. The restart logic module 53 is connected to the output of the event storage module 52 and determines whether an event to be read exists in the event storage module 52. The reset logic module 54 is connected to the output of the restart logic module 53 and the event holding module 51, resetting the event holding module 51 when an event to be read exists. It is also connected to the gate of the reset switch transistor Q15 in the switched capacitor amplifier 30 via the second level conversion circuit 70, resetting the output of the switched capacitor amplifier 30 after an event to be read is read. Based on the above design, when an event signal is generated, the pixel readout logic circuit 50 of the modular logic architecture synchronously stores and outputs the event signal in a sequential scanning synchronous readout manner. This avoids the priority judgment and conflict delay in the existing arbitration-type asynchronous readout mechanism, greatly reduces the readout delay, improves the pixel readout efficiency, and realizes efficient readout and management of events.

[0035] Continue to refer to Figure 1 and Figure 6 In some embodiments, the event holding module 51 includes a latch circuit, which includes two first D latches D1. The outputs of the first comparator A1 and the second comparator A2 are respectively connected to the data inputs of the two first D latches D1 through the first level conversion circuit 60. The two first D latches D1 are respectively used to receive a bright event signal CON and a dark event signal NCON. The clock inputs of the two first D latches D1 are connected to the output of the reset logic module 54, and the data output of one first D latch D1 and the inverted output of the other first D latch D1 serve as the outputs of the event holding module 51, connected to the event storage module 52. Figure 6 As shown, the two first D latches D1 output signals KON and KOFF respectively, representing the temporarily stored brightening and darkening events. Based on the above design, the event holding module 51 ensures that the event signal can be stably saved before being read out through the latching mechanism, avoiding the problem of false triggering caused by signal loss or jitter in traditional designs.

[0036] In some embodiments, the event storage module 52 includes two second D latches D2 and a bus readout circuit. The data input of one second D latch D2 is connected to the data output of a first D latch D1, and the data input of the other second D latch D2 is connected to the inverted output of the other D latch D1. The clock inputs of both second D latches D2 receive an external sampling signal SAMPLE, and the data outputs of both second D latches D2 are connected to the bus readout circuit, enabling the bus readout circuit to operate and synchronously output the event signal. The inverted outputs of the two second D latches D2 are connected to the restart logic module 53. Based on this design, the event storage module 52 stores the event signal in the event holding module 51 into the pixel according to the sampling signal SAMPLE for subsequent synchronous readout.

[0037] Preferably, in this embodiment, the bus readout circuit includes a first transistor Q11, a second transistor Q12, a third transistor Q13, and a fourth transistor Q14. The gates of the first transistor Q11 and the second transistor Q12 are connected to the data output terminals of the two second D latches D2. The source of the first transistor Q11 is connected to the source of the second transistor Q12. The drains of the first transistor Q11 and the second transistor Q12 are respectively connected to the sources of the third transistor Q13 and the fourth transistor Q14. The gate of transistor 4 receives the external column select signal YSEL. The drains of the third transistor Q13 and the fourth transistor Q14 serve as the output terminals of the bus readout circuit, used to synchronously output the event signals. Specifically, the first transistor Q11, the second transistor Q12, the third transistor Q13, and the fourth transistor Q14 are all NMOS transistors. The drains of the third transistor Q13 and the fourth transistor Q14 output signals NONBL and NOFFBL, respectively. Understandably, signals NONBL and NOFFBL represent the bright event signal CON and the dark event signal NCON, respectively. Based on the above design, the bus readout circuit utilizes the switching characteristics of NMOS transistors to achieve message transmission, thereby realizing synchronous pixel readout. Figure 6 As shown, when SAMPLE=1, KON and KOFF in the event holding module 51 are stored to obtain MON, MOFF, NMON, and NMOFF; when SAMPLE=0, MON, MOFF, NMON, and NMOFF remain unchanged, and the output of the external column select signal YSEL and the MON and MOFF control signals NONBL and NOFFBL is transmitted. When YSEL=1 and MON or MOFF=1, NONBL or NOFFBL=0; otherwise, NONBL and NOFFBL=1.

[0038] like Figure 6 As shown, in some embodiments, the restart logic module 53 includes a first NAND gate NAND1 and a third D latch D3. The two inputs of the first NAND gate NAND1 are connected to the inverted outputs of two second D latches D2. The output of the first NAND gate NAND1 is connected to the clock input of the third D latch D3, outputting a signal ME (event presence flag). The data input of the third D latch D3 receives an external restart signal RESTART. The inverted output of the third D latch D3 serves as the output of the restart logic module 53, connected to the reset logic module 54, outputting a signal KEN (event storage completion signal). The KEN signal triggers the reset logic module 54, completing the reset and restart of the pixel unit circuit. Specifically, when NMON or NMOFF = 0, ME = 1; otherwise, ME = 0. When ME = 1 and RESTART = 1, KEN = 0; when ME = 1 and RESTART = 0, KEN = 1; when ME = 0, KEN remains unchanged.

[0039] In some embodiments, the reset logic module 54 includes an OR gate OR1 and a NAND gate NAND2. The two inputs of the OR gate OR1 are connected to the output of the event holding module 51, and the output of the OR gate OR1 is connected to one input of the second NAND gate NAND2. The other input of the second NAND gate NAND2 is connected to the inverted output of the third D latch D3. The output of the second NAND gate NAND2 serves as the output of the reset logic module 54, outputting a reset signal NRST to the clock inputs of the two first D latches D1 and the input of the second level conversion circuit 70. When an event in the event holding module 51 is successfully stored, the reset logic module 54 generates the NRST signal. When NRST=0, the event holding module 51 is reset, and KON and KOFF remain unchanged. After the event is read out, i.e., sampling and reading are completed, when SAMPLE=0 and RESTART=1 and ME=1, NRST=1, and the pixel readout logic circuit 50 returns to normal operation to perform event threshold judgment.

[0040] Understandably, in this invention, the external sampling signal SAMPLE, the external restart signal RESTART, etc., are generated and provided by an external signal generator or an external control device. The pixel readout logic circuit 50 achieves sampling and resetting of the event signals generated and output by the analog section through the alternating enable of the SAMPLE and RESTART signals. (Refer to...) Figure 7 , Figure 7This is a timing waveform diagram of the pixel unit circuit for the dynamic vision sensor of the present invention. During the sampling period, when SAMPLE=1 and RESTART=0, the pixel readout logic circuit 50 performs sampling. If an event is output at this time (CON / NCOFF=1, making ME=1), the first D latch D1 in the event holding module 51 outputs KON / KOFF=1, and the second D latch D2 in the event storage module 52 outputs signals MON / MOFF=1 and NMOFF / NMON=0, and synchronously outputs the event through the bus readout circuit. Simultaneously, the third D latch D3 in the restart logic module 53 outputs signal KEN=1, resulting in reset RST=1 and NRST=0. The first D latch D1 is reset. At this time, the front-end analog section output signals CON and NCOFF are isolated from the back-end digital section, CON and NCOF return to a steady state (CON=0, NCOFF=1), and the potentials of the back-end KON and KOFF are locked, entering a steady state, stopping the event threshold judgment. If there is no event output, the circuit continues to operate normally and perform event threshold judgment. After sampling and event signal output, the system enters a reset cycle. When RESTART=1 and SAMPLE=0, the switched capacitor amplifier 30 is reset to prepare for the next event. If there is an event output at this time (MON / MOFF=1 makes ME=1), then KEN=0, NKEN=1, RST=0, NRST=1, and the pixel unit circuit returns to normal operation to perform event threshold judgment. If there is no event output, the circuit state remains unchanged.

[0041] In summary, the pixel unit circuit of this invention for dynamic vision sensors features high gain, low leakage current of the switched-capacitor amplifier, and high-speed synchronous event readout. Specifically, the IV conversion circuit adds a third MOS transistor to the feedback path, increasing the overall resistance and gain. Without reducing sensitivity, the capacitor size in the switched-capacitor amplifier can be reduced, thereby reducing the overall size of the pixel unit circuit. Furthermore, the direct connection between the substrate and its output in the switched-capacitor amplifier effectively suppresses substrate leakage current and reduces the occurrence of periodic false events. The modular logic architecture of the pixel readout logic circuit synchronously stores and outputs event signals using a sequential scanning synchronous readout method, avoiding the priority judgment and conflict delays of existing arbitration-based asynchronous readout mechanisms. This significantly reduces readout latency, improves pixel readout efficiency, and achieves efficient event readout and management.

[0042] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and these modifications or substitutions should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A pixel unit circuit for a dynamic vision sensor, characterized in that, The pixel unit circuit includes a photodiode, an IV conversion circuit, a switched capacitor amplifier, a comparator circuit, and a pixel readout logic circuit connected in sequence; wherein... The photodiode is used to receive ambient light and generate photocurrent; The IV conversion circuit is used to convert the photocurrent to generate a photovoltage; The switched-capacitor amplifier is used to sample and amplify the photovoltage. The switched-capacitor amplifier includes a first capacitor, a second capacitor, an operational amplifier, and a reset switch. The first capacitor is connected between the output terminal of the IV conversion circuit and the inverting input terminal of the operational amplifier. The non-inverting input terminal of the operational amplifier is connected to a reference power supply. The output terminal of the operational amplifier serves as the output terminal of the switched-capacitor amplifier and is connected to the comparator circuit. The second capacitor is connected between the inverting input terminal and the output terminal of the operational amplifier. The drain and source of the reset switch are respectively connected to the inverting input terminal and the output terminal of the operational amplifier, and the substrate of the reset switch is connected to the output terminal of the switched-capacitor amplifier. The comparison circuit is used to compare the amplified photovoltage with a preset voltage threshold and output an event signal; The pixel readout logic circuit is connected to the output of the comparison circuit to read out the event signal. The output of the pixel readout logic circuit is connected to the gate of the reset switch in the switched capacitor amplifier to reset the output of the switched capacitor amplifier after the event signal is read out.

2. The pixel unit circuit for a dynamic vision sensor as described in claim 1, characterized in that, The IV conversion circuit includes a transimpedance amplifier, a second MOSFET, and a third MOSFET. The inverting input of the transimpedance amplifier is connected to the cathode of the photodiode and the source of the third MOSFET. The gate of the third MOSFET is connected to its drain and then to the source of the second MOSFET. The drain and gate of the second MOSFET are connected to the power supply VCC and the output of the transimpedance amplifier, respectively. The output of the transimpedance amplifier serves as the output of the IV conversion circuit and is connected to the first capacitor. The non-inverting input of the transimpedance amplifier is connected to the power supply Vd. The anode of the photodiode is grounded.

3. The pixel unit circuit for a dynamic vision sensor as described in claim 1, characterized in that, The pixel unit circuit further includes a first level conversion circuit and a second level conversion circuit, wherein... The first level conversion circuit is connected between the output of the comparator circuit and the input of the pixel readout logic circuit to perform level conversion on the event signal; The second level conversion circuit is connected between the output of the pixel readout logic circuit and the gate of the reset switch in the switched capacitor amplifier.

4. The pixel unit circuit for a dynamic vision sensor as described in claim 3, characterized in that, The first level conversion circuit includes a fifth NMOS transistor, a fifth PMOS transistor, a sixth NMOS transistor, and a sixth PMOS transistor, wherein, The sources of the fifth and sixth PMOS transistors are both connected to the power supply VDD. The gate of the fifth NMOS transistor is connected to the gate of the fifth PMOS transistor and serves as the input terminal of the first level conversion circuit, which is connected to the output terminal of the comparator circuit. The drain of the fifth NMOS transistor is connected to the drain of the fifth PMOS transistor, the gate of the sixth NMOS transistor, and the gate of the sixth PMOS transistor. The drain of the sixth NMOS transistor is connected to the drain of the sixth PMOS transistor and serves as the output terminal of the first level conversion circuit, which is connected to the input terminal of the pixel readout logic circuit. The sources of the fifth and sixth NMOS transistors are both grounded.

5. The pixel unit circuit for a dynamic vision sensor as described in claim 3, characterized in that, The second level conversion circuit includes a first NMOS transistor, a first PMOS transistor, a second NMOS transistor, a second PMOS transistor, a third NMOS transistor, a third PMOS transistor, a fourth NMOS transistor, and a fourth PMOS transistor, wherein, The sources of the first, second, third, and fourth PMOS transistors are all connected to the power supply VDD. The gate of the first NMOS transistor is connected to the gates of the first PMOS transistor and the third NMOS transistor, and serves as the input terminal of the second level conversion circuit, connected to the output terminal of the pixel readout logic circuit. The drain of the first NMOS transistor is connected to the drain of the first PMOS transistor and connected to the gate of the second NMOS transistor. The drain of the second NMOS transistor is connected to the drain of the second PMOS transistor and the gate of the third PMOS transistor. The gate of the second PMOS transistor is connected to the drain of the third NMOS transistor and the third PMOS transistor, and connected to the gates of the fourth NMOS transistor and the fourth PMOS transistor. The drain of the fourth NMOS transistor is connected to the drain of the fourth PMOS transistor, and serves as the output terminal of the second level conversion circuit, connected to the gate of the reset switch in the switched capacitor amplifier. The sources of the first, second, third, and fourth NMOS transistors are all grounded.

6. The pixel unit circuit for a dynamic vision sensor as described in claim 1, characterized in that, The pixel unit circuit further includes a voltage follower circuit, which includes a first MOS transistor. The gate of the first MOS transistor is connected to the output terminal of the IV conversion circuit. The drain and source of the first MOS transistor are connected to the power supply VCC and ground, respectively. The source of the first MOS transistor serves as the output terminal of the voltage follower circuit. The first capacitor is connected between the output terminal of the voltage follower circuit and the inverting input terminal of the operational amplifier. The comparison circuit includes a first comparator and a second comparator. One input terminal of each of the first and second comparators is connected to the output terminal of the switched capacitor amplifier. The other input terminals of the first and second comparators receive a high preset voltage threshold and a low preset voltage threshold, respectively. The output terminals of the first and second comparators serve as the output terminals of the comparison circuit, used to output a bright event signal and a dark event signal.

7. The pixel unit circuit for a dynamic vision sensor as described in claim 1, characterized in that, The pixel readout logic circuit includes an event holding module, an event storage module, a restart logic module, and a reset logic module, wherein... The event holding module is connected to the output of the comparison circuit and is used to receive and temporarily store event signals from the comparison circuit. The event storage module is connected to the output of the event holding module, and is used to store the event signal and output the event signal synchronously after storage; The restart logic module is connected to the output of the event storage module and is used to determine whether there is an event to be read in the event storage module. The reset logic module is connected to the output of the restart logic module and the event holding module, and is used to reset the event holding module when there is an event to be read. It is also connected to the gate of the reset switch transistor, and is used to reset the output of the switched capacitor amplifier after an event to be read is read.

8. The pixel unit circuit for a dynamic vision sensor as described in claim 7, characterized in that, The event holding module includes a latch circuit, which includes two first D latches. The data input terminals of the two first D latches are connected to the output terminal of the comparator circuit to receive the event signal. The clock input terminals of the two first D latches are connected to the output terminal of the reset logic module. The data output terminal of one first D latch and the inverted output terminal of the other first D latch serve as the output terminals of the event holding module and are connected to the event storage module.

9. The pixel unit circuit for a dynamic vision sensor as described in claim 7, characterized in that, The event storage module includes two second D latches and a bus readout circuit. The bus readout circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. The data input terminals of the two second D latches are connected to the output terminals of the event holding module. The clock input terminals of the two second D latches receive external sampling signals. The data output terminals of the two second D latches are connected to the gates of the first transistor and the second transistor. The source of the first transistor is connected to the source of the second transistor. The drains of the first transistor and the second transistor are respectively connected to the sources of the third transistor and the fourth transistor. The gates of the third transistor and the fourth transistor receive external column select signals. The drains of the third transistor and the fourth transistor serve as the output terminals of the bus readout circuit for synchronously outputting the event signals. The inverted output terminals of the two second D latches are connected to the restart logic module.

10. The pixel unit circuit for a dynamic vision sensor as described in claim 9, characterized in that, The restart logic module includes a first NAND gate and a third D latch. The two inputs of the first NAND gate are connected to the inverted outputs of two second D latches. The output of the first NAND gate is connected to the clock input of the third D latch. The data input of the third D latch receives an external restart signal. The inverted output of the third D latch serves as the output of the restart logic module and is connected to the reset logic module. The reset logic module includes an OR gate and a second NAND gate. The two inputs of the OR gate are connected to the output of the event holding module. The output of the OR gate is connected to one input of the second NAND gate. The other input of the second NAND gate is connected to the output of the restart logic module. The output of the second NAND gate serves as the output of the reset logic module, outputting a reset signal to the event holding module and the switched capacitor amplifier.

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