Display device

Abstract

There is provided a display device including: a substrate having a display area and a peripheral area outside the display area; a light emitting diode disposed in the display area; an electrode unit including an electrode group disposed on the light emitting diode; a touch driving pad disposed in the peripheral area; a touch signal distribution unit disposed in the peripheral area and electrically connected between the electrode unit and the touch driving pad; and an electrostatic blocking unit electrically connected to the touch signal distribution unit and including organic diodes, in which each of the organic diodes includes a first electrode, a second electrode disposed on the first electrode, and an organic layer between the first electrode and the second electrode.

Description

[0001] Cross Reference to Related Applications

[0002] This application is based on and claims priority under 35 U.S.C. 119 to Korean Patent Application No. 10-2023-0164855, filed on November 23, 2023, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety. TECHNICAL FIELD

[0003] One or more embodiments relate to a display device. BACKGROUND

[0004] Display devices are now incorporated into various new applications. In addition, display devices are becoming thinner and lighter, enabling them to be used in new ways.

[0005] A display device can include a touch sensing device as an input device. The touch sensing device can include a touch electrode disposed on a front surface of the display device, a touch integrated circuit for driving the touch electrode and sensing a touch, and a touch signal distribution unit for controlling a connection between the touch electrode and the touch integrated circuit. SUMMARY

[0006] One or more embodiments include a display device that can reduce a circuit defect caused by static electricity. However, the scope of the disclosure is not limited thereto.

[0007] Additional aspects will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon examination of the description, or can be learned by practice of the presented embodiments of the disclosure.

[0008] According to one or more embodiments, a display device includes a substrate including a display area and a peripheral area outside the display area, light emitting diodes arranged in the display area, an electrode unit including a group of electrodes arranged on the light emitting diodes, a touch driving pad arranged in the peripheral area, a touch signal distribution unit arranged in the peripheral area and electrically connected between the electrode unit and the touch driving pad, and an electrostatic blocking unit electrically connected to the touch signal distribution unit and including organic diodes, wherein each of the organic diodes includes a first electrode, a second electrode arranged on the first electrode, and an organic layer between the first electrode and the second electrode.

[0009] Each of the light emitting diodes can include a pixel electrode, an opposite electrode arranged on the pixel electrode, and an intermediate layer between the pixel electrode and the opposite electrode, and the first electrode and the pixel electrode can include the same material, and the second electrode and the opposite electrode can include the same material.

[0010] The organic layer and the intermediate layer can include the same material.

[0011] The intermediate layer can include a light emitting layer, a first functional layer between the pixel electrode and the light emitting layer, and a second functional layer between the opposite electrode and the light emitting layer, and the organic layer can include the same material as at least one of the first functional layer and the second functional layer.

[0012] The organic diode can include a first organic diode and a second organic diode, and a second electrode of the first organic diode can be electrically connected to a first voltage line, and a second electrode of the second organic diode can be electrically connected to a second voltage line, and a first voltage applied to the first voltage line can be greater than a second voltage applied to the second voltage line.

[0013] The electrostatic blocking unit can further include a rectifier transistor, and the second electrode of each of the organic diodes can be electrically connected to the first voltage line, and each of the rectifier transistors can include a semiconductor layer and a gate electrode on the semiconductor layer, wherein the semiconductor layer includes a source region, a drain region, and a channel region between the source region and the drain region, and the gate electrode can be electrically connected to the drain region, and the source region can be electrically connected to the second voltage line.

[0014] The first voltage applied to the first voltage line can be greater than the second voltage applied to the second voltage line.

[0015] The first voltage can include a gate high voltage, and the second voltage can include a gate low voltage.

[0016] The touch signal distribution unit can include a first demultiplexer and a second demultiplexer, the second demultiplexer configured to electrically connect the first demultiplexer to the touch driving pad, and the first demultiplexer can include sub-demultiplexers, and each of the sub-demultiplexers can be electrically connected to one of the electrode groups.

[0017] The second demultiplexer can be further configured to sequentially connect the sub-demultiplexers to the touch driving pad in response to a first control signal.

[0018] The sub-demultiplexers connected to the touch driving pad can be configured to sequentially connect the touch electrodes of the corresponding electrode groups to the second demultiplexer in response to a second control signal.

[0019] The electrostatic blocking unit can include a first blocking unit and a second blocking unit arranged at two opposite sides of the first demultiplexer.

[0020] The electrostatic blocking unit can include a third blocking unit and a fourth blocking unit arranged at two opposite sides of the second demultiplexer.

[0021] Each of the sub-demultiplexers can include a first switching transistor, a first connection wire configured to electrically connect a first source-drain electrode of each of the first switching transistors to a corresponding touch electrode, and a second connection wire configured to connect a second source-drain electrode of each of the first switching transistors to a second demultiplexer.

[0022] The number of the first switching transistors can be the same as the number of the touch electrodes of each of the electrode groups.

[0023] The second demultiplexer can include a second switching transistor, a third connection wire configured to electrically connect a first source-drain electrode of each of the second switching transistors to a corresponding sub-demultiplexer, and a fourth connection wire configured to electrically connect a second source-drain electrode of each of the second switching transistors to a touch driving pad.

[0024] The number of the second switching transistors can be the same as the number of the sub-demultiplexers.

[0025] The first electrode of each of the organic diodes can be electrically connected to one of the first connection wire, the second connection wire, the third connection wire, and the fourth connection wire, and the second electrode of each of the organic diodes can be electrically connected to the first voltage line or the second voltage line.

[0026] In a plan view, the first electrode of each of the organic diodes can overlap one of the first connection wire, the second connection wire, the third connection wire, and the fourth connection wire.

[0027] The first connection wire, the second connection wire, the third connection wire, and the fourth connection wire can extend in a first direction, and the second electrodes of the organic diodes can be arranged along an imaginary straight line extending in a second direction crossing the first direction, and can be provided in its entirety.

[0028] Further aspects, features, and advantages of the present application, apart from those described above, will become apparent from a detailed description of the application taken in conjunction with the accompanying drawings, the claims of the claims, and the details of the application. BRIEF DESCRIPTION OF DRAWINGS

[0029] The above and other aspects, features, and advantages of certain embodiments of the present disclosure will be more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0030] Figure 1 is a plan view schematically showing a display device according to an embodiment;

[0031] Figure 2 is a plan view schematically showing a display device according to an embodiment;

[0032] Figure 3is an equivalent circuit diagram of one pixel of a display device according to an embodiment;

[0033] Figure 4 is a cross-sectional view schematically illustrating a display device according to an embodiment;

[0034] Figure 5 is a diagram schematically illustrating a touch sensing device of a display device according to an embodiment;

[0035] Figure 6 is a diagram schematically illustrating a circuit of one touch sensing device according to an embodiment;

[0036] Figure 7 is a timing chart showing a driving method of the touch sensing device shown in Figure 6

[0037] Figure 8 is a diagram schematically illustrating a circuit of one touch sensing device according to an embodiment;

[0038] Figure 9 and Figure 10 are circuit diagrams each schematically illustrating an electrostatic blocking unit according to an embodiment;

[0039] Figure 11 is a plan view schematically illustrating a part of a display device according to an embodiment; and

[0040] Figure 12 is a cross-sectional view taken along line I-I' of Figure 11 and schematically illustrates the display device. DETAILED DESCRIPTION

[0041] Reference will now be made in detail embodiments, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. In this regard, embodiments can have different forms and should not be construed as limited to the descriptions set forth herein. Accordingly, the embodiments are merely described below, by referring to the drawings, to explain aspects of the present description. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Throughout this disclosure, the expression "at least one of a, b, and c" indicates only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0042] ​Since various modifications and various embodiments are possible, specific embodiments are shown in the drawings and are described in detail in the detailed description. The effects and features of the present disclosure and methods of achieving them will be apparent by referring to the embodiments described below in detail in connection with the accompanying drawings. However, the present disclosure is not limited to the embodiments disclosed herein but can be implemented in various forms.

[0043] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings, and the same or corresponding components are denoted by the same reference numerals, and the same reference numerals are assigned, and redundant explanation will be omitted.

[0044] In this specification, the terms first and second are used to distinguish one element from another element for the purpose of distinguishing one element from other elements, not in a limiting sense.

[0045] In this specification, unless the context clearly indicates otherwise, the singular expression includes the plural expression.

[0046] In this specification, the terms such as include or have mean that a feature described in the specification or an element exists, and do not preclude the possibility of adding one or more other features or elements.

[0047] In this specification, when a part such as a layer, a region, an element, or the like is on another part, it not only means that the part is on the other element, but also means that the other element is interposed therebetween.

[0048] In this specification, "A, B, and / or C" can mean A, B, or C, or A and B, A and C, or B and C, or A, B, and C. "At least one of A, B, and C" can mean A, B, or C, or A and B, A and C, or B and C, or A, B, and C.

[0049] In this specification, the x-axis, the y-axis, and the z-axis are not limited to three axes on a Cartesian coordinate system, and can be interpreted in a broad sense including them. For example, the x-axis, the y-axis, and the z-axis can be perpendicular to each other, but can refer to different directions that are not orthogonal to each other.

[0050] In this specification, in cases where some embodiments can be implemented in this specification, a specific process sequence can be performed differently from the described order. For example, two processes described in succession can be performed substantially simultaneously, or in the reverse order to the order to be described.

[0051] In this specification, in cases where a wiring "extends in a first direction or a second direction", it not only means extending in a straight line shape in the first direction or the second direction, but also means extending in a zigzag shape or a curved shape in the first direction or the second direction.

[0052] In the present specification, when referred to as a "plan view", this means when a target portion is viewed from above, and when referred to as a "cross-sectional view", this means when a cross section of a target portion that is cut vertically is viewed from the side. In the following embodiments, a first component that "overlaps" a second component means that the first component is positioned at the top or bottom of the second component.

[0053] In the present specification, when X and Y are "connected" to each other, this can include a case where X and Y are electrically connected to each other, a case where X and Y are functionally connected to each other, and a case where X and Y are directly connected to each other. Here, X and Y can be objects (for example, a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, a layer, or the like). Thus, the present disclosure is not limited to a predetermined connection relationship, such as that represented in the drawings or the detailed description, and can also include a connection relationship other than that represented in the drawings or the detailed description.

[0054] When X and Y are electrically connected, one or more elements (for example, a switch, a transistor, a capacitive element, an inductor, a resistive element, a diode, or the like) that enable electrical connection of X and Y can be connected between X and Y, for example.

[0055] In the present specification, "ON" used in association with a device state can refer to an activated state of an element, and "OFF" can refer to a deactivated state of an element. "ON" used in association with a signal received by an element can refer to a signal that activates the element, and "OFF" can refer to a signal that deactivates the element. An element can be activated by a high-level voltage or a low-level voltage. For example, a P-channel transistor is activated by a low-level voltage, and an N-channel transistor is activated by a high-level voltage. Thus, it should be understood that the "ON" voltage of a P-channel transistor (P-type transistor) and an N-channel transistor (N-type transistor) has opposite (low and high) voltage levels.

[0056] In the drawings, the size of an element can be exaggerated or reduced, for convenience in explanation. For example, since the size and thickness of each component shown in the drawings are arbitrarily represented for the purpose of explanation, the present disclosure is not necessarily limited to the illustration.

[0057] Figure 1 FIG. 1 is a plan view schematically showing a display device according to an embodiment, and Figure 2 FIG. 1 is a plan view schematically showing a display device according to an embodiment, and

[0058] Reference Figure 1 and Figure 2 The display device 1 can include a display panel 10 and a circuit board 20.

[0059] The display panel 10 can include a display area DA in which an image is displayed and a peripheral area PA outside the display area DA. The display device 1 can provide a certain image according to light emitted from a plurality of pixels PX arranged in the display area DA. The peripheral area PA can be an area outside the display area DA and can be a kind of non-display area in which the plurality of pixels PX is not arranged. The display area DA can be completely surrounded by the peripheral area PA.

[0060] In an embodiment, as shown in Figure 1 and Figure 2 The display area DA can have a long rectangular shape in a first direction (e.g., a y-axis direction). In another embodiment, the display area DA can have a long rectangular shape in a second direction (e.g., an x-axis direction). The display area DA can have a circular shape, an elliptical shape, a polygonal shape, or an irregular shape.

[0061] Each of the plurality of pixels PX can include a display element such as an organic light emitting diode and a pixel circuit for controlling the display element. The pixel circuit can include a transistor, a storage capacitor, and the like. The pixel circuit can be electrically connected to a data line DL extending in a first direction (e.g., a y-axis direction) and a scan line SL extending in a second direction (e.g., an x-axis direction). The pixel circuit can be configured to control the display element in response to a data signal transmitted through the data line DL and a scan signal transmitted through the scan line SL. Each of the plurality of pixels PX can emit red light, green light, or blue light.

[0062] The display panel 10 can include a sensing area SA in which a touch input of a user is sensed. The touch electrode 410 can be arranged in the sensing area SA. In an embodiment, the display area DA and the sensing area SA can have substantially the same shape.

[0063] The peripheral area PA can include a first peripheral area PA1, a second peripheral area PA2, and a bending area BA. The first peripheral area PA1 can be an area surrounding the display area DA and various wirings for transmitting electrical signals to the display area DA and a driving circuit can be arranged in the first peripheral area PA1. The second peripheral area PA2 can be at a side of the first peripheral area PA1 and a data driving unit 30 to which a circuit board 20 is attached, a touch signal distribution unit 50, a pad PD, a touch driving pad TPa and TPDb, and a wiring can be arranged in the second peripheral area PA2.

[0064] In an embodiment, the peripheral area PA can further include a bending area BA between the first peripheral area PA1 and the second peripheral area PA2. The bending area BA can be an area in which the display panel 10 is bent, and the second peripheral area PA2 can be on the rear surface of the display panel 10 when the display panel 10 is bent. Accordingly, the area of the non-display area seen by the user can be reduced.

[0065] The circuit board 20 can be a flexible printed circuit board. The controller 40 can be located on the circuit board 20. The controller 40 can include a plurality of integrated circuits, and some of the integrated circuits can be configured to generate electrical signals to be transmitted to the plurality of pixels PX or the driving circuit, and other parts of the integrated circuits can be configured to generate electrical signals to be transmitted to the touch sensing device. The controller 40 can be mounted on the circuit board 20 by using a chip on plastic (COP) method or a chip on glass (COG) method.

[0066] The controller 40 can be electrically connected to the data driving unit 30 through the pad PD. The data driving unit 30 can be configured to convert an image signal into a data signal having a voltage or current shape in response to a control signal of the controller 40, and can be configured to transmit the data signal to the pixels PX through the data line DL.

[0067] The controller 40 can be electrically connected to the touch signal distribution unit 50 through the touch driving pads TPDa and TPDb. The touch signal distribution unit 50 can selectively connect the touch electrode 410 to the touch driving pads TPDa and TPDb in response to a control signal of the controller 40. The controller 40 can be configured to transmit a driving signal to the touch electrode 410 that is selectively connected to the touch driving pads TPDa and TPDb through the touch signal distribution unit 50 through a wire.

[0068] In an embodiment, the touch signal distribution unit 50 can include a first touch signal distribution unit 50a and a second touch signal distribution unit 50b. The first touch signal distribution unit 50a can be located on the left side (for example, with respect to the -x direction) of the data driving unit 30, and the second touch signal distribution unit 50b can be located on the right side (for example, with respect to the +x direction) of the data driving unit 30. In another embodiment, the touch signal distribution unit 50 can be arranged at only one side of the data driving unit 30.

[0069] Figure 3 is an equivalent circuit diagram of one pixel of a display device according to an embodiment.

[0070] Reference Figure 3The pixel PX can include a pixel circuit PC connected to the scan line SL and the data line DL, and a display element connected to the pixel circuit PC. The display element can be an organic light emitting diode OLED including a pixel electrode (anode) and a counter electrode (cathode). The counter electrode of the organic light emitting diode OLED can be a common electrode to which a second power supply voltage ELVSS is applied.

[0071] The pixel circuit PC can include a first transistor T1, a second transistor T2, and a storage capacitor Cst. The first terminal of each of the first transistor T1 and the second transistor T2 can be a source or a drain, and the second terminal of each of the first transistor T1 and the second transistor T2 can be a terminal different from the first terminal, according to the type (p-type or n-type) and / or the operating condition of the transistor. For example, when the first terminal is the source, the second terminal can be the drain.

[0072] The first transistor T1 can be a drive transistor in which the amplitude of a drive current is determined in response to a gate-source voltage, and the second transistor T2 can be a switching transistor that turns on / off in response to a gate-source voltage (substantially a gate voltage). The first transistor T1 and the second transistor T2 can be thin film transistors.

[0073] The first transistor T1 can be referred to as a drive transistor, and the second transistor T2 can be referred to as a scan transistor.

[0074] The storage capacitor Cst can be connected between the power supply line PL and the gate of the first transistor T1. The storage capacitor Cst can have a second electrode connected to the power supply line PL and a first electrode connected to the gate of the first transistor T1. The storage capacitor Cst can store a voltage corresponding to a difference between the voltage transferred from the second transistor T2 and the first power supply voltage ELVDD supplied to the power supply line PL.

[0075] The first transistor T1 can have a gate connected to the first electrode of the storage capacitor Cst, a first terminal connected to the power supply line PL, and a second terminal connected to the organic light emitting diode OLED. The first transistor T1 can control the amplitude of the drive current Id flowing from the power supply line PL to the organic light emitting diode OLED in response to a gate-source voltage. The organic light emitting diode OLED can emit light having a certain brightness by using the drive current Id.

[0076] The second transistor T2 can have a gate connected to the scan line SL, a drain connected to the data line DL, and a source connected to the gate of the first transistor T1. The second transistor T2 can transfer the data signal Dm to the gate of the first transistor T1 in response to the scan signal Sn.

[0077] Although Figure 3The pixel circuit PC is shown to include two thin film transistors and one storage capacitor for the pixel PX, but this is only one of possible implementations, and other configurations are possible. For example, the pixel circuit PC can include three or more transistors and / or two or more capacitors. In an implementation, the pixel circuit PC can include three transistors and one storage capacitor. In yet another implementation, the pixel circuit PC can include seven transistors and one storage capacitor.

[0078] Figure 4 is a cross-sectional view schematically illustrating a display device according to an embodiment.

[0079] Reference Figure 4 The display panel 10 can include a substrate 100, a display element layer, and an encapsulation layer 300. An organic light emitting diode OLED and a pixel circuit PC electrically connected to the organic light emitting diode OLED can be disposed on the display element layer.

[0080] The substrate 100 can include an insulating material such as glass, quartz, a polymer resin, or the like. The substrate 100 can be a rigid substrate or a flexible substrate that can be bent, folded, or rolled. For example, the substrate 100 can include a polymer resin such as polyether sulfone, polyacrylate, polyether imide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate. The substrate 100 can have a multi-layer structure including a layer including the above-described polymer resin and an inorganic layer (not shown). For example, the substrate 100 can have a multi-layer structure in which a layer including a polymer resin and an inorganic barrier layer are alternately stacked.

[0081] Because the display panel 10 includes the display area DA and the peripheral area (see Figure 1 The substrate 100 can include an area corresponding to the display area DA and an area corresponding to the peripheral area PA. Here, the substrate 100 including the display area DA and the peripheral area PA indicates that the substrate 100 includes an area corresponding to the display area DA and an area corresponding to the peripheral area PA.

[0082] The buffer layer 201 can be located on the substrate 100 and can reduce or prevent impurities, moisture, or external air from permeating from a lower portion of the substrate 100. In addition, the buffer layer 201 can provide a flat surface for the semiconductor layer Act. The buffer layer 201 can include an inorganic material such as an oxide or a nitride, an organic material, or an organic / inorganic composite material, and can have a single-layer structure or a multi-layer structure of inorganic materials and organic materials.

[0083] A barrier layer for preventing external air permeation can also be disposed between the substrate 100 and the buffer layer 201. The barrier layer and the buffer layer 201 can include silicon oxide (SiO2) or silicon nitride (SiN x ).

[0084] A pixel circuit PC including a thin film transistor TFT and a storage capacitor Cst can be disposed on the buffer layer 201. The thin film transistor TFT can correspond to the first transistor T1 described with reference to FIG. 1. Figure 3

[0085] The thin film transistor TFT can include a semiconductor layer Act, a gate electrode GE, a drain electrode DE, and a source electrode SE.

[0086] The semiconductor layer Act can be disposed on the buffer layer 201 and can include polysilicon. In another embodiment, the semiconductor layer Act can include amorphous silicon. In still another embodiment, the semiconductor layer Act can include an oxide of at least one material selected from the group consisting of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), and zinc (Zn). The semiconductor layer Act can include a channel region, and source and drain regions doped with impurities. The source and drain regions can be on both sides of the channel region, respectively.

[0087] A first gate insulating layer 203 can be provided to cover the semiconductor layer Act. The first gate insulating layer 203 can include an inorganic insulating material such as silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO x , which can be ZnO or ZnO2). The first gate insulating layer 203 can have a single-layer structure or a multi-layer structure including the above-described inorganic insulating material.

[0088] A gate electrode GE can be disposed on the first gate insulating layer 203 to overlap the semiconductor layer Act. The gate electrode GE can have a single-layer structure or a multi-layer structure including molybdenum (Mo), Al, Cu, Ti, or the like. For example, the gate electrode GE can have a single-layer Mo structure.

[0089] A second gate insulating layer 204 can be provided to cover the gate electrode GE. The second gate insulating layer 204 can include an inorganic insulating material such as silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO​x N y ), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO x ). The second gate insulating layer 204 can have a single-layer structure or a multi-layer structure including the above-described inorganic insulating material.

[0090] The second electrode CE2 of the storage capacitor Cst can be disposed above the second gate insulating layer 204. The second electrode CE2 can overlap the gate electrode GE. The gate electrode GE and the second electrode CE2 can overlap each other with the second gate insulating layer 204 therebetween, and can constitute the storage capacitor Cst. That is, the gate electrode GE can serve as the first electrode CE1 of the storage capacitor Cst.

[0091] The second electrode CE2 can include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and can have a single-layer structure or a multi-layer structure including the above-described material.

[0092] An interlayer insulating layer 205 can be provided to cover the second electrode CE2. The interlayer insulating layer 205 can include an inorganic insulating material such as silicon oxide (SiO2), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO x ). The interlayer insulating layer 205 can have a single-layer structure or a multi-layer structure including the above-described inorganic insulating material.

[0093] The source electrode SE and the drain electrode DE can be disposed on the interlayer insulating layer 205. The source electrode SE and the drain electrode DE can include a conductive material including Mo, Al, Cu, Ti, or the like, and can have a multi-layer structure or a single-layer structure including the above-described material. For example, the source electrode SE and / or the drain electrode DE can have a three-layer structure of Ti / Al / Ti. In some embodiments, the source electrode SE or the drain electrode DE can also be omitted. For example, adjacent thin film transistors TFT can share a source region and a drain region of the semiconductor layer Act, and the source region or the drain region can serve as the source electrode SE or the drain electrode DE.

[0094] The first planarization insulating layer 207 can be disposed to cover the source electrode SE and the drain electrode DE, and the second planarization insulating layer 208 can be disposed on the first planarization insulating layer 207. The first planarization insulating layer 207 and the second planarization insulating layer 208 can provide a flat base surface to the pixel electrode 210 disposed above the first planarization insulating layer 207 and the second planarization insulating layer 208.

[0095] The first planarization insulating layer 207 and the second planarization insulating layer 208 can include an organic material, and can have a single layer structure or a multi-layer structure. The organic material can include a generally commonly used polymer such as benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethyl methacrylate (PMMA), or polystyrene (PS), a polymer derivative having a phenol-based group, an acryl-based polymer, an imide-based polymer, an aryl ether-based polymer, an amide-based polymer, a fluorine-based polymer, a p-xylene-based polymer, or a vinyl alcohol-based polymer, etc. The first planarization insulating layer 207 and the second planarization insulating layer 208 can include an inorganic insulating material such as silicon oxide (SiO2), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO x ). When the first planarization insulating layer 207 and the second planarization insulating layer 208 are formed, in order to provide a flat upper surface after the formation of these layers, chemical mechanical polishing can be performed on the upper surfaces of these layers.

[0096] The connection electrode CM can be disposed between the first planarization insulating layer 207 and the second planarization insulating layer 208. The connection electrode CM can include a conductive material including Mo, Al, Cu, Ti, etc., and can have a multi-layer structure or a single layer structure including the above-described material. The connection electrode CM can be electrically connected to the drain electrode DE of the thin film transistor TFT through a contact hole passing through the first planarization insulating layer 207.

[0097] The pixel electrode 210 can be disposed above the second planarization insulating layer 208. The pixel electrode 210 can be electrically connected to the thin film transistor TFT by contacting the connection electrode CM through a contact hole passing through the second planarization insulating layer 208.

[0098] The pixel electrode 210 can include a transparent conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO). The pixel electrode 210 can include a reflective layer including Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, or a compound thereof. For example, the pixel electrode 210 can have a structure having a layer formed of ITO, IZO, ZnO, or In2O3 above / below the above-described reflective layer. In this case, the pixel electrode 210 can have a stack structure of ITO / Ag / ITO.

[0099] The pixel defining layer 209 can cover edges of the pixel electrode 210 on the second planarization insulating layer 208 and can include a pixel opening OP1 for exposing a center of the pixel electrode 210. An emission area EA of the organic light emitting diode OLED, that is, a size and a shape of a pixel, is defined by the pixel opening OP1.

[0100] The pixel defining layer 209 can be configured to increase a distance between the edges of the pixel electrode 210 and the counter electrode 230 on the pixel electrode 210 to prevent an arc or the like from occurring in the edges of the pixel electrode 210. The pixel defining layer 209 can be formed of an organic insulating material such as polyimide, polyamide, acrylic resin, BCB, HMDSO, phenol resin, or the like by a method such as spin coating.

[0101] The pixel defining layer 209 can be black. The pixel defining layer 209 can include a light blocking material and can be black. The light blocking material can include carbon black, carbon nanotubes, a paste or a resin including a black dye, metal particles such as Ni, Al, Mo, and alloys thereof, metal oxide particles (e.g., chromium oxide), or metal nitride particles (e.g., chromium nitride). When the pixel defining layer 209 includes the light blocking material, external light reflection caused by a metal structure located below the pixel defining layer 209 can be reduced.

[0102] The intermediate layer 220 can be disposed between the pixel electrode 210 and the counter electrode 230. The intermediate layer 220 can include a first functional layer 221, an emission layer 222, and a second functional layer 223.

[0103] The emission layer 222 formed to correspond to the pixel electrode 210 can be disposed within the pixel opening OP1 of the pixel defining layer 209. The emission layer 222 can include a polymer material or a low molecular weight material and can emit red light, green light, blue light, or white light.

[0104] The first functional layer 221 can be disposed between the pixel electrode 210 and the light emitting layer 222, and the second functional layer 223 can be disposed between the light emitting layer 222 and the counter electrode 230. In an embodiment, unlike the light emitting layer 222 which is patterned and disposed in each pixel, the first functional layer 221 and the second functional layer 223 can be provided integrally throughout the display area DA.

[0105] The first functional layer 221 can be a single layer or multiple layers. For example, when the first functional layer 221 includes a polymer material, the first functional layer 221 can be a hole transport layer (HTL) having a single layer structure, and can include poly-(3,4)-ethylenedioxythiophene (PEDOT) or polyaniline (PANI). When the first functional layer 221 includes a low molecular weight material, the first functional layer 221 can include a hole injection layer (HIL) and an HTL.

[0106] The second functional layer 223 can be selectively disposed. For example, when the first functional layer 221 and the light emitting layer 222 include a polymer material, the second functional layer 223 can be formed. The second functional layer 223 can be a single layer or multiple layers. The second functional layer 223 can include an electron transport layer (ETL) and / or an electron injection layer (EIL). In some embodiments, at least one of the HIL, the HTL, the ETL, and the EIL can also be omitted.

[0107] The counter electrode 230 can include a conductive material having a relatively low work function. For example, the counter electrode 230 can include a (semi-)transparent layer including silver (Ag), magnesium (Mg), aluminum (Al), nickel (Ni), chromium (Cr), lithium (Li), calcium (Ca), or an alloy thereof. Alternatively, the counter electrode 230 can also include a layer such as ITO, IZO, ZnO, or In2O3 on the (semi-)transparent layer including the above-described materials. In an embodiment, the counter electrode 230 can include Ag and Mg.

[0108] The stack structure of the pixel electrode 210, the intermediate layer 220, and the counter electrode 230, which are sequentially stacked, can constitute an organic light emitting diode OLED.

[0109] In an embodiment, a capping layer (not shown) can be disposed on the organic light emitting diode OLED. The capping layer can be configured to improve the light emitting efficiency of the organic light emitting diode OLED by the principle of enhancing interference. The capping layer can be an organic capping layer including an organic material, an inorganic capping layer including an inorganic material, or a composite capping layer including an organic material and an inorganic material.

[0110] The encapsulation layer 300 can be disposed on the organic light emitting diode OLED. In an embodiment, the encapsulation layer 300 can include at least one inorganic encapsulation layer and at least one organic encapsulation layer. In an embodiment, the encapsulation layer 300 can include a first inorganic encapsulation layer 310 and a second inorganic encapsulation layer 330 and an organic encapsulation layer 320 therebetween.

[0111] Each of the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 can include one or more inorganic insulating materials. The inorganic insulating material can include aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), zinc oxide (ZnO x ), silicon oxide (SiO X ), silicon nitride (SiN X ), or / and silicon oxynitride (SiO x N y ). The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 can be formed by chemical vapor deposition.

[0112] The organic encapsulation layer 320 can further include polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyvinyl sulfonate, polyformaldehyde, polyarylate, hexamethyldisiloxane (HMDSO), an acrylic-based resin, or a combination thereof.

[0113] The encapsulation layer 300 can completely cover the display area DA, can extend to the peripheral area (see Figure 1 PA), and can be disposed to cover at least a portion of the peripheral area PA.

[0114] In an embodiment, the electrode unit of the touch sensing device can be disposed on the encapsulation layer 300. As described above, the encapsulation layer 300 can include the organic encapsulation layer 320 and can provide a further planarized base surface. Accordingly, even when the electrode unit of the touch sensing device and the wiring are formed through a continuous process, the defect rate can be reduced.

[0115] Figure 5 FIG. 1 is a diagram schematically illustrating a display device according to an embodiment.

[0116] Referring to Figure 5 , the touch sensing device TSD according to an embodiment can include an electrode unit 400 disposed in a sensing area (see Figure 2 SA), a touch signal distribution unit 50, a touch driving pad TPD, and a connection wiring for connecting components.

[0117] One electrode unit 400 can include touch electrodes 410 electrically connected to one touch driving pad TPD. The electrode unit 400 can include a plurality of electrode groups. As Figure 5 As shown in the middle, the electrode unit 400 can include a first electrode group 401, a second electrode group 402, a third electrode group 403, and a fourth electrode group 404.

[0118] Each of the electrode groups 401, 402, 403, and 404 can include a plurality of touch electrodes 410. In an embodiment, the touch electrodes 410 belonging to the same electrode group can be arranged to be spaced apart from each other in a first direction (e.g., a y-axis direction).

[0119] The first electrode group 401 and the third electrode group 403 can be arranged adjacent to each other in the first direction (e.g., a y-axis direction), and the second electrode group 402 and the fourth electrode group 404 can be arranged adjacent to each other in the first direction (e.g., a y-axis direction). The first electrode group 401 and the second electrode group 402 can be arranged adjacent to each other in a second direction (e.g., an x-axis direction), and the third electrode group 403 and the fourth electrode group 404 can be arranged adjacent to each other in the second direction (e.g., an x-axis direction). For example, the touch electrodes 410 can form a matrix in the first direction (e.g., a y-axis direction) and the second direction (e.g., an x-axis direction), and the first electrode group 401 and the third electrode group 403 can be arranged in odd-numbered columns, and the second electrode group 402 and the fourth electrode group 404 can be arranged in even-numbered columns.

[0120] The touch signal distribution unit 50 can be electrically connected between the electrode unit 400 and the touch driving pad TPD. The touch signal distribution unit 50 can be configured to sequentially connect the touch electrodes 410 belonging to one electrode unit 400 to the touch driving pad TPD in response to a control signal. The touch signal distribution unit 50 can include a first demultiplexer 510 and a second demultiplexer 520.

[0121] The first demultiplexer 510 can be electrically connected to the touch electrodes 410 of the electrode unit 400 through connection wires. Each of the first demultiplexer 510 can include a plurality of sub-demultiplexers 511, 512, 513, and 514. Each of the plurality of sub-demultiplexers 511, 512, 513, and 514 can be electrically connected to one of the electrode groups 401, 402, 403, and 404. Accordingly, the number of the sub-demultiplexers 511, 512, 513, and 514 can be the same as the number of the electrode groups 401, 402, 403, and 404 included in one electrode unit 400.

[0122] In an embodiment, the first sub-demultiplexer 511 can be electrically connected to the touch electrodes 410 of the first electrode group 401 through connection wirings, the second sub-demultiplexer 512 can be electrically connected to the touch electrodes 410 of the second electrode group 402 through connection wirings, the third sub-demultiplexer 513 can be electrically connected to the touch electrodes 410 of the third electrode group 403 through connection wirings, and the fourth sub-demultiplexer 514 can be electrically connected to the touch electrodes 410 of the fourth electrode group 404 through connection wirings.

[0123] Each of the sub-demultiplexers 511, 512, 513, and 514 can be configured to sequentially connect each of the touch electrodes 410 of the electrode group to the second demultiplexer 520 in response to a first control signal Cs1.

[0124] The second demultiplexer 520 can be disposed between the first demultiplexer 510 and the touch driving pad TPD, and can electrically connect the first demultiplexer 510 to the touch driving pad TPD. The second demultiplexer 520 can be configured to sequentially electrically connect each of the sub-demultiplexers 511, 512, 513, and 514 to the touch driving pad TPD in response to a second control signal Cs2.

[0125] In an embodiment, the second demultiplexer 520 can be configured to electrically connect the first sub-demultiplexer 511 to the touch driving pad TPD for a first period, electrically connect the second sub-demultiplexer 512 to the touch driving pad TPD for a second period, electrically connect the third sub-demultiplexer 513 to the touch driving pad TPD for a third period, and electrically connect the fourth sub-demultiplexer 514 to the touch driving pad TPD for a fourth period.

[0126] For the first period, the first sub-demultiplexer 511 can be configured to sequentially electrically connect each of the touch electrodes 410 of the first electrode group 401 to the touch driving pad TPD. For the second period, the second sub-demultiplexer 512 can be configured to sequentially electrically connect each of the touch electrodes 410 of the second electrode group 402 to the touch driving pad TPD. For the third period, the third sub-demultiplexer 513 can be configured to sequentially electrically connect each of the touch electrodes 410 of the third electrode group 403 to the touch driving pad TPD. For the fourth period, the fourth sub-demultiplexer 514 can be configured to sequentially electrically connect each of the touch electrodes 410 of the fourth electrode group 404 to the touch driving pad TPD.

[0127] Accordingly, a driving signal provided to the touch driving pad TPD by the controller (see Figure 2 40) can be time-divisionally delivered to each of the touch electrodes 410 by the touch signal distribution unit 50.

[0128] Figure 6FIG. 1 is a diagram schematically illustrating a circuit of a touch sensing device according to an embodiment.

[0129] Referring to Figure 6 The touch sensing device TSD can include an electrode unit 400, a touch signal distribution unit 50, a touch driving pad TPD, connection wirings TL1, TL2, TL3, and TL4, and control signal lines ESL and GSL.

[0130] The electrode unit 400 can include electrode groups 401, 402, 403, and 404. The electrode groups 401, 402, 403, and 404 can include a first electrode group 401, a second electrode group 402, a third electrode group 403, and a fourth electrode group 404. Each of the electrode groups 401, 402, 403, and 404 can include a plurality of touch electrodes 410.

[0131] The touch signal distribution unit 50 can be disposed between the electrode unit 400 and the touch driving pad TPD. The touch signal distribution unit 50 can include first de-multiplexers 510 and second de-multiplexers 520. Each of the first de-multiplexers 510 can include a plurality of sub-de-multiplexers 511, 512, 513, and 514. The plurality of sub-de-multiplexers 511, 512, 513, and 514 can include a first sub-de-multiplexer 511, a second sub-de-multiplexer 512, a third sub-de-multiplexer 513, and a fourth sub-de-multiplexer 514.

[0132] The first de-multiplexers 510 can include a plurality of first switching transistors T11, …, and T4n, a first connection wiring TL1, a second connection wiring TL2, and a first control signal line ESL. The number of the first switching transistors T11, …, and T4n of each of the sub-de-multiplexers 511, 512, 513, and 514 can be the same as the number of the touch electrodes 410 of the electrode group to which each of the sub-de-multiplexers 511, 512, 513, and 514 is connected.

[0133] In an embodiment, the first electrode group 401 can include n touch electrodes 410, and the first sub-de-multiplexer 511 can include n first switching transistors T11, T12, …, and T1n. A first terminal of each of the first switching transistors T11, T12, …, and T1n of the first sub-de-multiplexer 511 can be connected one-to-one to the touch electrodes 410 of the first electrode group 401 through the first connection wiring TL1. A second terminal of each of the first switching transistors T11, T12, …, and T1n can be electrically connected to the second connection wiring TL2. The second connection wiring TL2 of the first sub-de-multiplexer 511 can be joined in a first node N1 and can be electrically connected to the second de-multiplexer 520.

[0134] Similarly, the second sub-demultiplexer 512 can include n first switching transistors T21, T22, …, and T2n. The first terminal of each of the first switching transistors T21, T22, …, and T2n of the second sub-demultiplexer 512 can be connected one-to-one to the touch electrode 410 of the second electrode group 402 through the first connection wire TL1. The second terminal of each of the first switching transistors T21, T22, …, and T2n can be electrically connected to the second connection wire TL2. The second connection wire TL2 of the second sub-demultiplexer 512 can be joined in the second node N2 and can be electrically connected to the second demultiplexer 520.

[0135] The third sub-demultiplexer 513 can include n first switching transistors T31, T32, …, and T3n. The first terminal of each of the first switching transistors T31, T32, …, and T3n of the third sub-demultiplexer 513 can be connected one-to-one to the touch electrode 410 of the third electrode group 403 through the first connection wire TL1. The second terminal of each of the first switching transistors T31, T32, …, and T3n can be electrically connected to the second connection wire TL2. The second connection wire TL2 of the third sub-demultiplexer 513 can be joined in the third node N3 and can be electrically connected to the second demultiplexer 520.

[0136] The fourth sub-demultiplexer 514 can include n first switching transistors T41, T42, …, and T4n. The first terminal of each of the first switching transistors T41, T42, …, and T4n of the fourth sub-demultiplexer 514 can be connected one-to-one to one of the touch electrodes 410 of the fourth electrode group 404 through the first connection wire TL1. The second terminal of each of the first switching transistors T41, T42, …, and T4n can be electrically connected to the second connection wire TL2. The second connection wire TL2 of the fourth sub-demultiplexer 514 can be joined in the fourth node N4 and can be electrically connected to the second demultiplexer 520.

[0137] The gate of each of the first switching transistors T11, T12, …, and T4n can be electrically connected to one of the first control signal lines ESL. The first control signal lines ESL can be configured to deliver the first control signals Es1, Es2, …, and Esn applied through the first control pad CPD1 to the gates of the first switching transistors T11, …, and T4n. The first switching transistors T11, …, and T4n can be turned on or off in response to the first control signals Es1, Es2, …, and Esn.

[0138] Accordingly, each of the sub-demultiplexers 511, 512, 513, and 514 can be configured to sequentially connect the touch electrodes 410 of the corresponding electrode group to the second demultiplexer 520 in response to the first control signals Es1, Es2, …, and Esn.

[0139] The second demultiplexer 520 can include a plurality of second switching transistors M1, M2, M3, and M4, a third connection wire TL3, a fourth connection wire TL4, and a second control signal line GSL. The number of the second switching transistors M1, M2, M3, and M4 of the second demultiplexer 520 can be the same as the number of the sub-demultiplexers 511, 512, 513, and 514 of the first demultiplexer 510. In other words, the number of the second switching transistors M1, M2, M3, and M4 of the second demultiplexer 520 can be the same as the number of the electrode groups 401, 402, 403, and 404 of the electrode unit 400.

[0140] In an embodiment, the second demultiplexer 520 can include four second switching transistors M1, M2, M3, and M4. The first terminal of each of the second switching transistors M1, M2, M3, and M4 can be connected one-to-one to the nodes N1, N2, N3, and N4 through the third connection wire TL3. The second terminal of each of the second switching transistors M1, M2, M3, and M4 can be electrically connected to the fourth connection wire TL4. The fourth connection wire TL4 can be connected to each other and can be electrically connected to the touch driving pad TPD.

[0141] The gate of each of the second switching transistors M1, M2, M3, and M4 can be electrically connected to one of the second control signal lines GSL. The second control signal lines GSL can be configured to deliver the second control signals Gs1, Gs2, Gs3, and Gs4 applied through the second control pad CPD2 to the gates of the second switching transistors M1, M2, M3, and M4. The second switching transistors M1, M2, M3, and M4 can be turned on or off in response to the second control signals Gs1, Gs2, Gs3, and Gs4. Accordingly, the second demultiplexer 520 can be configured to sequentially connect the sub-demultiplexers 511, 512, 513, and 514 to the touch driving pad TPD in response to the second control signals Gs1, Gs2, Gs3, and Gs4.

[0142] The touch sensing device TSD can include an electrostatic blocking unit EC. The electrostatic blocking unit EC can include a protection circuit SC for protecting the transistors of the touch signal distribution unit 50 from being damaged by a high-voltage pulse.

[0143] In one embodiment, the electrostatic discharge (ESD) blocking unit EC may include a first blocking unit EC1 and a second blocking unit EC2 disposed on both sides of the first demultiplexer 510. Each of the first blocking unit EC1 and the second blocking unit EC2 may include multiple protection circuits SC. The first blocking unit EC1 may be electrically connected to a first connection wiring TL1 of the first demultiplexer 510, and the second blocking unit EC2 may be electrically connected to a second connection wiring TL2 of the first demultiplexer 510. In another embodiment, the second blocking unit EC2 may be disposed between nodes N1, N2, N3, and N4 and the second demultiplexer 520.

[0144] Figure 7 It is shown Figure 6 The timing diagram shows the driving method of the touch sensing device.

[0145] refer to Figure 6 and Figure 7 The first control signals Es1, Es2, ..., Esn can be transmitted from the controller via the first control signal line ESL (see...). Figure 2 40) is provided to the first demultiplexer 510. The first control signals Es1, Es2, ..., and Esn can be gate control signals controlling the on and off states of the first switching transistors T11, ..., and T4n. The first control signals Es1, Es2, ..., and Esn can provide an on-state voltage for each of the first switching transistors T11, ..., and T4n to be turned on and an off-state voltage for each of the first switching transistors T11, ..., and T4n to be turned off. The first control signals Es1, Es2, ..., and Esn can be signals with the same waveform and offset phase. The time periods (hereinafter referred to as "on-state voltage periods") maintaining the on-state voltage of each of the first control signals Es1, Es2, ..., and Esn can arrive sequentially and can not overlap with each other.

[0146] The second control signals Gs1, Gs2, Gs3, and Gs4 can be transmitted from the controller via the second control signal line GSL (see [link]). Figure 2The second control signals Gs1, Gs2, Gs3, and Gs4 can be gate control signals for controlling the turn-on and turn-off of the second switching transistors M1, M2, M3, and M4 of the second demultiplexer 520. The second control signals Gs1, Gs2, Gs3, and Gs4 can be provided as a turn-on voltage at which each of the second switching transistors M1, M2, M3, and M4 can be turned on and a turn-off voltage at which each of the second switching transistors M1, M2, M3, and M4 can be turned off. The second control signals Gs1, Gs2, Gs3, and Gs4 can have the same waveform and offset phases. For example, the (2-1)th control signal Gs1 can be provided as a turn-on voltage for the first period P1 and can be provided as a turn-off voltage for the second period P2, the third period P3, and the fourth period P4. The (2-2)th control signal Gs2 can be provided as a turn-on voltage for the second period P2 and can be provided as a turn-off voltage for the first period P1, the third period P3, and the fourth period P4. The (2-3)th control signal Gs3 can be provided as a turn-on voltage for the third period P3 and can be provided as a turn-off voltage for the first period P1, the second period P2, and the fourth period P4. The (2-4)th control signal Gs4 can be provided as a turn-on voltage for the fourth period P4 and can be provided as a turn-off voltage for the first period P1, the second period P2, and the third period P3.

[0147] For example, the first period P1 can be a turn-on voltage period of the (2-1)th control signal Gs1, the second period P2 can be a turn-on voltage period of the (2-2)th control signal Gs2, the third period P3 can be a turn-on voltage period of the (2-3)th control signal Gs3, and the fourth period P4 can be a turn-on voltage period of the (2-4)th control signal Gs4. The first period P1, the second period P2, the third period P3, and the fourth period P4 can be sequentially repeated.

[0148] For the first period P1, the second period P2, the third period P3, and the fourth period P4, a driving signal Ds can be provided to the touch driving pad TPD. The driving signal Ds can have a square wave signal in which a high-level voltage and a low-level voltage are repeated.

[0149] The (2-1)th switching transistor M1 of the second demultiplexer 520 can be turned on by the (2-1)th control signal Gs1 for the first period P1. The driving signal Ds can be transmitted to the first node N1 through the (2-1)th switching transistor M1.

[0150] The first switching transistors T11, T12, …, and T1n of the first sub-demultiplexer 511 can be sequentially turned on in the first period P1 in response to the first control signals Es1, Es2, …, and Esn. Accordingly, the touch electrodes 410 included in the first electrode group 401 can be activated by sequentially receiving the driving signal Ds.

[0151] The second (2-2) switching transistor M2 of the second demultiplexer 520 can be turned on by the second (2-2) control signal Gs2 in the second period P2. The driving signal Ds can be transmitted to the second node N2 through the second (2-2) switching transistor M2.

[0152] The first switching transistors T21, T22, …, and T2n of the second sub-demultiplexer 512 can be sequentially turned on in the second period P2 in response to the first control signals Es1, Es2, …, and Esn. Accordingly, the touch electrodes 410 included in the second electrode group 402 can be activated by sequentially receiving the driving signal Ds.

[0153] The second (2-3) switching transistor M3 of the second demultiplexer 520 can be turned on by the second (2-3) control signal Gs3 in the third period P3. The driving signal Ds can be transmitted to the third node N3 through the second (2-3) switching transistor M3.

[0154] The first switching transistors T31, T32, …, and T3n of the third sub-demultiplexer 513 can be sequentially turned on in the third period P3 in response to the first control signals Es1, Es2, …, and Esn. Accordingly, the touch electrodes 410 included in the third electrode group 403 can be activated by sequentially receiving the driving signal Ds.

[0155] The second (2-4) switching transistor M4 of the second demultiplexer 520 can be turned on by the second (2-4) control signal Gs4 in the fourth period P4. The driving signal Ds can be transmitted to the fourth node N4 through the second (2-4) switching transistor M4.

[0156] The first switching transistors T41, T42, …, and T4n of the fourth sub-demultiplexer 514 can be sequentially turned on in the fourth period P4 in response to the first control signals Es1, Es2, …, and Esn. Accordingly, the touch electrodes 410 included in the fourth electrode group 404 can be activated by sequentially receiving the driving signal Ds.

[0157] Figure 8 FIG. 1 is a diagram schematically illustrating a circuit of a touch sensing device according to an embodiment. Figure 8 With Figure 6 Similarly, but Figure 8 With Figure 6The difference is that the electrostatic blocking unit EC is arranged at both sides of the second demultiplexer 520.

[0158] Referring to Figure 8 The touch sensing device TSD can include the electrode unit 400, the touch signal distribution unit 50, the touch driving pad TPD, the connection wires TL1, TL2, TL3, and TL4, and the control signal lines ESL and GSL.

[0159] The electrode unit 400 can include electrode groups 401, 402, 403, and 404. The electrode groups 401, 402, 403, and 404 can include a first electrode group 401, a second electrode group 402, a third electrode group 403, and a fourth electrode group 404. Each of the electrode groups 401, 402, 403, and 404 can include a plurality of touch electrodes 410.

[0160] The touch signal distribution unit 50 can be arranged between the electrode unit 400 and the touch driving pad TPD. The touch signal distribution unit 50 can include a first demultiplexer 510 and a second demultiplexer 520. Each of the first demultiplexer 510 can include a plurality of sub-demultiplexers 511, 512, 513, and 514. The plurality of sub-demultiplexers 511, 512, 513, and 514 can include a first sub-demultiplexer 511, a second sub-demultiplexer 512, a third sub-demultiplexer 513, and a fourth sub-demultiplexer 514.

[0161] The first demultiplexer 510 can include a plurality of first switching transistors T11, …, and T4n, a first connection wire TL1, a second connection wire TL2, and a first control signal line ESL. The second demultiplexer 520 can include a plurality of second switching transistors M1, M2, M3, and M4, a third connection wire TL3, a fourth connection wire TL4, and a second control signal line GSL.

[0162] The touch sensing device TSD can include an electrostatic blocking unit EC. The electrostatic blocking unit EC can include a protection circuit SC for protecting the transistors of the touch signal distribution unit 50 from being damaged by a high-voltage pulse.

[0163] In an embodiment, the electrostatic blocking unit EC can include a third blocking unit EC3 and a fourth blocking unit EC4 arranged at both sides of the second demultiplexer 520. Each of the third blocking unit EC3 and the fourth blocking unit EC4 can include a plurality of protection circuits SC. The third blocking unit EC3 can be electrically connected to the third connection wire TL3 of the second demultiplexer 520, and the fourth blocking unit EC4 can be electrically connected to the fourth connection wire TL4 of the second demultiplexer 520.

[0164] In another embodiment, the electrostatic blocking unit EC can include a first blocking unit (see EC1 of Figure 6 ) and a second blocking unit (see EC2 of Figure 6 ) arranged at both sides (e.g., two opposite sides) of the first demultiplexer 510 and a third blocking unit EC3 and a fourth blocking unit EC4 arranged at both sides of the second demultiplexer 520.

[0165] In another embodiment, the electrostatic blocking unit EC can include a first blocking unit (see EC1 of Figure 6 ) arranged between the first demultiplexer 510 and the electrode unit 400 and a third blocking unit EC3 and a fourth blocking unit EC4 located at both sides (e.g., two opposite sides) of the second demultiplexer 520.

[0166] Figure 9 and Figure 10 are circuit diagrams schematically illustrating electrostatic blocking units according to embodiments.

[0167] Figure 9 and Figure 10 The electrostatic blocking unit EC shown in Figure 6 may be applied to the first demultiplexer 510 as shown in Figure 8 , or can be applied to the second demultiplexer 520 as shown in Figure 9 and Figure 10 The transistors TR shown in Figure 6 may correspond to first switching transistors T11, …, and T4n of the first demultiplexer (see 510 of Figure 8 ) or second switching transistors M1, M2, M3, and M4 of the second demultiplexer (see 520 of

[0168] The first terminal of each of the transistors TR can be electrically connected to the first wiring WL1, and the second terminal of the transistor TR can be electrically connected to the second wiring WL2, and the gate of the transistor TR can be electrically connected to the control signal line CSL.

[0169] When the transistor TR is one of the first switching transistors T11, …, and T4n, the first wiring WL1 can correspond to the first connection wiring TL1, the second wiring WL2 can correspond to the second connection wiring TL2, and the control signal line CSL can correspond to the first control signal line ESL. When the transistor TR is one of the second switching transistors M1, M2, M3, and M4, the first wiring WL1 can correspond to the third connection wiring TL3, the second wiring WL2 can correspond to the fourth connection wiring TL4, and the control signal line CSL can correspond to the second control signal line GSL.

[0170] ReferenceFigure 9 The electrostatic blocking unit EC can include a protection circuit SC electrically connected to both terminals of the transistor TR in the internal circuit.

[0171] One protection circuit SC can include a first organic diode OD1 and a second organic diode OD2. Each of the first organic diode OD1 and the second organic diode OD2 can include a first electrode, a second electrode on the first electrode, and an organic layer between the first electrode and the second electrode.

[0172] The first electrode of the first organic diode OD1 and the first electrode of the second organic diode OD2 belonging to one protection circuit SC can be electrically connected to the same wiring. For example, the first electrode of the first organic diode OD1 and the first electrode of the second organic diode OD2 belonging to the protection circuit SC on the first terminal of the transistor TR can be electrically connected to the first wiring WL1. The first electrode of the first organic diode OD1 and the first electrode of the second organic diode OD2 belonging to the protection circuit SC on the second terminal of the transistor TR can be electrically connected to the second wiring WL2.

[0173] The second electrode of the first organic diode OD1 can be electrically connected to a first voltage line VL1. The first voltage line VL1 can be configured to deliver a first voltage V H to the second electrode of the first organic diode OD1. The second electrode of the second organic diode OD2 can be electrically connected to a second voltage line VL2. The second voltage line VL2 can be configured to deliver a second voltage V L to the second electrode of the second organic diode OD2. The first voltage V H applied to the first voltage line VL1 can be greater than the second voltage V L .

[0174] In an embodiment, the first voltage V H may be a gate high voltage, and the second voltage V L may be a gate low voltage. The gate high voltage can be a voltage used to turn on a gate of a transistor connected to a gate line, and the gate low voltage can be a voltage used to turn off the gate of the transistor connected to the gate line. In another embodiment, the second voltage V L may be a second power voltage (see ELVSS of Figure 2 ) or a ground voltage.

[0175] By electrostatic, when a voltage applied to the first wiring WL1 or the second wiring WL2 is greater than the first voltage V HWhen the sum of the threshold voltage of the first organic diode OD1 and the threshold voltage of the second organic diode OD2 is reached, a positive charge can flow through the first voltage line VL1 through the first organic diode OD1. By static electricity, when the voltage applied to the first wiring WL1 or the second wiring WL2 is lower than the second voltage V L When the sum of the threshold voltage of the first organic diode OD1 and the threshold voltage of the second organic diode OD2 is reached, a positive charge can flow through the first voltage line VL1 through the first organic diode OD1. By static electricity, when the voltage applied to the first wiring WL1 or the second wiring WL2 is lower than the second voltage V

[0176] Reference Figure 10 In an embodiment, each of the protection circuits SC can include the first organic diode OD1 and the rectifier transistor TD.

[0177] The first organic diode OD1 can include a first electrode, a second electrode on the first electrode, and an organic layer between the first electrode and the second electrode. The rectifier transistor TD can include a semiconductor layer, a source electrode, a drain electrode, and a gate electrode, and the gate electrode of the rectifier transistor TD can be electrically connected to the drain electrode of the rectifier transistor TD.

[0178] The first electrode of the first organic diode OD1 and the gate electrode of the rectifier transistor TD belonging to one protection circuit SC can be electrically connected to the same wiring. For example, the first electrode of the first organic diode OD1 and the gate electrode and the drain electrode of the rectifier transistor TD belonging to the protection circuit SC on the first terminal of the transistor TR can be electrically connected to the first wiring WL1. The first electrode of the first organic diode OD1 and the gate electrode and the drain electrode of the rectifier transistor TD belonging to the protection circuit SC on the second terminal of the transistor TR can be electrically connected to the second wiring WL2. The second electrode of the first organic diode OD1 can be electrically connected to the first voltage line VL1, and the source electrode of the rectifier transistor TD can be electrically connected to the second voltage line VL2.

[0179] In another embodiment, each of the protection circuits SC can include the rectifier transistor TD and the second organic diode (see Figure 9 OD2) whose second electrode is electrically connected to the second voltage line VL2. In this case, the gate electrode and the drain electrode of the rectifier transistor TD can be electrically connected to the first voltage line VL1.

[0180] In an embodiment of the disclosure, at least one rectifier device of the protection circuit SC can be formed as an organic diode, so that the area of the protection circuit SC can be reduced. In this case, the organic diode can be formed at the same time as the organic light emitting diode OLED of the display area DA, so that the protection circuit SC can be formed without increasing the manufacturing process.

[0181] Figure 11 is a plan view schematically showing a portion of a display device according to an embodiment, and Figure 12 is a cross-sectional view taken along line I-I' of Figure 11 , and schematically shows the display device.

[0182] Figure 11 and Figure 12 The electrostatic blocking unit EC shown in Figure 6 may be applied to the first demultiplexer 510 as shown in Figure 8 , or can be applied to the second demultiplexer 520 as shown in Figure 11 , for example. Figure 12 The transistor TR shown in Figure 6 may correspond to the first switching transistor T11,..., and T4n of the first demultiplexer (see 510 of Figure 8 ) or the second switching transistor M1, M2, M3, and M4 of the second demultiplexer (see 520 of

[0183] When the transistor TR is one of the first switching transistors T11,..., and T4n, the first wiring WL1 can correspond to the first connection wiring TL1, the second wiring WL2 can correspond to the second connection wiring TL2, and the control signal line CSL can correspond to the first control signal line ESL. When the transistor TR is one of the second switching transistors M1, M2, M3, and M4, the first wiring WL1 can correspond to the third connection wiring TL3, the second wiring WL2 can correspond to the fourth connection wiring TL4, and the control signal line CSL can correspond to the second control signal line GSL.

[0184] With reference to Figure 11 and Figure 12 , the electrostatic blocking unit EC can include a protection circuit SC electrically connected to the first wiring WL1.

[0185] The buffer layer 201 can be disposed on the substrate 100, and the transistor TR can be disposed on the buffer layer 201. The transistor TR can be a thin film transistor, and can include a semiconductor layer Act, a gate electrode GE, a first source-drain electrode SD1, and a second source-drain electrode SD2.

[0186] The semiconductor layer Act of the transistor TR can be disposed on the buffer layer 201 and can include polysilicon. In another embodiment, the semiconductor layer Act can include amorphous silicon. In another embodiment, the semiconductor layer Act can include an oxide of at least one material selected from the group consisting of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), and zinc (Zn). The semiconductor layer Act can include a channel region, and source and drain regions doped with impurities. The source and drain regions can be connected to two opposite sides of the channel region.

[0187] The first gate insulating layer 203 can be disposed to cover the semiconductor layer Act, and the gate electrode GE can be disposed on the first gate insulating layer 203 to overlap the semiconductor layer Act of the transistor TR. The second gate insulating layer 204 and the interlayer insulating layer 205 can be disposed on the gate electrode GE.

[0188] The first source-drain electrode SD1 and the second source-drain electrode SD2 can be disposed on the interlayer insulating layer 205. The first source-drain electrode SD1 can be connected to one of the source and drain regions of the semiconductor layer Act through a contact hole, and the second source-drain electrode SD2 can be connected to the other of the source and drain regions of the semiconductor layer Act through a contact hole. The first source-drain electrode SD1 and the second source-drain electrode SD2, and the source electrode SE and the drain electrode DE of the thin film transistor TFT shown in FIG. 1B can have the same material. Figure 4 The source electrode SE and the drain electrode DE of the thin film transistor TFT shown in FIG. 1B can have the same material. As used herein, the first source-drain electrode SD1 and the second source-drain electrode SD2 including the same material means that the first source-drain electrode SD1 and the second source-drain electrode SD2 are simultaneously formed to have the same material, film, layer structure, etc. by the same process.

[0189] The first planarization insulating layer 207 can be disposed on the first source-drain electrode SD1 and the second source-drain electrode SD2, and the first wiring WL1 and the second wiring WL2 can be disposed on the first planarization insulating layer 207. The first wiring WL1 can be connected to the first source-drain electrode SD1 through a contact hole passing through the first planarization insulating layer 207, and the second wiring WL2 can be connected to the second source-drain electrode SD2 through a contact hole passing through the first planarization insulating layer 207.

[0190] The second planarization insulating layer 208 can be disposed on the first wiring WL1 and the second wiring WL2, and the protection circuit SC can be disposed on the second planarization insulating layer 208. Each of the protection circuits SC can include the first organic diode OD1 and the second organic diode OD2.

[0191] The first electrode 610a of the first organic diode OD1 and the first electrode 610b of the second organic diode OD2 can be disposed on the second planarization insulating layer 208. Each of the first electrode 610a of the first organic diode OD1 and the first electrode 610b of the second organic diode OD2 can be connected to the first wiring WL1 through a contact hole passing through the second planarization insulating layer 208.

[0192] The first electrode 610a of the first organic diode OD1 and the first electrode 610b of the second organic diode OD2, and Figure 4 The pixel electrode 210 of the organic light emitting diode OLED illustrated in FIG. 1A can have the same material. In other words, the first electrode 610a of the first organic diode OD1 and the first electrode 610b of the second organic diode OD2 can be formed by the same process as a process of forming the pixel electrode 210 of the organic light emitting diode OLED.

[0193] In a plan view, the first electrode 610a of the first organic diode OD1 and the first electrode 610b of the second organic diode OD2 can be disposed to overlap the first wiring WL1. When the first wiring WL1 and the second wiring WL2 extend in a first direction (e.g., a y-axis direction), the first electrode 610a of the first organic diode OD1 can be disposed along an imaginary first straight line L1 extending in a second direction (e.g., an x-axis direction) to be spaced apart from each other. The first electrode 610b of the second organic diode OD2 can be disposed along an imaginary second straight line L2 extending in the second direction (e.g., the x-axis direction) to be spaced apart from each other.

[0194] The pixel definition layer 209 can be configured to cover edges of each of the first electrode 610a of the first organic diode OD1 and the first electrode 610b of the second organic diode OD2 on the second planarization insulating layer 208, and can include an opening for exposing a center of each of the first electrode 610a of the first organic diode OD1 and the first electrode 610b of the second organic diode OD2.

[0195] The first organic layer 620a can be disposed between the first electrode 610a and the second electrode 630a of the first organic diode OD1, and the second organic layer 620b can be disposed between the first electrode 610b and the second electrode 630b of the second organic diode OD2. The first organic layer 620a and the second organic layer 620b, and Figure 4 Each of the intermediate layers 220 of the organic light emitting diode OLED illustrated in FIG. 1A can include the same material. For example, each of the first organic layer 620a and the second organic layer 620b can include a first sub organic layer 621, a second sub organic layer 622, and a third sub organic layer 623. The first sub organic layer 621 and the first functional layer (seeFigure 4 The 221) can include the same material, the second sub-organic layer 622 and the light emitting layer (see Figure 4 The 222) can include the same material, and the third sub-organic layer 623 and the second functional layer (see Figure 4 The 223) can include the same material. In an embodiment, one or more of the first sub-organic layer 621, the second sub-organic layer 622, and the third sub-organic layer 623 can be omitted. For example, each of the first organic layer 620a and the second organic layer 620b can include only the first sub-organic layer 621 and the third sub-organic layer 623. Alternatively, each of the first organic layer 620a and the second organic layer 620b can include only the first sub-organic layer 621 or the third sub-organic layer 623.

[0196] The second electrode 630a of the first organic diode OD1 and the second electrode 630b of the second organic diode OD2, and Figure 4 Figure 4 Each of the opposite electrodes 230 of the organic light emitting diode OLED shown in the can include the same material.

[0197] In a plan view, the second electrodes 630a of the first organic diodes OD1 adjacent in a second direction (for example, an x-axis direction) can be integrally formed. In other words, the second electrodes 630a of the first organic diodes OD1 arranged along an imaginary first straight line L1 can be integrated as a single body. The second electrodes 630a of the first organic diodes OD1 can be electrically connected to a first voltage line (not shown).

[0198] In a plan view, the second electrodes 630b of the second organic diodes OD2 adjacent in a second direction (for example, an x-axis direction) can be integrally formed. In other words, the second electrodes 630b of the second organic diodes OD2 arranged along an imaginary second straight line L2 can be integrally provided. The second electrodes 630b of the second organic diodes OD2 can be electrically connected to a second voltage line (not shown). The first voltage line can be configured to transmit a first voltage, the second voltage line can be configured to transmit a second voltage, and the first voltage can be greater than the second voltage.

[0199] The first organic diodes OD1 and the second organic diodes OD2 are formed above the first wiring line WL1 or the second wiring line WL2, and in a plan view, the electrostatic blocking unit EC can be arranged to overlap the touch signal distribution unit. Accordingly, an area occupied by the touch signal distribution unit and the electrostatic blocking unit EC can be reduced.

[0200] The encapsulation layer 300 can be disposed on the protection circuit SC. The encapsulation layer 300 can include a first inorganic encapsulation layer 310 and a second inorganic encapsulation layer 330, and an organic encapsulation layer 320 therebetween.

[0201] According to one or more embodiments, a display device in which a circuit defect due to static electricity can be reduced can be implemented. Of course, the scope of the present disclosure is not limited by these effects.

[0202] It should be understood that the embodiments described herein should be considered in a descriptive sense only and not for purposes of limitation. Descriptions of features or aspects within each embodiment should typically be considered as being applicable to other similar features or aspects in other embodiments. While one or more embodiments have been described with reference to the figures, it will be understood by those of ordinary skill in the art that various changes in form and details can be made therein without departing from the spirit and scope as defined by the following claims.

Claims

1. A display device, characterized by comprising: comprises: a substrate including a display area and a peripheral area outside the display area; light emitting diodes arranged in the display area; an electrode unit including electrode groups arranged on the light emitting diodes; a touch driving pad arranged in the peripheral area; a touch signal distribution unit arranged in the peripheral area and electrically connected between the electrode unit and the touch driving pad; and an electrostatic blocking unit electrically connected to the touch signal distribution unit and including organic diodes, wherein each of the organic diodes includes a first electrode, a second electrode arranged on the first electrode, and an organic layer between the first electrode and the second electrode. each of the light emitting diodes includes a pixel electrode, an opposite electrode arranged on the pixel electrode, and an intermediate layer between the pixel electrode and the opposite electrode, and the first electrode and the pixel electrode include the same material, and the second electrode and the opposite electrode include the same material, and 2. The display device according to claim 1, wherein wherein the intermediate layer includes a light emitting layer, a first functional layer between the pixel electrode and the light emitting layer, and a second functional layer between the opposite electrode and the light emitting layer, and the organic layer includes the same material as at least one of the first functional layer and the second functional layer. the organic diodes include a first organic diode and a second organic diode, and a second electrode of the first organic diode is electrically connected to a first voltage line, and a second electrode of the second organic diode is electrically connected to a second voltage line, and a first voltage applied to the first voltage line is greater than a second voltage applied to the second voltage line.

3. The display device according to claim 1, wherein the electrostatic blocking unit further includes rectifier transistors, and the second electrode of each of the organic diodes is electrically connected to a first voltage line, and each of the rectifier transistors includes a semiconductor layer and a gate electrode on the semiconductor layer, wherein the semiconductor layer includes a source region, a drain region, and a channel region between the source region and the drain region, and the gate electrode is electrically connected to the drain region, and the source region is electrically connected to a second voltage line.

4. The display device according to claim 1, wherein the touch signal distribution unit includes a first demultiplexer and a second demultiplexer, and the first demultiplexer includes sub-demultiplexers, and each of the sub-demultiplexers is electrically connected between one of the electrode groups and the touch driving pad, and 5. The display device according to claim 1, wherein wherein the second demultiplexer is configured to sequentially connect the sub-demultiplexers to the touch driving pad in response to a first control signal, and the sub-demultiplexers are configured to sequentially connect touch electrodes of the respective electrode groups to the second demultiplexer in response to a second control signal. the electrostatic blocking unit includes a first blocking unit and a second blocking unit arranged at two opposite sides of the first demultiplexer.

6. The display device according to claim 5, wherein the electrostatic blocking unit includes a third blocking unit and a fourth blocking unit arranged at two opposite sides of the second demultiplexer.

7. The display device according to claim 5, wherein each of the sub-demultiplexers includes:

8. The display device according to claim 5, wherein a first switching transistor; ​ a first connection wiring configured to electrically connect the first source-drain electrode of each of the first switching transistors to a respective touch electrode; and a second connection wiring configured to electrically connect the second source-drain electrode of each of the first switching transistors to the second demultiplexer, wherein the second demultiplexer includes: a second switching transistor; a third connection wiring configured to electrically connect the first source-drain electrode of each of the second switching transistors to a respective sub-demultiplexer; and a fourth connection wiring configured to electrically connect the second source-drain electrode of each of the second switching transistors to the touch drive pad.

9. The display device of claim 8, wherein, the first electrode of each of the organic diodes is electrically connected to one of the first connection wiring, the second connection wiring, the third connection wiring, and the fourth connection wiring, and the second electrode of each of the organic diodes is electrically connected to either the first voltage line or the second voltage line.

10. The display device according to claim 8, wherein the first electrode of each of the organic diodes overlaps with one of the first connection wiring, the second connection wiring, the third connection wiring, and the fourth connection wiring in a plan view, and wherein the first connection wiring, the second connection wiring, the third connection wiring, and the fourth connection wiring extend in a first direction, and the second electrodes of the organic diodes are arranged along an imaginary straight line extending in a second direction that crosses the first direction, and are integrated as a single body.

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