Compatible control system of DDR4 and DDR5

Abstract

The utility model relates to the technical field of computers, in particular to a DDR4 and DDR5 compatible control system. Comprising a mainboard and a trigger module, the mainboard comprises a BIOS (Basic Input / Output System) firmware module; the output end of the main board is connected with the input end of the trigger module, and the trigger module is used for controlling the level state of the output end of the trigger module according to an output signal of the output end of the main board; the output end of the trigger module is connected with the input end of the mainboard, and the trigger module is used for the BIOS firmware module to call the corresponding DDR configuration parameters according to the level state so as to complete startup operation according to the called DDR configuration parameters. According to the method, the technical effect that one set of BIOS firmware is shared on the DDR4 platform and the DDR5 platform can be achieved, and a BIOS firmware scheme capable of efficiently and flexibly supporting multiple memory types is provided.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computers, and in particular to a compatible control system for DDR4 and DDR5. BACKGROUND

[0002] With the rapid development of computer technology, the demand for increasing memory performance has stimulated the rapid emergence of DDR5 memory technology. However, there is a huge difference in the budget and performance demand of different users in the market, which also leads to the coexistence of different levels of hardware platforms. The traditional BIOS firmware solution lacks flexibility and needs to be developed separately for different memory types such as DDR4 and DDR5, which leads to waste of resources, increased development difficulty and rising maintenance costs.

[0003] The common solution at this stage is to develop two independent BIOS firmware, respectively adapting to DDR4 and DDR5 platforms. Although this solution can meet the needs of users, it also has obvious disadvantages. First, developing two independent firmware requires higher cost and time investment; second, this will lead to additional storage space consumption, further reducing the efficiency of the hardware platform.

[0004] Therefore, there is an urgent need for a BIOS firmware solution that can efficiently and flexibly support multiple memory types to address the shortcomings of traditional solutions and optimize resource utilization and development costs. CONTENT OF THE INVENTION

[0005] In order to overcome the shortcomings of the prior art, the present application provides a compatible control system for DDR4 and DDR5, thereby achieving the technical effect of sharing one set of BIOS firmware on DDR4 and DDR5 platforms, to provide a BIOS firmware solution that can efficiently and flexibly support multiple memory types.

[0006] The technical solution adopted by the present application to solve its technical problems is:

[0007] A compatible control system for DDR4 and DDR5, comprising: a mainboard and a trigger module; the mainboard comprises a BIOS firmware module;

[0008] The output end of the mainboard is connected to the input end of the trigger module, for the trigger module to control the level state of the output end of the trigger module according to the output signal of the output end of the mainboard;

[0009] The output end of the trigger module is connected to the input end of the mainboard, for the BIOS firmware module to call corresponding DDR configuration parameters according to the level state, to complete the boot operation according to the called DDR configuration parameters.

[0010] Optionally, the trigger module comprises a first resistor or a second resistor; the resistance of the first resistor is greater than the resistance of the second resistor.

[0011] If the trigger module comprises the first resistor, one end of the first resistor is connected to the output end of the mainboard, and the other end is grounded and connected to the input end of the mainboard.

[0012] If the trigger module comprises the second resistor, one end of the second resistor is connected to the input end of the mainboard and the output end of the mainboard, and the other end is grounded.

[0013] Optionally, the resistance of the first resistor is 4.7KΩ.

[0014] Optionally, the resistance of the second resistor is 1KΩ.

[0015] Optionally, the BIOS firmware module comprises DDR4 configuration parameters and DDR5 configuration parameters.

[0016] Optionally, the mainboard comprises a CPU module, a PCIE to SATA module, a PCIE to USB module, a BMC module, a PCIE to GBE module, an M.2 module, an mPCIE module, a PCIEX16 SLOT module and a SlimSAS module; the CPU module comprises CPU0 and CPU1.

[0017] The CPU module is connected with the PCIE to SATA module, the PCIE to USB module, the BMC module, the PCIE to GBE module, the M.2 module, the PCIEX16 SLOT module and the SlimSAS module respectively, and is used to provide PCIE resources.

[0018] The CPU0 and the CPU1 both support four DDR interfaces.

[0019] The CPU0 and the CPU1 are connected through C2C, and are used for communication between the CPU0 and the CPU1.

[0020] Optionally, the CPU0 and the CPU1 adopt S5000C-32, S5000C-16 or S5000C-64.

[0021] Optionally, the DDR interface is a DDR4 interface or a DDR5 interface; each DDR4 interface supports 1.2V DDR4 RDIMM / UDIMM; and each DDR5 interface supports 1.1V DDR4 RDIMM / UDIMM.

[0022] The beneficial effects of the present application are: the system is composed of a mainboard and a trigger module, the mainboard is embedded with a BIOS firmware module, the output end of the mainboard is connected to the input end of the trigger module, the trigger module controls the output level state according to the output signal of the mainboard, the output end of the trigger module is connected to the input end of the mainboard, the BIOS firmware module can read the level state of the trigger module, and different DDR configuration parameters are called according to different level states. Based on this, the system does not need to develop independent BIOS firmware, and can automatically select the corresponding configuration according to the detected memory type, realizing efficient and flexible support for multiple memory types. From the hardware point of view, the trigger module plays a bridge role in signal conversion, converting the mainboard output signal into the level state required by the BIOS firmware, ensuring that the BIOS firmware can identify and control the characteristics of different types of memory. BRIEF DESCRIPTION OF DRAWINGS

[0023] Figure 1 is a module connection diagram of a compatible control system of DDR4 and DDR5 provided by an embodiment of the present application;

[0024] Figure 2 is a circuit principle diagram of a trigger module of a compatible control system of DDR4 and DDR5 provided by an embodiment of the present application;

[0025] Figure 3 is a first circuit principle diagram of a mainboard of a compatible control system of DDR4 and DDR5 provided by an embodiment of the present application;

[0026] Figure 4 is a second circuit principle diagram of a mainboard of a compatible control system of DDR4 and DDR5 provided by an embodiment of the present application. DETAILED DESCRIPTION

[0027] The present application will be further described below in combination with the drawings and embodiments.

[0028] The concept, specific structure and technical effects of the present application will be described clearly and completely in combination with embodiments and drawings, so as to fully understand the purpose, features and effects of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all the embodiments, and other embodiments obtained by those skilled in the art based on the embodiments of the present application without creative labor are within the scope of protection of the present application. In addition, all the coupling / connection relations involved in the patent do not mean that the components are directly connected, but that the optimal coupling structure can be composed by adding or reducing coupling accessories according to the specific implementation situation. The technical features in the creation of the present application can be interactively combined without mutual contradiction and conflict.

[0029] REFERENCE Figure 1 , Figure 1is a module connection diagram of a DDR4 and DDR5 compatible control system provided by an embodiment of the present application, comprising a mainboard and a trigger module, wherein the mainboard comprises a BIOS firmware module. The following will be described in combination with Figure 1 The system will be specifically described:

[0030] The output end of the mainboard is connected to the input end of the trigger module.

[0031] Specifically, the above connection is used for the trigger module to control the level state of the output end of the trigger module according to the output signal of the output end of the mainboard. When the mainboard is powered on, the control signal corresponding to the mainboard is generated through the potential adjustment of the output end of the mainboard, thereby affecting the level state of the output end of the trigger module. In the embodiment of the present application, when the mainboard is a DDR4 mainboard, the mainboard is powered on after being connected, the output end of the trigger module is selected to be pulled up, and a high-level signal is generated; when the mainboard is a DDR5 mainboard, the mainboard is powered on after being connected, the output end of the trigger module is selected to be pulled down, and a low-level signal is generated. According to the level of the output end of the trigger module, the mainboard will call the saved corresponding memory configuration parameters.

[0032] The output end of the trigger module is connected to the input end of the mainboard.

[0033] Specifically, the above connection is used for the BIOS firmware module to call the corresponding DDR configuration parameters according to the level state, so as to complete the boot operation according to the called DDR configuration parameters. In the embodiment, when the mainboard is a DDR4 mainboard, the high level is output to the input end of the mainboard (i.e. input to the CPU) by selecting the pull-up of the trigger module, and the mainboard will call the memory configuration parameters of DDR4 stored in the BIOS firmware according to the sampled high level; similarly, when the mainboard is a DDR5 mainboard, the low level is output by selecting the pull-down of the trigger module, and the low level will make the system call the memory configuration parameters of DDR5 of the BIOS firmware.

[0034] More specifically, before this, BIOS firmware packaging is needed, that is, the memory configuration parameters of DDR4 and DDR5 are integrated into the same BIOS firmware, that is, the BIOS firmware module comprises DDR4 configuration parameters and DDR5 configuration parameters.

[0035] The memory configuration parameters include timing, voltage, frequency, etc., to ensure that the BIOS can correctly initialize different types of memories.

[0036] BIOS (Basic Input / Output System, basic input / output system) is a firmware embedded on the motherboard of a computer, responsible for hardware initialization, self-checking (POST, Power-On Self-Test) and loading the operating system when the computer starts up. BIOS firmware is a program code stored in a non-volatile memory (such as ROM, EEPROM or flash memory) on the motherboard.

[0037] DDR (Double Data Rate, double data rate) is a memory technology used to increase the data transfer rate of memory modules. DDR4 and DDR5 are the fourth and fifth generations, respectively.

[0038] Further, in another embodiment provided by the present application, the BIOS firmware module can also read the SPD (Serial Presence Detect) information of the memory through the I2C (Inter-Integrated Circuit) bus connecting the memory and the BIOS firmware module, to determine whether the currently installed memory is DDR4 or DDR5 according to the SPD information, and then call the corresponding memory configuration parameters saved according to the determination result.

[0039] SPD is a small chip on the memory module that stores key information such as memory specifications, timing, voltage, etc., i.e. SPD information. The SPD information contains the type identification of the memory, and the BIOS can determine the type of memory through these identifications.

[0040] Specifically, if it is determined to be DDR4 memory, the BIOS will call the pre-packaged DDR4 memory configuration parameters in the firmware and use these parameters to initialize the memory. If it is determined to be DDR5 memory, the BIOS will call the DDR5 memory configuration parameters to initialize the memory. After correctly configuring the memory parameters, the BIOS will continue to execute the subsequent startup process, including initializing other hardware devices, loading the operating system, etc., until the boot-up process is completed.

[0041] It can be seen that the present application provides two ways to determine the type of installed memory, through the I2C bus and through the GPIO level state, and then calls the corresponding memory parameters. On this basis, the user can choose one of the two ways to implement the compatible system provided by the present application according to the actual needs; further, the two compatible ways can also be combined for use, to determine the accuracy of one memory type determination method through the other memory type determination method, thereby improving the reliability of compatibility, which can be debugged by the user.

[0042] Further, referring to Figure 2 , Figure 2is a circuit schematic of a trigger module of a compatible control system of DDR4 and DDR5 provided by an embodiment of the present application, the trigger module comprises a first resistor or a second resistor; the resistance value of the first resistor is greater than the resistance value of the second resistor.

[0043] Specifically, the trigger module reserves two resistor patch positions (only one is used in actual cases, and a patch resistor is usually used), and only the first resistor or the second resistor needs to be selected according to the different mainboards to be connected.

[0044] More specifically, if the trigger module comprises the first resistor, one end of the first resistor is connected to the output end of the mainboard, and the other end is grounded and connected to the input end of the mainboard.

[0045] Specifically, when the mainboard is a DDR4 mainboard, pull-up is selected, and in this case, the first resistor R1 is mounted, so that when the DDR4 mainboard is powered on, the signal output by the CPU0_GPIO_P1V8 pin is pulled up through the first resistor R1, so that the DDR4_DDR5_SELECT pin is at a high level. The high level state is sensed by a pin of the CPU (i.e. the input end of the mainboard), and the mainboard will call the DDR4 configuration parameters in the PBF header file in the BIOS firmware, and continue to complete the subsequent stage process until the boot is completed.

[0046] In the embodiment of the present application, a weak pull-up and strong pull-down strategy is adopted, and the resistance value of the first resistor should be greater than that of the second resistor. In this embodiment, the resistance value of the first resistor can be 4.7KΩ. Wherein, the weak pull-up is mainly used to maintain the stability of the signal line and provide current protection, and the strong pull-down is used to quickly change the signal state and provide strong driving ability.

[0047] Wherein, the PBF header file (Protocol Buffer Binary Format Header File) is a file format related to Protocol Buffers (Protobuf for short). Protobuf is a lightweight and efficient data serialization protocol developed by Google, which is used for structured data storage and transmission.

[0048] Further, if the trigger module comprises the second resistor, one end of the second resistor is connected to the input end of the mainboard and the output end of the mainboard, and the other end is grounded.

[0049] Specifically, the pull-down is selected when the mainboard is a DDR5 mainboard, in which case the second resistor R2 is connected, so that when the DDR5 mainboard is powered on, the signal output through the CPU0_GPIO_P1V8 pin passes through the second resistor R2 to the pull-down, so that the DDR4_DDR5_SELECT pin is at a low level, which is sensed by a pin of the CPU (i.e. the input end of the mainboard), and the mainboard will call the DDR5 configuration parameter in the PBF header file in the BIOS firmware, and continue to complete the subsequent stage process until the boot is completed.

[0050] More specifically, the second resistor R2 in the embodiment can be between 1KΩ and 0.1KΩ.

[0051] Further, with reference to Figure 3 , Figure 4 , Figure 3 is a first circuit schematic diagram of a mainboard of a DDR4 and DDR5 compatible control system provided by an embodiment of the application, Figure 4 is a second circuit schematic diagram of a mainboard of a DDR4 and DDR5 compatible control system provided by an embodiment of the application. Wherein, Figure 3 is a connection diagram of a DDR4 mainboard, Figure 4 is a connection diagram of a DDR5 mainboard, and the connection modes of the two are basically the same, which will be described in detail below:

[0052] The mainboard comprises a CPU module, a PCIE to SATA module, a PCIE to USB module, a BMC module, a PCIE to GBE module, an M.2 module, an mPCIE module, a PCIEX16 SLOT module and a SlimSAS module; the CPU module comprises CPU0 and CPU1.

[0053] Specifically, the model of the CPU0 and the CPU1 can be S5000C-32, S5000C-16 or S5000C-64, etc.

[0054] Further, the CPU module is connected with the PCIE to SATA module, the PCIE to USB module, the BMC module, the PCIE to GBE module, the M.2 module, the PCIEX16 SLOT module and the SlimSAS module respectively, for providing PCIE resources.

[0055] Specifically, the PCIEX16 SLOT module comprises PCIEX16 SLOT0 / 1 / 2 / 3 / 4, and the SlimSAS module comprises SlimSAS0 / 1 / 2 / 3.

[0056] The CPU0 and the CPU1 both support four DDR interfaces.

[0057] Specifically, the DDR interface is a DDR4 interface or a DDR5 interface, which is a DDR4 interface when the mainboard is a DDR4 mainboard, and which is a DDR5 interface when the mainboard is a DDR5 mainboard. Each of the DDR4 interfaces supports 1.2V DDR4 RDIMM / UDIMM, and each of the DDR5 interfaces supports 1.1V DDR4 RDIMM / UDIMM.

[0058] The CPU0 and the CPU1 are connected through C2C, for communication between the CPU0 and the CPU1.

[0059] The above is a specific description of the preferred embodiment of the application, but the application creation is not limited to the embodiments, and those skilled in the art can make various equivalent modifications or replacements without departing from the spirit of the application. These equivalent modifications or replacements are all included in the scope defined by the claims of the application.

Claims

1. A compatible control system of DDR4 and DDR5, characterized in that, The application relates to a mainboard and a trigger module; the mainboard comprises a BIOS firmware module; an output end of the mainboard is connected with an input end of the trigger module, so that the trigger module controls the level state of an output end of the trigger module according to the output signal of the output end of the mainboard; the output end of the trigger module is connected with an input end of the mainboard, so that the BIOS firmware module calls corresponding DDR configuration parameters according to the level state, and completes booting operation according to the called DDR configuration parameters. The trigger module comprises a first resistor or a second resistor; the resistance value of the first resistor is greater than that of the second resistor. If the trigger module comprises the first resistor, one end of the first resistor is connected with the output end of the mainboard, and the other end is grounded and connected with the input end of the mainboard. If the trigger module comprises the second resistor, one end of the second resistor is connected with the input end of the mainboard and the output end of the mainboard, and the other end is grounded.

2. The compatible control system of DDR4 and DDR5 according to claim 1, wherein, The resistance value of the first resistor is 4.7K omega. The resistance value of the second resistor is 1K omega. The BIOS firmware module comprises DDR4 configuration parameters and DDR5 configuration parameters.

3. The compatible control system of DDR4 and DDR5 according to claim 2, characterized in that, The mainboard comprises a CPU module, a PCIE-to-SATA module, a PCIE-to-USB module, a BMC module, a PCIE-to-GBE module, an M.2 module, an mPCIE module, a PCIEX16 SLOT module and a SlimSAS module; the CPU module comprises CPU0 and CPU1.

4. The compatible control system of DDR4 and DDR5 according to claim 2, characterized in that, The CPU module is connected with the PCIE-to-SATA module, the PCIE-to-USB module, the BMC module, the PCIE-to-GBE module, the M.2 module, the PCIEX16 SLOT module and the SlimSAS module respectively, and is used for providing PCIE resources.

5. The compatible control system of DDR4 and DDR5 according to claim 1, wherein, The CPU0 and the CPU1 both support four DDR interfaces.

6. The compatible control system of DDR4 and DDR5 according to claim 1, wherein, The CPU0 and the CPU1 are connected through C2C, and are used for communication between the CPU0 and the CPU1. The CPU0 and the CPU1 adopt S5000C-32, S5000C-16 or S5000C-64. The DDR interface is a DDR4 interface or a DDR5 interface; Each DDR4 interface supports 1.2V DDR4 RDIMM / UDIMM; and each DDR5 interface supports 1.1V DDR4 RDIMM / UDIMM.

7. The compatible control system of DDR4 and DDR5 according to claim 6, characterized in that, ​ 8. The compatible control system of DDR4 and DDR5 according to claim 6, wherein, ​ ​

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