Multi-chip parallel packaging structure and intelligent power module
By directly connecting chips in parallel with metal layers and using passivation layers for protection, the problems of dicing stress and bonding line failure in traditional processes are solved, achieving higher chip reliability and power module stability.
Patent Information
- Application Number
- CN202423214868.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-25
- Publication Date
- 2025-11-28
- Estimated Expiration
- 2034-12-25
AI Technical Summary
In traditional multi-chip parallel processes, stress damage and bonding wire failure caused by dicing affect chip performance and reliability, especially under mechanical vibration and thermal shock.
The chips are directly connected in parallel using metal layers, protected by a passivation layer to avoid stress damage during the dicing process, and the connection stability is enhanced by using a double metal layer.
It improves the stability and reliability of chip connections, reduces power loss and electrical faults caused by unstable connections, extends the lifespan of chips, and enhances the working efficiency and stability of power modules.
Smart Images
Figure CN223612418U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to power module technical field especially relates to a kind of multi-chip parallel packaging structure and intelligent power module. BACKGROUND
[0002] In the field of high-power power semiconductor devices, implementing chip parallel function is a key technology. Referring to Figure 1 , the traditional method is to divide semiconductor wafer into independent chips by scribing, and then interconnect by welding or bonding wire to achieve multi-chip parallel. However, this traditional scribing and then bonding interconnection process has many drawbacks. First, during mechanical scribing process, stress is generated near the scribing path, causing lattice damage. When the device encounters mechanical vibration or thermal shock, these stresses will further deteriorate, seriously affecting the performance and reliability of the chip. For example, in some high-frequency vibration working environment, the tiny cracks generated by scribing may rapidly expand, leading to unstable electrical performance of the chip. Second, bonding wire failure problems also occur frequently, such as bonding wire damage, breakage, shedding, and bonding wire bending, which can cause open circuit failure. Moreover, during long-term use, the stability of the bonding wire connection gradually decreases due to repeated thermal expansion and contraction and mechanical stress, greatly reducing the reliability of the entire parallel structure.
[0003] Therefore, it is necessary to improve the existing multi-chip parallel method of power modules to overcome the shortcomings of the prior art. SUMMARY
[0004] To overcome the problems in the related art, one of the purposes of the present utility model is to provide a multi-chip parallel packaging structure that directly connects chips in parallel through a metal layer, changing the existing method of scribing and dividing chips and then connecting them in parallel through bonding wires, which can avoid damage to the chips during the scribing process and improve the stability of chip connection.
[0005] A multi-chip parallel packaging structure includes:
[0006] A plurality of chips are connected in parallel with each other through a metal layer between adjacent two chips, and a passivation layer is provided on the metal layer.
[0007] In the preferred technical solution of the present utility model, the first metal layer is connected in parallel with each other between adjacent two chips, and the opposite sides of the first metal layer are respectively connected to the top of one chip.
[0008] In the preferred technical solution of the present utility model, the thickness of the first metal layer is 8 mil-20 mil.
[0009] In the preferable technical scheme of the utility model, the top of the two adjacent chips is provided with a first metal layer, and a passivation layer is arranged between the two adjacent first metal layers.
[0010] The top of the two adjacent first metal layers is provided with a second metal layer, and the two adjacent first metal layers are connected in parallel through the second metal layer.
[0011] In the preferable technical scheme of the utility model, the thickness of the first metal layer is 6mil-12mil, and the thickness of the second metal layer is 7mil-150mil.
[0012] The second purpose of the utility model is to provide an intelligent power module comprising the multi-chip parallel packaging structure.
[0013] In the preferable technical scheme of the utility model, the utility model further comprises a frame, a PCB and a substrate, the PCB and the substrate are arranged in the frame, and the multi-chip parallel packaging structure is arranged on the substrate.
[0014] In the preferable technical scheme of the utility model, the bottom of the substrate is provided with a heat dissipation structure, and the heat dissipation structure comprises a plurality of heat dissipation channels extending from the substrate to the outside of the plastic package body of the intelligent power module.
[0015] The utility model has the advantages of:
[0016] The multi-chip parallel packaging structure comprises a plurality of chips, the two adjacent chips are connected in parallel through a metal layer, and a passivation layer is arranged on the metal layer. The multi-chip parallel packaging structure directly connects the chips by using the metal layer, and the slicing process is not needed, so that the influence of slicing stress on the chips is eliminated from the source. In the long-term use process, the chips can maintain a more complete crystal structure, the performance decline and reliability problems caused by lattice defects are reduced, such as increased leakage, reduced breakdown voltage and the like, so that the service life of the chips is prolonged, and the reliability of the entire power module is improved. The metal layer is firmly connected with the chip electrode through the close deposition and photolithography process, and can withstand greater mechanical stress and temperature change. The power loss and electrical failure caused by unstable connection are reduced, and the working efficiency and stability of the power module are improved. BRIEF DESCRIPTION OF DRAWINGS
[0017] REFERENCE SIGNS:
[0018] 1, chip; 2, metal layer; 3, passivation layer; 4, slicing channel; 5, first metal layer; 6, second metal layer; 7, frame; 8, substrate; 9, heat dissipation structure. BRIEF DESCRIPTION OF DRAWINGS:
[0020] Figure 1 is a structural schematic view of the prior multi-chip parallel packaging structure provided by the utility model;
[0021] Figure 2 is a structural schematic view of the multi-chip parallel packaging structure provided in embodiment 1 of the utility model;
[0022] Figure 3 is a structural schematic view of the multi-chip parallel packaging structure provided in embodiment 2 of the utility model;
[0023] Figure 4 is a structural schematic view of the intelligent power module provided in the embodiment of the utility model. DETAILED DESCRIPTION
[0024] The preferred embodiments of the utility model will be described in more detail below with reference to the drawings. Although the preferred embodiments of the utility model are shown in the drawings, it should be understood that the utility model can be implemented in various forms and should not be limited by the embodiments described herein. On the contrary, these embodiments are provided to make the utility model more thorough and complete, and to fully convey the scope of the utility model to those skilled in the art.
[0025] In the field of high-power power semiconductor devices, implementing chip parallel function is a key technology. The traditional method is to divide the semiconductor wafer into independent chips by scribing, and then interconnect by means of welding or bonding wires to achieve multi-chip parallel. However, this traditional scribing and then bonding interconnection process has many drawbacks. First, in the mechanical scribing process, stress will be generated near the scribe line, causing lattice damage. When the device encounters mechanical vibration or thermal shock, these stresses will further deteriorate, seriously affecting the performance and reliability of the chip. For example, in some high-frequency vibration working environments, the tiny cracks caused by scribing may rapidly expand, leading to unstable electrical performance of the chip. Secondly, the bonding wire is also prone to failure problems, such as bonding wire damage, breakage, shedding, and bonding wire bending, which often occurs, thereby causing open circuit and other failure phenomena. And in the long-term use process, due to the repeated thermal expansion and contraction and mechanical stress, the stability of the bonding wire connection gradually decreases, greatly reducing the reliability of the entire parallel structure.
[0026] Based on this, the application provides a multi-chip parallel packaging structure.
[0027] Embodiment 1
[0028] As shown in Figures 1-4 , the multi-chip 1 parallel packaging structure provided by the embodiment includes:
[0029] A plurality of chips 1 are connected in parallel with each other by a metal layer 2 between two adjacent chips 1, and a passivation layer 3 is arranged on the metal layer 2.
[0030] The above-mentioned multi-chip 1 parallel packaging structure directly uses a metal layer 2 to connect the chips 1, without the need for a dicing process, thereby eliminating the influence of dicing stress on the chips 1 from the source. In the long-term use process, the chips 1 can maintain a more complete crystal structure, reducing performance degradation and reliability problems caused by lattice defects, such as increased leakage current, reduced breakdown voltage, etc., thereby prolonging the service life of the chips 1 and improving the reliability of the entire power module. The metal layer 2 forms a firm connection with the chip 1 electrode through a tight deposition and photolithography process, and can withstand greater mechanical stress and temperature changes. Reducing power loss and electrical failures caused by unstable connections improves the efficiency and stability of the power module.
[0031] The embodiment provides an implementation in which two adjacent chips 1 are connected to each other by a metal layer 2. Specifically as follows:
[0032] Two adjacent chips 1 are connected in parallel with each other by a first metal layer 52, and opposite sides of the first metal layer 52 are respectively connected to the top of one chip 1.
[0033] Further, the thickness of the first metal layer 52 is 8-20 mil.
[0034] In this implementation, the preparation process is as follows:
[0035] Select a suitable power semiconductor chip 1, such as a silicon carbide (SiC) based power chip 1, which has advantages such as high breakdown electric field and high saturated electron drift speed, and can meet the demand for high power applications. Prepare a high-purity metal material, such as copper (Cu), as the metal layer 2 material. Copper has good electrical conductivity and thermal conductivity, which helps to improve the electrical connection performance and heat dissipation capacity between the chips 1. At the same time, prepare silicon nitride (Si3N4) as the passivation layer 3 material. Silicon nitride has excellent chemical stability, insulation and mechanical strength, and can effectively protect the metal layer 2 and the surface of the chip 1.
[0036] Arrange a plurality of selected chips 1 according to a predetermined layout on a packaging substrate 8, ensure that the spacing between adjacent chips 1 is uniform and meets the design requirements, and provide a good foundation for subsequent deposition of the metal layer 2. Use an electron beam evaporation coating device to deposit copper metal in the gap area between the chips 1, and by precisely controlling the evaporation rate and deposition time, form a metal layer 2 with uniform thickness and good adhesion, achieving electrical connection between adjacent chips 1. During the deposition process, use photolithography technology to define the pattern of the metal layer 2, ensuring that it only forms an effective connection path at the electrode part of the chip 1 that needs to be connected, avoiding problems such as short circuit.
[0037] A silicon nitride passivation layer 3 is grown on the surface of the metal layer 2 using a chemical vapor deposition (CVD) apparatus. By optimizing the CVD process parameters, such as the flow rate of the reaction gas, temperature, and pressure, the silicon nitride passivation layer 3 can tightly cover the metal layer 2, effectively preventing the oxidation of the metal and the erosion of the metal layer 2 by external impurities, while providing a certain mechanical protection effect. After the preparation of the passivation layer 3 is completed, a final packaging process is performed, and a suitable packaging material (such as epoxy resin) is used to seal the chip 1 and the interconnection structure, forming a complete multi-chip 1 parallel packaging structure, protecting the internal structure from the external environment.
[0038] In this embodiment, the first metal layer 52 is used to connect the adjacent two chips 1, and the thickness of the first metal layer 52 is 8 mil-20 mil, which can ensure the electrical connection effect between the adjacent two chips 1.
[0039] Embodiment 2
[0040] This embodiment provides another implementation of the parallel connection of the metal layer 2 between the adjacent two chips 1. In this implementation:
[0041] The top of each of the adjacent two chips 1 is provided with a first metal layer 52, and the passivation layer 3 is arranged between the adjacent two first metal layers 52.
[0042] The top of each of the adjacent two first metal layers 52 is provided with a second metal layer 62, and the adjacent two first metal layers 52 are connected in parallel through the second metal layer 62.
[0043] Further, the thickness of the first metal layer 52 is 6 mil-12 mil, and the thickness of the second metal layer 62 is 7 mil-150 mil.
[0044] In this implementation, the multi-chip 1 parallel packaging structure is manufactured as follows:
[0045] The chip 1 is fixed on a clean packaging substrate 8, and a photolithography technique is used to lithograph the pattern of the first metal layer 52 on the top of the chip 1. Then, a copper layer is deposited on the lithographed pattern area through an electroplating process, forming a first metal layer 52 with a thickness of 6 mil-12 mil, ensuring good ohmic contact with the electrode of the chip 1, and laying a foundation for subsequent electrical connection. After the deposition of the first metal layer 52 is completed, a silicon nitride passivation layer 3 is grown on its surface using a chemical vapor deposition (CVD) apparatus, with a moderate thickness and uniform coverage of the first metal layer 52, preventing its oxidation and contamination by external impurities, and protecting the interface stability of the chip 1 and the first metal layer 52.
[0046] The connection pattern of the second metal layer 62 is photoetched above the first metal layer 52 of the adjacent chip 1 again using the photoetching technology, and the pattern design should ensure that the effective parallel connection between the adjacent chips 1 can be realized. The copper with a thickness of 7 mil-150 mil is deposited in the photoetched pattern area by the processes such as electroplating or physical vapor deposition (PVD), to form the second metal layer 62, so that the reliable electrical connection between the two adjacent first metal layers 52 is realized through the second metal layer 62, and the parallel connection structure between the chips 1 is completed.
[0047] Compared with the single-layer metal layer 2, the double-layer metal layer 2 structure adopted in the embodiment increases the redundancy and mechanical stability of the connection between the chips 1. In a complex working environment, such as under the impact of mechanical vibration or thermal stress, even if slight deformation or damage occurs in a local metal interconnection, the other layer of metal interconnection can still maintain the electrical connection between the chips 1, thereby reducing the probability of the entire power module failure caused by connection failure and improving the reliability and stability of the system.
[0048] Embodiment 3
[0049] The embodiment provides an intelligent power module, which comprises a multi-chip 1 parallel connection packaging structure as described above.
[0050] Specifically, the multi-chip 1 parallel connection packaging structure is arranged on the substrate 8, and the PCB and the substrate 8 are arranged in the frame 7.
[0051] Further, the bottom of the substrate 8 is provided with a heat dissipation structure 9, and the heat dissipation structure 9 comprises a plurality of heat dissipation channels extending from the substrate 8 to the outside of the plastic package body of the intelligent power module.
[0052] The power module adopts the multi-chip 1 parallel connection packaging structure, and the intelligent power module can realize higher power processing capacity. The parallel operation of the plurality of chips 1 can share a large current and power load, thereby improving the applicability of the module in a large power application scenario, such as a large power motor drive in an industrial automation device, an inverter in a new energy power generation system, and the like. Meanwhile, the multi-chip 1 parallel connection packaging structure and the control and driving circuit on the PCB are integrated in the same module, which reduces the complexity and parasitic parameters of the external circuit connection, improves the overall performance and reliability of the system, and realizes the high integration of the power conversion and control functions.
[0053] And the heat dissipation structure 9 effectively solves the heat problem generated when the multi-chip 1 works in parallel. The heat dissipation channel can conduct the heat generated by the chip 1 in time, avoiding the problems such as performance degradation, service life shortening and even failure of the chip 1 due to overheating. In high-power operation, the stable temperature environment helps to keep the electrical performance of the chip 1 stable, reduces the parameter drift caused by temperature change, thereby improving the stability and reliability of the intelligent power module in long-time continuous operation or high-load working condition, prolonging the service life of the module and reducing the maintenance cost.
[0054] In addition, it should be noted that the use of the terms "first", "second", etc. to define parts only facilitates the differentiation of the corresponding parts, and the above terms have no special meaning unless otherwise stated, and therefore cannot be understood as limiting the scope of protection of the present application.
[0055] The above only describes the preferred embodiments of the present application and is not intended to limit the present application. For those skilled in the art, the present application can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.
Claims
1. A multi-chip parallel packaging structure, characterized in that, include: Multiple chips are connected in parallel between adjacent chips via a metal layer, and a passivation layer is disposed on the metal layer.
2. The multi-chip parallel packaging structure according to claim 1, characterized in that: Two adjacent chips are connected in parallel through a first metal layer, and the opposite sides of the first metal layer are respectively connected to the top of a chip.
3. The multi-chip parallel packaging structure according to claim 2, characterized in that: The thickness of the first metal layer is 8mil-20mil.
4. The multi-chip parallel packaging structure according to claim 1, characterized in that: A first metal layer is disposed on the top of each of two adjacent chips, and a passivation layer is disposed between two adjacent first metal layers; A second metal layer is disposed on top of two adjacent first metal layers, and the two adjacent first metal layers are connected in parallel through the second metal layer.
5. The multi-chip parallel packaging structure according to claim 4, characterized in that: The thickness of the first metal layer is 6mil-12mil, and the thickness of the second metal layer is 7mil-150mil.
6. A smart power module, characterized in that: Including a multi-chip parallel packaging structure as described in any one of claims 1-5.
7. The intelligent power module according to claim 6, characterized in that: It also includes a frame, a PCB, and a substrate, wherein the PCB and the substrate are both disposed in the frame, and the multi-chip parallel packaging structure is disposed on the substrate.
8. The intelligent power module according to claim 7, characterized in that: The bottom of the substrate is provided with a heat dissipation structure, which includes multiple heat dissipation channels that extend from the substrate to the plastic encapsulation body of the smart power module.