Semiconductor laser chip

Abstract

The utility model relates to the technical field of semiconductor lasers, in particular to a semiconductor laser chip, which comprises a substrate, a growth buffer layer, a lower waveguide layer, an active layer, an upper waveguide layer, an upper cladding and a cover layer which are sequentially stacked from bottom to top in the longitudinal direction, a plurality of current injection regions with different widths and a plurality of ion injection regions with different widths are arranged in the transverse direction of the semiconductor laser chip; a plurality of current injection regions are distributed between the two ion injection regions on the two sides; the ion implantation region penetrates through the cover layer and a part of the upper cladding layer in the longitudinal direction; forming a ridge waveguide structure on the cover layer; processing the ridge waveguide structure through ion implantation to form a lateral chirp electric injection modulation ridge waveguide structure; the chirp electric injection structure formed by the utility model can regulate and control each order mode from the aspects of gain and loss, so that the loss of a high-order mode is greater than that of a fundamental mode, and finally, the effects of reducing the output of the high-order mode, reducing the divergence angle and improving the beam quality of a far field are achieved.

Description

TECHNICAL FIELD

[0001] The utility model belongs to the technical field of semiconductor laser, especially relates to a semiconductor laser chip. BACKGROUND

[0002] High power wide area semiconductor laser is the most important power type semiconductor laser at present, has major demand in each field, and all requires that laser is high power and has high beam quality simultaneously to obtain high brightness. High order side mode of semiconductor laser has greater light mode size and far field divergence angle, so the more the mode order of lasing is, the worse the beam quality is. Wide area semiconductor laser has many modes under lasing of large current, so far field width rapidly widens with the increase of current, finally leads to the deterioration of lateral beam quality.

[0003] There are several directions for traditional realization of high beam quality: external cavity, high order mode is filtered through external cavity feedback, so that lateral single mode (or few mode) lasing is realized to improve lateral beam quality, refractive index engineering, lateral refractive index modulation structure is adopted, mode resolution and mode selection are enhanced through refractive index engineering, output beam brightness is improved by controlling mode field characteristics, etc. Traditional mode is generally effective for lateral mode control, but also has respective limitations and problems, such as: external cavity needs larger system volume and more accurate optical path adjustment, system system is complex and cost rises. Refractive index engineering can realize near diffraction limit beam quality, narrow divergence (<1 °) laser emission at present, but must adopt higher precision and complex processing technology, the manufacturing cost is higher, and the output power of the device is lower at present. CONTENT OF THE UTILITY MODEL

[0004] Therefore, the utility model aims at providing a novel structure semiconductor laser chip which can improve the lateral beam quality of the semiconductor laser as much as possible without affecting the performance parameters such as efficiency and threshold value and has relatively simple process.

[0005] To achieve the above object, the technical scheme of the utility model is as follows:

[0006] A semiconductor laser chip, the semiconductor laser chip is a planar chip, the semiconductor laser chip comprises, from bottom to top in longitudinal direction, substrate, growth buffer layer, lower waveguide layer, active layer, upper waveguide layer, upper cladding layer and cover layer which are stacked in sequence.

[0007] The lateral direction of the semiconductor laser chip comprises several current injection regions with different widths distributed in the center and both sides and several ion implantation regions with different widths distributed in the center and both sides. The current injection regions are arranged between the ion implantation regions on both sides. The ion implantation regions penetrate the cover layer and part of the upper cladding layer in the longitudinal direction.

[0008] forming a ridge waveguide structure on the cap layer; and processing the ridge waveguide structure by ion implantation to form a lateral chirped current-injection modulated ridge waveguide structure.

[0009] Further, the width of the central ion implantation region is less than the width of the two side ion implantation regions; and the width of the central current injection region is greater than the width of the two side current injection regions.

[0010] Further, the zero point of the coordinate is the symmetry axis of the center of the semiconductor laser structure, and the several ion implantation regions with different widths are symmetrically arranged relative to the symmetry axis.

[0011] Further, two ion implantation regions with a width of 5 μm are located at a distance of 110 μm from the two sides of the symmetry axis; two ion implantation regions with a width of 10 μm are located at a distance of 195 μm from the two sides of the symmetry axis; two ion implantation regions with a width of 15 μm are located at a distance of 255 μm from the two sides of the symmetry axis; two ion implantation regions with a width of 20 μm are located at a distance of 345 μm from the two sides of the symmetry axis; and an ion implantation region with a width of 25 μm is located at a distance of 375 μm from the two sides.

[0012] Further, the thickness of the substrate ranges from 100 μm to 200 μm, the thickness of the buffer layer ranges from 0.5 μm to 1.5 μm, the thickness of the lower waveguide layer ranges from 0.5 μm to 1.5 μm, the thickness of the active layer ranges from 0.08 μm to 0.2 μm, the thickness of the upper waveguide layer ranges from 0.2 μm to 1 μm, the thickness of the upper cladding layer ranges from 0.5 μm to 2 μm, and the thickness of the cap layer ranges from 0.1 μm to 0.3 μm.

[0013] Further, the thickness of the buffer layer is 1 μm, the thickness of the lower waveguide layer is 870 nm, the thickness of the active layer is 8 nm, the thickness of the upper waveguide layer is 400 nm, the thickness of the upper cladding layer is 700 nm, and the thickness of the cap layer is 200 nm.

[0014] Further, the width of the ion implantation region ranges from 5 μm to 25 μm, and the width of the current injection region ranges from 10 μm to 200 μm.

[0015] Further, the cap layer comprises an electrically insulating layer, the electrically insulating layer comprises a P-face metal electrode, and the back of the substrate comprises an N-face metal electrode.

[0016] Further, the thickness of the electrically insulating layer ranges from 50 nm to 500 nm.

[0017] Further, the thickness of the electrically insulating layer is 500 nm.

[0018] Compared with the prior art, the utility model discloses can obtain following beneficial effect:

[0019] The semiconductor laser chip with the novel structure has the carrier modulation structure formed by ion implantation without etching, and the corresponding process step is reduced, and the process is simpler.

[0020] In addition, the semiconductor laser chip with the novel structure can control each order mode from the gain and loss aspects by the design of the chirp electric injection structure, the middle current injection area is wider than the two side current injection areas, the fundamental mode can obtain greater gain than the high order mode, the ion injection area of the two sides is greater than the ion injection area of the middle part, the loss of the high order mode can be greater than the fundamental mode, and finally the effect of reducing the high order mode output, reducing the divergence angle and improving the beam quality of the far field is achieved. BRIEF DESCRIPTION OF DRAWINGS

[0021] The accompanying drawings, which form a part of this application, are included to provide a further understanding of the application, and are incorporated herein for explanation by reference. In the drawings:

[0022] Figure 1 It is a laser semiconductor chip structure schematic view in the embodiment of the utility model;

[0023] Figure 2 It is a current injection area structure schematic view in the laser semiconductor chip in the embodiment of the utility model;

[0024] Figure 3 It is a preparation method flow chart of the laser semiconductor chip in the embodiment of the utility model;

[0025] Figure 4 It is a laser semiconductor chip structure schematic view in the comparative example of the utility model;

[0026] Figure 5 It is a divergence angle comparison schematic view of the embodiment and the comparative example of the utility model;

[0027] Figure 6 It is a laser power comparison schematic view of the embodiment and the comparative example of the utility model.

[0028] Explanation of the reference signs:

[0029] 1, ion implantation non-current injection region; 2, P face metal electrode, 3: silicon oxide electric insulating film; 4, cover layer; 5, P type cladding layer; 6, P type waveguide; 7, active layer; 8, N type waveguide; 9, buffer layer; 10, substrate; 11, N face metal electrode; 12, current injection region. DETAILED DESCRIPTION

[0030] In order to make the purpose, technical scheme and advantages of the utility model more clearly, the following will combine with the specific embodiment, and make the utility model further detailedly explained.It should be understood that the specific embodiment described here is only used to explain the utility model, and does not constitute the limitation to the utility model.

[0031] It should be noted that in the case of no conflict, the embodiments in the utility model and the features in the embodiments can be combined with each other.

[0032] In the description of the utility model, it should be understood that the orientation or position relationship indicated by the terms "center", "longitudinal", "lateral", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like is based on the orientation or position relationship shown in the drawings, and is only for the convenience of describing the utility model and simplifying the description, and therefore cannot be understood as indicating or implying that the device or element indicated must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the utility model.In addition, the terms "first", "second" and the like are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated.The features limited by "first", "second" and the like can explicitly or implicitly include one or more features.In the description of the utility model, unless otherwise specified, the meaning of "a plurality of" is two or more.

[0033] In the description of the utility model, it should be noted that, unless otherwise specified and limited, the terms "mounting", "connection", "connection" should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected, it can be mechanically connected, or it can be electrically connected, it can be directly connected, or indirectly connected through an intermediate medium, it can be the communication inside two elements.The above-mentioned terms in the utility model can be understood by the specific meaning of the person skilled in the art according to the specific circumstances.

[0034] The utility model discloses a semiconductor laser chip, the semiconductor laser chip is planar chip, the semiconductor laser chip includes substrate, growth buffer layer, lower waveguide layer, active layer, upper waveguide layer, upper cladding layer, cover layer that stack in proper order from below to top in longitudinal direction, the lateral direction of semiconductor laser chip includes several current injection area of different width that distribute in center and both sides, several ion implantation area of different width that distribute in center and both sides, several current injection area are arranged and set up between the ion implantation area of two both sides, the ion implantation area is in longitudinal direction, and penetrates cover layer and part upper cladding layer, forms ridge waveguide structure on the cover layer, handles ridge waveguide structure through ion implantation, forms lateral chirp electric injection modulation ridge waveguide structure, and the lateral here refers to the lateral strip width direction of semiconductor laser, that is, light emitting direction, specifically, the energy of ion implantation is 50KeV~500KeV, and the injection dose of ion implantation is 2e12cm -2 ~ 5e15cm -2 , and the ion of ion implantation is one of hydrogen ion, helium ion, nitrogen ion or argon ion, can control the concentration and depth of injection ion accurately through the energy and beam current density of ion implantation, can reduce the problem that ion implantation can cause damage to each layer, specifically, ion implantation concentration can be selected according to the doping concentration of semiconductor material, for example, when the doping concentration of semiconductor material is greater than 1e18cm -3 , then the dose of ion implantation is preferably greater than 1e15 cm -2 ; The ion implantation depth of the utility model is controlled above upper waveguide layer, that is, the ion implantation area is in longitudinal direction, only penetrates cover layer and part upper cladding layer, and does not penetrate to upper waveguide layer any more, avoids producing internal loss.

[0035] In the specific embodiment, the width of the ion injection area in the center is smaller than the width of the ion injection areas on the two sides; the width of the current injection area in the center is larger than the width of the current injection areas on the two sides; the width of the ion injection area and the current injection area can be determined according to the mode distribution in the specific semiconductor laser, in the scheme provided in the specific embodiment of the utility model, the ion injection area in the center is set to be narrower and the ion injection areas on the two sides are set to be wider, so that the current injection area is still in the center of the fundamental mode and the ion injection is on the two sides of the fundamental mode, thereby reducing the influence on the gain of the fundamental mode; meanwhile, the ion injection areas on the two sides are located at the peak values of the high-order modes and the width is widened as much as possible to cover the high-order modes, thereby reducing the gain of the high-order modes, finally realizing the normal output of the fundamental mode and reducing the output of the high-order modes, so as to reduce the divergence angle. Therefore, the semiconductor laser chip with the novel structure provided in the utility model can regulate each mode from the gain and loss by designing the chirp current injection structure, the current injection area in the middle is set to be wider than the current injection areas on the two sides, the fundamental mode can obtain larger gain than the high-order modes, the ion injection areas on the two sides are set to be larger than the ion injection area in the middle, so that the loss of the high-order modes is larger than that of the fundamental mode, finally the effect of reducing the output of the high-order modes, reducing the divergence angle and improving the beam quality of the far field is achieved.

[0036] In the specific embodiment, the thickness of the substrate ranges from 100 μm to 200 μm, the thickness of the buffer layer ranges from 0.5 μm to 1.5 μm, the thickness of the lower waveguide layer ranges from 0.5 μm to 1.5 μm, the thickness of the active layer ranges from 0.08 μm to 0.2 μm, the thickness of the upper waveguide layer ranges from 0.2 μm to 1 μm, the thickness of the upper cladding layer ranges from 0.5 μm to 2 μm, and the thickness of the cover layer ranges from 0.1 μm to 0.3 μm; preferably, the thickness of the buffer layer is 1 μm, the thickness of the lower waveguide layer is 870 nm, the thickness of the active layer is 8 nm, the thickness of the upper waveguide layer is 400 nm, the thickness of the upper cladding layer is 700 nm, and the thickness of the cover layer is 200 nm; specifically, different mode distribution positions correspond to different ridge widths, and the ion injection area and the current injection area need to be changed accordingly; in the case of a 740 um strip width, the width of the ion injection area ranges from 5 μm to 25 μm; and the width of the current injection area ranges from 10 μm to 200 μm.

[0037] In a specific embodiment, the substrate is made of InP or GaAs; the buffer layer is made of one of AlGaAs, InGaAs, or InP; the upper waveguide layer is made of one of AlGaAs, AlInAs, or InGaAsP; the upper cladding layer is made of one of AlGaAs, InGaAs, or InP; the lower waveguide layer is made of one of AlGaAs, GaAsSb, or InP; and the capping layer is made of InP or GaAs.

[0038] The semiconductor laser chip structure provided by this utility model is applicable to various semiconductor laser epitaxy. In other specific embodiments, when the epitaxy type is different, the materials and thicknesses selected for each layer in the semiconductor laser chip, such as the substrate, growth buffer layer, lower waveguide layer, active layer, upper waveguide layer, upper cladding layer, and capping layer, are also different.

[0039] The semiconductor laser chip provided by this utility model includes an electrically insulating layer on the cap layer, and a P-side metal electrode on the electrically insulating layer. The back side of the substrate includes an N-side metal electrode. The electrically insulating layer is a silicon oxide electrically insulating film or a silicon nitride electrically insulating film. The thickness of the electrically insulating layer ranges from 50 nm to 500 nm. The thickness of the electrically insulating layer is 500 nm.

[0040] The novel semiconductor laser chip proposed in this invention, compared to the carrier modulation structure formed by etching in traditional chips, eliminates the need for etching during ion implantation, thus reducing the number of process steps and simplifying the process. Furthermore, since ion implantation does not involve etching, it does not alter the surface morphology, resulting in a higher heat dissipation capacity for the ion-implanted carrier modulation structure compared to the etched structure. This higher heat dissipation capacity reduces the refractive index change caused by heat, lowers the thermal lensing effect, and consequently improves the beam quality in the far field.

[0041] The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0042] Example

[0043] This embodiment provides a semiconductor laser chip with the following structure: Figure 1 As shown, from top to bottom, it includes a 300nm thick P-side metal electrode 2, a 500nm thick SiO2 electrically insulating layer 3, a 200nm thick GaAs capping layer 4, a 700nm thick P-type GaAs upper cladding layer 5, a 400nm thick P-type AlGaAs upper waveguide layer 6, an 8nm thick undoped InGaAs active region 7, an 870nm thick N-type AlGaAs lower waveguide layer 8, a 1μm growth buffer layer 9, and a GaAs substrate 10.

[0044] The method for fabricating a semiconductor laser chip provided in this example is as follows:Figure 3 As shown: first, epitaxially grow buffer layer 9, lower waveguide layer 8, active layer 7, upper waveguide layer 6, upper cladding layer 5, and cover layer 4 on substrate 10 in sequence; then, uniformly glue lithography on cover layer 4, vertically etch away cover layer 4 and part of upper cladding layer 5 to form a ridge waveguide structure, the deep trench position shown by the black box in the figure is the ridge waveguide trench formed by etching before ion implantation, which is used to standardize the width of the ridge waveguide structure; then, uniformly glue lithography on the ridge waveguide structure to form a pattern for ion implantation, the ion implantation energy is 90KeV, the ion species is helium ion, the implantation depth is 800nm, and the ion implantation region 1 is formed, taking the center symmetry axis of the laser structure as the coordinate zero point, the ion implantation region is symmetrically arranged relative to the symmetry axis: the ion implantation region with a width of 5μm is located at ±110μm on both sides of the symmetry axis; the ion implantation region with a width of 10μm is located at ±195μm on both sides of the symmetry axis; the ion implantation region with a width of 15μm is located at ±255μm on both sides of the symmetry axis; the ion implantation region with a width of 20μm is located at ±345μm on both sides of the symmetry axis; the ion implantation region with a width of 25μm is located at ±375μm on both sides of the symmetry axis, and the ion implantation region 1 penetrates the cover layer 4 to part of the P-type upper cladding layer 5; then, grow an upper electrical insulation layer 3 on the cover layer 4, uniformly glue lithography, and etch away the upper electrical insulation layer on the ridge waveguide structure to form a window; finally, grow a P-face metal electrode 2, thin the substrate 10, and then grow an N-face metal electrode 11 on the back, specifically, in the semiconductor laser chip provided by the present example, the structure of the current injection region is as shown in Figure 2 .

[0045] Comparative Example

[0046] First, epitaxially grow buffer layer 9, lower waveguide layer, i.e., N-type waveguide 8, active layer 7, upper waveguide layer, i.e., P-type waveguide 6, upper cladding layer 5, and cover layer 4 on substrate 10 in sequence; then, uniformly glue lithography on cover layer 3, vertically etch away the cover layer and part of the cladding layer to form a ridge waveguide structure; then, grow an upper electrical insulation layer, i.e., a silicon oxide electrical insulation film 3, on the cover layer 4, uniformly glue lithography, and etch away the upper electrical insulation layer on the ridge waveguide structure to form a window; finally, grow a P-face metal electrode 2, thin the substrate 10, and then grow an N-face metal electrode 11 on the back, specifically, the structure of the semiconductor laser chip in the comparative example provided by the present example is as shown in Figure 4 .

[0047] As Figure 5 and Figure 6As shown, respectively, are a divergence angle comparison schematic diagram and a laser power comparison schematic diagram of the embodiment and the comparative example of the utility model, from the diagram, it can be seen that the semiconductor laser chip prepared by adopting the preparation method of the utility model, the divergence angle is reduced from originally containing 95% light power 13.58 ° to 10.71 °, is reduced 21 %;And the efficiency power is reduced from 34.9 W to 33.4 W, is reduced only 4%;Fully demonstrate that while the divergence angle is reduced, the laser power efficiency does not have big drop.

[0048] It should be understood that the steps can be reordered, added, or deleted using the various forms of flow shown above. For example, the steps described in the utility model disclosure can be executed in parallel, sequentially, or in a different order, as long as the desired results of the technical solutions of the utility model disclosure can be achieved, which is not limited herein.

[0049] The above specific embodiments do not constitute a limitation on the scope of protection of the utility model. Those skilled in the art should understand that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement within the spirit and principles of the utility model should be included in the scope of protection of the utility model.

Claims

1. A semiconductor laser chip, characterized in that: The semiconductor laser chip is a planar chip, and the semiconductor laser chip includes, from bottom to top in the longitudinal direction, a substrate, a growth buffer layer, a lower waveguide layer, an active layer, an upper waveguide layer, an upper cladding layer, and a capping layer stacked sequentially. The semiconductor laser chip includes, in the lateral direction, several current injection regions of different widths distributed at the center and on both sides, and several ion injection regions of different widths distributed at the center and on both sides; several current injection regions are distributed between the two ion injection regions on both sides; in the longitudinal direction, the ion injection regions penetrate the capping layer and part of the upper cladding layer. A ridge waveguide structure is formed on the capping layer; the ridge waveguide structure is then processed by ion implantation to form a laterally chirped electro-injection modulated ridge waveguide structure.

2. The semiconductor laser chip according to claim 1, characterized in that: The width of the central ion implantation region is smaller than the width of the ion implantation regions on both sides; the width of the central current implantation region is larger than the width of the current implantation regions on both sides.

3. The semiconductor laser chip according to claim 1, characterized in that: With the axis of symmetry at the center of the semiconductor laser structure as the zero point of the coordinate system, several ion implantation regions of different widths are arranged symmetrically relative to the axis of symmetry.

4. The semiconductor laser chip according to claim 3, characterized in that: Two ion implantation regions with a width of 5 μm are located at a distance of 110 μm from both sides of the axis of symmetry; two ion implantation regions with a width of 10 μm are located at a distance of 195 μm from both sides of the axis of symmetry; two ion implantation regions with a width of 15 μm are located at a distance of 255 μm from both sides of the axis of symmetry; two ion implantation regions with a width of 20 μm are located at a distance of 345 μm from both sides of the axis of symmetry; and an ion implantation region with a width of 25 μm is located at a distance of 375 μm from both sides.

5. The semiconductor laser chip according to claim 1, characterized in that: The thickness of the substrate ranges from 100 μm to 200 μm, the thickness of the buffer layer ranges from 0.5 μm to 1.5 μm, the thickness of the lower waveguide layer ranges from 0.5 μm to 1.5 μm, the thickness of the active layer ranges from 0.08 μm to 0.2 μm, the thickness of the upper waveguide layer ranges from 0.2 μm to 1 μm, the thickness of the upper cladding layer ranges from 0.5 μm to 2 μm, and the thickness of the capping layer ranges from 0.1 μm to 0.3 μm.

6. The semiconductor laser chip according to claim 1, characterized in that: The thickness of the buffer layer is 1 μm, the thickness of the lower waveguide layer is 870 nm, the thickness of the active layer is 8 nm, the thickness of the upper waveguide layer is 400 nm, the thickness of the upper cladding layer is 700 nm, and the thickness of the capping layer is 200 nm.

7. The semiconductor laser chip according to claim 1, characterized in that: The width of the ion implantation region ranges from 5 μm to 25 μm; the width of the current implantation region ranges from 10 μm to 200 μm.

8. The semiconductor laser chip according to claim 1, characterized in that: The capping layer includes an electrically insulating layer, and the electrically insulating layer includes a P-side metal electrode. The back side of the substrate includes an N-side metal electrode.

9. The semiconductor laser chip according to claim 8, characterized in that: The thickness of the electrical insulating layer ranges from 50 nm to 500 nm.

10. The semiconductor laser chip according to claim 8, characterized in that: The thickness of the electrical insulating layer is 500 nm.

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