Grid driving negative voltage generation circuit
By connecting a capacitor and a Zener diode in series in the gate drive circuit, and combining them with a PNP transistor, a simple peripheral circuit is constructed, which solves the problems of large size and complex peripheral circuits in the negative voltage turn-off scheme. This achieves low-cost and high-efficiency negative voltage turn-off, which is suitable for high-power power conversion and motor drive.
Patent Information
- Application Number
- CN202422833430.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-20
- Publication Date
- 2025-12-02
- Estimated Expiration
- 2034-11-20
AI Technical Summary
In the existing technology, the negative voltage shutdown scheme used for high-power power conversion and motor drive has the problems of large chip size, complex peripheral circuits, unsuitability for space-constrained occasions, and poor economy.
By connecting a capacitor in series between the gate drive circuit and the power device, and combining a Zener diode and a PNP transistor, a simple peripheral circuit is constructed to generate negative voltage. This is suitable for conventional gate drive chips without negative voltage drive, and uses AC drive to generate negative voltage and clamp it.
It achieves negative voltage turn-off with simple structure and low cost in space-constrained environments, with good economic efficiency and practicality, and is suitable for power devices such as silicon MOS and IGBT.
Smart Images
Figure CN223625752U_ABST
Abstract
Description
Technical Field
[0001] This utility model belongs to the field of electronic circuits, and in particular relates to a gate drive negative voltage generation circuit. Background Technology
[0002] In high-power power conversion circuits and motor driver circuits, silicon carbide MOS or IGBTs are often used as power devices. When it is necessary to turn off the silicon carbide MOS or IGBT, it is generally necessary to use negative voltage drive to turn off, that is, to apply a reverse voltage between the gate and source of the power device to completely turn off the power device. At the same time, it can also effectively prevent the voltage between the drain and source of the power device from being too high, and the dv / dt generated during turn-off from being too large, which could lead to the power device being falsely turned on.
[0003] Currently, there are dedicated gate driver chips for negative voltage shutdown on the market, but they are usually large in size, have many pins, and require some external components to achieve the negative voltage shutdown function, making them inconvenient to use in applications with limited space.
[0004] There are also drive methods that use transformer isolation, which employ AC drive and use a portion of the drive voltage to bootstrap into a negative voltage through a capacitor. However, the transformer itself is relatively large, and transformer-isolated drives cannot support a continuous DC state for extended periods. Therefore, they are not suitable for special applications such as servo motor drives.
[0005] Meanwhile, for conventional gate driver chips that do not have negative voltage drive shutdown, a common option is to achieve negative voltage drive through external circuitry. However, the external circuitry of this solution is relatively complex. In order to obtain a continuous and stable negative voltage, multiple compensation measures are usually required, which leads to a decrease in economic efficiency, an increase in size, and affects practicality. Summary of the Invention
[0006] The present invention aims to solve the above problems by providing a gate drive negative voltage generation circuit that achieves negative voltage shutdown of the gate drive through simple peripheral circuit processing and using a conventional gate drive chip without negative voltage drive shutdown.
[0007] The gate drive negative voltage generation circuit of this utility model includes a gate drive circuit and a power device; a capacitor Cb is connected in series between the gate of the gate drive circuit and the gate of the power device.
[0008] A Zener diode D1 is connected in parallel across the capacitor Cb for voltage clamping, ensuring that the voltage across the negative capacitor Cb is stable near the rated Zener voltage Vz1 of D1; the negative terminal of the Zener diode D1 is connected to the gate drive circuit terminal, and the positive terminal is connected to the gate terminal of the power device.
[0009] A bidirectional voltage regulator diode D2 is connected in parallel between the gate and source of the power device to protect the gate and clamp the gate voltage.
[0010] A resistor R1 is connected in parallel between the gate and source of the power device to provide gate electrostatic discharge protection, discharge excess charge on the gate when power is off, and provide bootstrap current for capacitor Cb.
[0011] Furthermore, in the gate drive negative voltage generation circuit of this invention, a gate resistor Rg is connected in series between the capacitor Cb and the gate drive circuit to reduce the turn-on speed.
[0012] Furthermore, in the gate drive negative voltage generation circuit of this utility model, the PNP transistor in the gate drive circuit is used for turn-off acceleration processing. The emitter of the PNP transistor is connected to the node of the negative voltage capacitor Cb and the gate resistor Rg; the base of the PNP transistor is connected to the connection node of the gate resistor Rg and the gate drive circuit; the collector of the PNP transistor is connected to the source of the power device to be driven. The gate negative voltage generation circuit thus constitutes a circuit that can flexibly control the turn-on time of the gate of the power device and use the PNP transistor to accelerate the drive to a negative gate voltage when the power device is turned off.
[0013] The gate drive negative voltage generation circuit of this utility model uses an AC drive method, that is, it generates negative voltage by adding a capacitor in the gate drive circuit and uses a Zener diode for negative voltage clamping. Thus, it can achieve negative voltage drive shutdown of power devices by simply expanding on a common gate drive bridge chip. It has the advantages of simple structure and low cost, and has good economy and practicality, especially in space-constrained environments. Attached Figure Description
[0014] Figure 1 This is a schematic diagram of the gate drive negative voltage generation circuit described in an embodiment of the present invention;
[0015] Figure 2 This is a schematic diagram illustrating the application of the gate drive negative voltage generation circuit described in an embodiment of this utility model. Detailed Implementation
[0016] The gate drive negative voltage generation circuit of this utility model will be described in detail below with reference to the accompanying drawings and embodiments.
[0017] like Figure 1As shown, this embodiment discloses a gate drive negative voltage generation circuit, including a gate drive circuit and a power device; a capacitor Cb is connected in series between the gate drive circuit and the gate of the power device; a Zener diode D1 is connected in parallel across the two ends of the capacitor Cb for voltage clamping, ensuring that the voltage across the negative voltage capacitor Cb is stable near the rated regulated voltage Vz1 of D1; the negative terminal of the Zener diode D1 is connected to the gate drive circuit terminal, and the positive terminal is connected to the gate terminal of the power device; a bidirectional Zener diode D2 is connected in parallel between the gate and source of the power device for protecting the gate and clamping the gate voltage; a resistor R1 is connected in parallel between the gate and source of the power device for gate electrostatic discharge protection, and can discharge excess charge on the gate when power is off, while providing bootstrap current for the capacitor Cb.
[0018] In this embodiment, the stable negative voltage established on the negative voltage capacitor Cb is approximately equal to the rated voltage Vz1 of the clamping diode D1. The sum of the rated voltage Vz2 of the selected bidirectional Zener diode D1 and Vz1 is less than the maximum driving voltage VDvr of the driving PWM. When the voltage on the driving negative voltage capacitor Cb is lower than the rated voltage Vz1 of the clamping diode D1 minus the forward voltage drop of the diode above D2, the bidirectional Zener diode D2 freewheels in the forward direction, thereby accelerating the establishment of the bootstrap voltage on the negative voltage capacitor.
[0019] In this embodiment, a gate resistor Rg is connected in series between the capacitor Cb and the gate driving circuit to reduce the turn-on speed. The PNP transistor in the gate driving circuit is used for turn-off acceleration. The emitter of the PNP transistor is connected to the node of the negative voltage capacitor Cb and the gate resistor Rg; the base of the PNP transistor is connected to the node of the gate resistor Rg and the gate driving circuit; and the collector of the PNP transistor is connected to the source of the power device to be driven. This gate negative voltage generation circuit can flexibly control the turn-on time of the power device's gate and accelerate the power device's turn-off to a negative gate voltage using the PNP transistor.
[0020] By connecting a negative voltage capacitor Cb in series between the signal terminal of a conventional gate drive circuit and the gate of the power device, the driven PWM can be made to drive the gate of the power device in a certain AC form, thus obtaining a negative gate voltage. Assuming the driving PWM voltage is VDvr and the gate capacitance of the power device is Cg, then when the PWM is high, the voltages across Cb and Cg are respectively:
[0021]
[0022] When the PWM is low, the capacitors on Cg and Cb start to discharge simultaneously, and eventually the voltage drops to zero at the same time. Therefore, Cb alone cannot generate a negative voltage and be used for gate driving.
[0023] Meanwhile, a resistor R1 is connected in parallel between the gate and source of the power device to form a separate freewheeling circuit for Cb. The charge on Cb is greater than the charge on Cg, so when the PWM is low, the discharge speed of Cb is slower than that of Cg. Consequently, a negative voltage is established on Cg during the low-level period of the PWM. However, the negative voltage generated by this simple structure is related to the period and duty cycle of the PWM, and is extremely unstable and affected by a variety of factors.
[0024] A Zener diode D1 is connected in parallel across the negative voltage capacitor Cb. The negative terminal of the Zener diode is connected to the gate drive circuit terminal, and the positive terminal is connected to the gate of the power device. The rated Zener voltage of D1 is Vz1. The voltage across Cb will be clamped to near Vz1. Even if the PWM turn-on period is infinitely long, the freewheeling current of R1 can be shunted through D1, thus ensuring that the voltage on Cb will not increase indefinitely.
[0025] When the PWM duty cycle is small, the freewheeling current of R1 is insufficient to establish a sufficient voltage across Cb, resulting in a negative voltage across Cb that is lower than Vz1. A bidirectional Zener diode D2 (two Zener diodes connected back-to-back in series) is connected in parallel between the gate and source of the power device. The rated Zener voltage of D2 is Vz2. We choose Vz1 + Vz2 = VDvr. When the voltage across Cb is lower than Vz1 - 0.7V, that is, when VDvr minus the voltage across Cb is greater than the sum of the rated Zener voltage of the bidirectional Zener diode Vz2 and the forward conduction voltage of a diode, D2 starts to conduct freewheeling current, thus ensuring that the voltage across Cb is not lower than Vz1 - 0.7V.
[0026] The power device QA can be a silicon MOS, silicon carbide MOS, or IGBT, and they are driven in the same way. When using an IGBT power device, its emitter corresponds to the source of QA, and its collector corresponds to the drain of QA. The main difference between silicon MOS, silicon carbide MOS, and IGBT power devices lies in the drive voltage and the required turn-off negative voltage. Silicon MOS typically uses a 7.5~12V forward drive voltage, and the required turn-off negative voltage can be 3~8V. Therefore, VDvr is selected as 10.5~20V, Vz1 as 3~8V, and Vz2 is VDvr-Vz1. Silicon carbide and IGBTs typically require a forward drive voltage of 18V or higher. Silicon carbide can have a turn-off negative voltage as low as 3V, but IGBTs require a turn-off negative voltage between 10~20V. The selection methods for VDvr, Vz1, and Vz2 are the same as for silicon MOS. It should be noted that D1 and D2... Since they are connected in series, when VDvr is higher than Vz1 + Vz2 + 0.7, a large current will flow through D1 and D2. Therefore, the negative voltage generation circuit provided in this embodiment requires a stable VDvr. An unstable and excessively high VDvr will increase power consumption and may even damage D2. In practical applications, a resistor of several hundred ohms can be connected in series with D2 to limit the current and prevent the current from increasing rapidly due to excessively high VDvr. However, this will affect the stability of the negative voltage. R1 is used for gate electrostatic discharge protection and can discharge excess charge on the gate when the power is off. At the same time, it provides a certain bootstrap current for Cb. Usually, 30kΩ to 100kΩ can be selected. A smaller resistance value can provide better freewheeling capability, but it increases power consumption. When the resistance value is too large, the electrostatic discharge protection effect and freewheeling effect will decrease. Therefore, it is necessary to select the appropriate value in practical applications.
[0027] In this embodiment, as Figure 2 As shown, the FD2606S half-bridge driver chip from Peakray Technology is used. Therefore, the driven power devices are divided into upper and lower arms. The drive circuit structures for the upper and lower arms are the same, except that the upper arm uses a swing circuit, with the swinging upper arm drive voltage generated by a bootstrap circuit. The lower arm directly uses VDvr as the drive voltage. D3, U2, C1, and C2 constitute the basic peripheral components of the FD driver bridge chip. Without a negative voltage generation circuit, the HO and LO outputs of U2 can be used to drive the power devices.
[0028] The negative voltage generation circuit of the upper arm power device consists of RgH, CbH, D1H, D2H, Q1H, and G1H, while the negative voltage generation circuit of the lower arm power device consists of RgL, CbL, D1L, D2L, Q1L, and G1L. The parameters of the negative voltage generation circuits of the upper and lower arm power devices are the same. The lower arm drive circuit is directly connected to the GND ground line, while the upper arm drive circuit is connected to the middle node of the H bridge. GH and GL are the gate nodes of the upper and lower arm power devices, respectively.
[0029] VDvr uses a 15V drive voltage, Vz1 is selected as 3V, Vz2 is selected as 12V, Rg is 10 ohms, Cb is 2.2uF, Q1 uses a PNP small power transistor SS8550W, R1 is selected as 100k, PWMH and PWML are the drive PWM signals for the upper and lower arms, respectively.
[0030] Figure 2 The circuit shown has a drive-on rising edge of approximately 400ns and a drive-off falling edge as low as 40ns when driving a 10nF load, and has a negative voltage of 3V.
[0031] The MOS transistor used in this embodiment is an NMOS transistor. The gate drive negative voltage generation circuit disclosed in this embodiment is also applicable to PMOS transistors. Those skilled in the art do not need to do any additional creative work. In specific applications, they only need to replace Q1 with an NPN transistor and change the direction of the Zener diode D1 to make applicability adjustments to achieve the technical effect described in this embodiment.
[0032] The gate drive negative voltage generation circuit disclosed in this embodiment achieves negative voltage shutdown of the gate drive through simple peripheral circuit processing and using a conventional gate drive chip without negative voltage drive shutdown. It has the characteristics of simple structure and small size, and has broad application prospects.
Claims
1. A gate drive negative voltage generation circuit, comprising a gate drive circuit and power devices; characterized in that: A capacitor Cb is connected in series between the gate drive circuit and the gate of the power device. A Zener diode D1 is connected in parallel across the two ends of the capacitor Cb; the negative terminal of the Zener diode D1 is connected to the gate drive circuit terminal, and the positive terminal is connected to the gate terminal of the power device. A bidirectional voltage regulator diode D2 is connected in parallel between the gate and source of the power device; A resistor R1 is connected in parallel between the gate and source of the power device.
2. The gate drive negative voltage generation circuit according to claim 1, characterized in that: A gate resistor Rg is connected in series between the capacitor Cb and the gate drive circuit.
3. The gate drive negative voltage generation circuit according to claim 2, characterized in that: The emitter of the PNP transistor in the gate drive circuit is connected to the node of the negative voltage capacitor Cb and the gate resistor Rg; the base of the PNP transistor is connected to the node of the gate resistor Rg and the gate drive circuit; and the collector of the PNP transistor is connected to the source of the power device to be driven.