SiP-based four-channel peak signal acquisition circuit

Abstract

The utility model relates to a SiP-based four-channel peak signal acquisition circuit, the circuit comprises a four-channel peak holding module and a signal acquisition module, the input of the four-channel peak holding module is an analog pulse signal, and after peak holding processing, a held analog signal is output; and inputting the maintained analog signal into a signal acquisition module, and outputting a corresponding serial digital signal after analog-to-digital conversion. The circuit can carry out peak holding operation on pulse signals of four channels, and the holding time is adjustable.

Description

Technical Field

[0001] This invention belongs to the field of signal acquisition technology, and in particular relates to a four-channel peak signal acquisition circuit based on SiP. Background Technology

[0002] Peak hold and acquisition circuits are widely used in multi-quadrant detector signal acquisition systems. Depending on the number of signal channels acquired, there are single-channel, dual-channel, and four-channel acquisition systems. In practice, these systems require peak hold operations on the signal, followed by analog-to-digital conversion and digital processing. The components typically used include operational amplifiers, diodes, A / D converters, and digital processing devices such as microcontrollers, field-programmable gate arrays (FPGAs), or digital signal processors (DSPs). These systems generally use low-voltage power supplies, such as 3.3V or 5V, and place certain requirements on the bandwidth of the operational amplifiers, the speed of the A / D converters, and the digital processors.

[0003] In existing technologies, this system is typically implemented by using separate operational amplifiers and diodes, microcontroller units (MCUs), or other components to build circuits, depending on the number of channels, to provide a fixed output signal hold time. The components used in the system may also require different supply voltages, necessitating multiple external power supplies. This approach has several drawbacks: the number of channels is designed based on actual needs, lacking versatility, and one solution is only suitable for one application; the front-end peak hold and the back-end analog-to-digital conversion and digital processing use multiple cascaded components, making debugging difficult and cumbersome; different components use multiple power supply modules, occupying significant space in the system and causing considerable noise, reducing acquisition accuracy. Therefore, how to make the system versatile, simplify design in applications, and improve accuracy is a major challenge facing existing designs. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a novel four-channel peak signal acquisition circuit to solve the problems of difficult debugging and limited number of channels in the prior art.

[0005] This invention provides a four-channel peak signal acquisition circuit based on SiP, comprising: a four-channel peak hold module and a signal acquisition module. The input of the four-channel peak hold module is an analog pulse signal, which is processed by peak hold and outputs a held analog signal. The held analog signal is input to the signal acquisition module, which is converted from analog to digital and outputs a corresponding serial digital signal.

[0006] Furthermore, the four-channel peak hold module includes four channels with identical circuit structures. Each channel includes a dual operational amplifier chip, a diode chip, a first resistor, a second resistor, and a capacitor. The dual operational amplifier chip includes two operational amplifiers connected in a cascaded manner, with its positive power supply pin connected to a positive power supply and its negative power supply pin grounded. The first positive input pin of the dual operational amplifier chip receives the analog pulse signal from the first channel and is grounded through the first resistor. The second negative input pin of the dual operational amplifier chip is connected to the first output pin of the dual operational amplifier chip and serves as the output pin of that channel. The first output pin of the dual operational amplifier chip is connected to the anode of the diode, and the cathode of the diode is connected to the second positive input pin of the dual operational amplifier chip and connected to a common terminal of the capacitor and the second resistor. The other common terminal of the capacitor and the second resistor is grounded.

[0007] The beneficial effects of the present invention are as follows: The four-channel peak hold module of the present invention can simultaneously receive four channels of peak signals, perform peak voltage hold operation on them, and output four channels of hold voltage. At the same time, the hold time of the output voltage can be adjusted through the control port. The signal acquisition module can perform analog-to-digital conversion on the hold voltage through digital signal control, and can simultaneously output four digital signals. It can also perform calculation operations on the digital signals as needed, which can greatly simplify the upper computer calculation. Attached Figure Description

[0008] Figure 1 This is a schematic diagram of the SiP-based four-channel peak signal acquisition circuit according to an embodiment of the present invention;

[0009] Figure 2 for Figure 1 Circuit diagram of the first unit in the four-channel peak hold module;

[0010] Figure 3 for Figure 1 Circuit diagram of the second unit in the four-channel peak hold module;

[0011] Figure 4 for Figure 1 Circuit diagram of the third unit in the four-channel peak hold module;

[0012] Figure 5 for Figure 1 Circuit diagram of the fourth unit in the four-channel peak hold module;

[0013] Figure 6 for Figure 1 Circuit diagram of the signal acquisition module;

[0014] Explanation of reference numerals in the attached figures:

[0015] VCC: Internal op-amp power supply; GND: Ground;

[0016] MCU (Microcontroller Unit): A microcontroller unit or single-chip microcomputer;

[0017] URAT interface (Universal Asynchronous Receiver / Transmitter interface): A universal asynchronous receiver and transmitter interface;

[0018] I2C interface: A two-wire serial bus interface used to connect the MCU and other peripherals;

[0019] IN1: First channel analog input; IN2: Second channel analog input;

[0020] IN3: Third channel analog input; IN4: Fourth channel analog input;

[0021] SET1: Keep settings for the first channel; SET2: Keep settings for the second channel;

[0022] SET3: Hold settings for the third channel; SET4: Hold settings for the fourth channel;

[0023] OUT1: First channel holds output; OUT2: Second channel holds output;

[0024] OUT3: Third channel holds output; OUT4: Fourth channel holds output;

[0025] OP1-A: One of the amplifiers in the first dual-channel operational amplifier chip;

[0026] OP1-B: The other amplifier in the first dual-channel operational amplifier chip;

[0027] R1: First resistor; D1: First diode; C1: First capacitor; R2: Second resistor;

[0028] OP2-A: One of the amplifiers in the second dual-channel operational amplifier chip;

[0029] OP2-B: The other amplifier in the second dual-channel operational amplifier chip;

[0030] R3: Third resistor; D2: Second diode; C2: Second capacitor; R4: Fourth resistor;

[0031] OP3-A: One of the amplifiers in the third dual-channel operational amplifier chip;

[0032] OP3-B: Another amplifier in the third dual-channel operational amplifier chip;

[0033] R5: Fifth resistor; D3: Third diode; C3: Third capacitor; R6: Sixth resistor;

[0034] OP4-A: One of the amplifiers in the second dual-channel operational amplifier chip;

[0035] OP4-B: The other amplifier in the second dual-channel operational amplifier chip;

[0036] R7: Seventh resistor; D4: Fourth diode; C4: Fourth capacitor; R8: Eighth resistor;

[0037] IC1: First dual-channel operational amplifier chip; IC2: Second dual-channel operational amplifier chip;

[0038] IC3: Third dual-channel operational amplifier chip; IC4: Fourth dual-channel operational amplifier chip;

[0039] IC5: Microcontroller chip. Detailed Implementation

[0040] The terms "first," "second," "third," "fourth," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such terms can be used interchangeably where appropriate; this is merely a way of distinguishing objects with the same attributes in the embodiments of this application.

[0041] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0042] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show components related to the present invention and are not drawn according to the actual number, shape, and size of the components in implementation. In actual implementation, the form, quantity, and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex. The structures, proportions, sizes, etc., shown in the accompanying drawings are only used to complement the content disclosed in the specification for those skilled in the art to understand and read, and are not intended to limit the conditions under which the present invention can be implemented. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportional relationships, or adjustments to the size, without affecting the effects and objectives that the present invention can produce, should still fall within the scope of the technical content disclosed in the present invention.

[0043] Terminology Explanation:

[0044] SiP: System in a Package.

[0045] BT organic substrate, also known as BT resin substrate material, is a high-performance substrate made from BT resin as the base material, and is widely used in the PCB (printed circuit board) field.

[0046] UART: Universal Asynchronous Receiver / Transmitter, is a commonly used serial communication interface.

[0047] I2C (Inter-Integrated Circuit, IIC) is an integrated circuit bus and a serial communication bus.

[0048] As mentioned in the background section: the number of channels is designed according to actual needs and lacks universality; one solution is only for one application; the peak holding at the front end and the analog-to-digital conversion and digital processing at the back end use multiple cascaded devices, making debugging difficult and cumbersome; different devices use multiple power supply modules, occupying a lot of space in the system and causing significant noise, reducing acquisition accuracy. Based on this, the present invention proposes a newly designed four-channel peak signal acquisition circuit and its packaging structure.

[0049] Figure 1 This is a schematic diagram of the SiP-based four-channel peak signal acquisition circuit according to an embodiment of the present invention. Figure 1In the diagram, IN1~IN4 represent the analog pulse signals received by the four-channel peak hold module; SET1~SET4 represent the selectable signals of the four-channel peak hold module, used to control the hold time of the output signal; OUT1~OUT4 represent the analog signals output by the four-channel peak hold module after hold, VCC is the 5V power supply, and GND is ground.

[0050] This invention provides a four-channel peak signal acquisition circuit based on SiP, referring to... Figure 1 As shown, the circuit includes a four-channel peak hold module and a signal acquisition module. The input of the four-channel peak hold module is an analog pulse signal, which is processed by peak hold and outputs a held analog signal. The held analog signal is input to the signal acquisition module, which is converted from analog to digital and outputs a corresponding serial digital signal.

[0051] As a preferred embodiment, refer to Figure 1 As shown, the four-channel peak hold module includes four channels with identical circuit structures, which are as follows:

[0052] The first channel includes a first dual-channel operational amplifier chip OP1, a first diode chip D1, a first resistor R1, a second resistor R2, and a first capacitor C1. The first dual-channel operational amplifier chip includes two operational amplifiers connected in a cascaded manner, specifically amplifier OP1-A and amplifier OP1-B. The positive power supply pin of the first dual-channel operational amplifier chip is connected to the positive power supply VCC, and the negative power supply pin is grounded. The first positive input pin of the first dual-channel operational amplifier chip (i.e., the positive input pin of amplifier OP1-A) receives the analog pulse signal IN1 of the first channel, and the first positive input pin is grounded through the first resistor R1. The first negative input pin of the first dual-channel operational amplifier chip (i.e., the negative input pin of amplifier OP1-A) is connected to the second output pin of the first dual-channel operational amplifier chip. The first negative input pin (i.e., the negative input pin of amplifier OP1-B) is connected to the first negative input pin (i.e., the negative input pin of amplifier OP1-A), the second negative input pin (i.e., the negative input pin of amplifier OP1-B), and the second output pin (i.e., the output pin of amplifier OP1-B) of the first dual-channel operational amplifier chip are connected to serve as the output pin of the first channel; the first output pin (i.e., the output pin of amplifier OP1-A) of the first dual-channel operational amplifier chip is connected to the anode of the first diode D1, the cathode of the first diode D1 is connected to the second positive input pin (i.e., the positive input pin of amplifier OP1-B) of the first dual-channel operational amplifier chip, and is connected to one common terminal of the first capacitor C1 and the second resistor R2, and the other common terminal of the first capacitor C1 and the second resistor R2 is grounded.

[0053] The second channel includes a second dual-channel operational amplifier chip OP2, a second diode chip D2, a third resistor R3, a fourth resistor R4, and a second capacitor C2. The second dual-channel operational amplifier chip includes two operational amplifiers connected in a cascaded manner, specifically amplifiers OP2-A and OP2-B. The positive power supply pin of the second dual-channel operational amplifier chip is connected to the positive power supply VCC, and the negative power supply pin is grounded. The first positive input pin of the second dual-channel operational amplifier chip (i.e., the positive input pin of amplifier OP2-A) receives the analog pulse signal IN2 of the second channel, and the first positive input pin is grounded through the first resistor R3. The first negative input pin of the second dual-channel operational amplifier chip (i.e., the negative input pin of amplifier OP2-A) is connected to the second output pin of the second dual-channel operational amplifier chip. The first negative input pin (i.e., the negative input pin of amplifier OP2-B) of the second dual-channel operational amplifier chip is connected to the second negative input pin (i.e., the negative input pin of amplifier OP2-A), the second negative input pin (i.e., the negative input pin of amplifier OP2-B), and the second output pin (i.e., the output pin of amplifier OP2-B), which are then connected to serve as the output pin of the second channel; the first output pin (i.e., the output pin of amplifier OP2-A) of the second dual-channel operational amplifier chip is connected to the anode of the second diode D2, the cathode of the second diode D2 is connected to the second positive input pin (i.e., the positive input pin of amplifier OP2-B) of the second dual-channel operational amplifier chip, and is connected to one common terminal of the second capacitor C2 and the fourth resistor R4, and the other common terminal of the second capacitor C2 and the fourth resistor R4 is grounded.

[0054] The third channel includes a third dual-channel operational amplifier chip OP3, a third diode chip D3, a fifth resistor R5, a sixth resistor R6, and a third capacitor C3. The third dual-channel operational amplifier chip includes two operational amplifiers connected in a cascaded manner, specifically amplifiers OP3-A and OP3-B. The positive power supply pin of the third dual-channel operational amplifier chip is connected to the positive power supply VCC, and the negative power supply pin is grounded. The first positive input pin of the third dual-channel operational amplifier chip (i.e., the positive input pin of amplifier OP3-A) receives the analog pulse signal IN3 of the third channel, and the first positive input pin is grounded through the fifth resistor R5. The first negative input pin of the third dual-channel operational amplifier chip (i.e., the negative input pin of amplifier OP3-A) is connected to the second output pin of the third dual-channel operational amplifier chip. The first negative input pin (i.e., the negative input pin of amplifier OP3-B) of the third dual-channel operational amplifier chip is connected to the second negative input pin (i.e., the negative input pin of amplifier OP3-A), the second negative input pin (i.e., the negative input pin of amplifier OP3-B), and the second output pin (i.e., the output pin of amplifier OP3-B), which are then connected to serve as the output pin of the third channel; the first output pin (i.e., the output pin of amplifier OP3-A) of the third dual-channel operational amplifier chip is connected to the anode of the third diode D3, the cathode of the third diode D3 is connected to the second positive input pin (i.e., the positive input pin of amplifier OP3-B) of the third dual-channel operational amplifier chip, and is connected to one common terminal of the third capacitor C3 and the sixth resistor R6, and the other common terminal of the third capacitor C3 and the sixth resistor R6 is grounded.

[0055] The fourth channel includes a fourth dual operational amplifier chip OP4, a fourth diode chip D4, a seventh resistor R7, an eighth resistor R8, and a fourth capacitor C4. The fourth dual operational amplifier chip includes two operational amplifiers connected in a cascaded manner, specifically amplifiers OP4-A and OP4-B. The positive power supply pin of the fourth dual operational amplifier chip is connected to the positive power supply VCC, and the negative power supply pin is grounded. The first positive input pin of the fourth dual operational amplifier chip (i.e., the positive input pin of amplifier OP4-A) receives the analog pulse signal IN4 of the fourth channel, and the first positive input pin is grounded through the seventh resistor R7. The first negative input pin of the fourth dual operational amplifier chip (i.e., the negative input pin of amplifier OP4-A) is connected to the second output pin of the fourth dual operational amplifier chip. The first negative input pin (i.e., the negative input pin of amplifier OP4-B) of the fourth dual-channel operational amplifier chip is connected to the second negative input pin (i.e., the negative input pin of amplifier OP4-A), the second negative input pin (i.e., the negative input pin of amplifier OP4-B), and the second output pin (i.e., the output pin of amplifier OP4-B), which are then connected to serve as the output pin of the fourth channel; the first output pin (i.e., the output pin of amplifier OP4-A) of the fourth dual-channel operational amplifier chip is connected to the anode of the fourth diode D4, the cathode of the fourth diode D4 is connected to the second positive input pin (i.e., the positive input pin of amplifier OP4-B) of the fourth dual-channel operational amplifier chip, and is connected to one common terminal of the fourth capacitor C4 and the eighth resistor R8, and the other common terminal of the fourth capacitor C4 and the eighth resistor R8 is grounded.

[0056] Figures 2-5 They are respectively Figure 1 Circuit diagrams of the first, second, third, and fourth units in the four-channel peak hold module.

[0057] In a preferred embodiment, the dual-channel operational amplifier chip adopts dual-channel operational amplifier integrated chips IC1~IC4, specifically the AD8042 manufactured by ADI.

[0058] In a preferred embodiment, the diodes D1 to D4 are SC070H100A5F manufactured by International Rectifier (IR).

[0059] In a preferred embodiment, the resistance values ​​of resistors R1 to R8 are all 10kΩ.

[0060] In a preferred embodiment, the capacitance values ​​of capacitors C1 to C4 are 0.01 μF.

[0061] As a preferred embodiment, refer to Figures 2-5As shown, in the four-channel peak hold module, the dual operational amplifier chip is an AD8042 dual operational amplifier chip. The four-channel peak hold module specifically consists of four structurally identical units. Specifically:

[0062] Reference Figure 2 As shown, the first unit includes a first dual-channel operational amplifier chip IC1, a first diode chip D1, a first resistor R1, a second resistor R2, and a first dual-capacitor C1. Pin 8 of the dual-channel operational amplifier chip IC1 is connected to a positive 5V power supply VCC, and pin 4 is grounded; pin 3 of the dual-channel operational amplifier chip IC1 receives the pulse signal IN1 of the first channel and is grounded through the first resistor R1; pin 2 of the dual-channel operational amplifier chip IC1 is connected to pin 6, and pin 6 of the dual-channel operational amplifier chip IC1 is connected to pin 7, serving as the output terminal OUT1 of the first channel; pin 1 of the dual-channel operational amplifier chip IC1 is connected to the cathode of the first diode D1, pin 5 of the dual-channel operational amplifier chip IC1 is connected to the anode of the first diode D1, one common terminal of the first capacitor C1 and the second resistor R2 is connected to pin 5 of the dual-channel operational amplifier chip IC1, and the other common terminal of the first capacitor C1 and the second resistor R2 is grounded.

[0063] Reference Figure 3 As shown, the second unit includes a second dual-channel operational amplifier chip IC2, a second diode chip D2, a third resistor R3, a fourth resistor R4, and a second capacitor C2. Pin 8 of the second dual-channel operational amplifier chip IC2 is connected to a positive 5V power supply VCC, and pin 4 is grounded. Pin 3 of the second dual-channel operational amplifier chip IC2 receives the pulse signal IN2 from the second channel and is simultaneously grounded through the third resistor R3. Pin 2 of the second dual-channel operational amplifier chip IC2 is connected to its pin 6, and pin 6 is connected to its pin 7, serving as the output terminal OUT2 of the second channel. Pin 1 of the second dual-channel operational amplifier chip IC2 is connected to the cathode of the second diode D2, and pin 5 of the second dual-channel operational amplifier chip IC2 is connected to the anode of the second diode D2. One common terminal of the second capacitor C2 and the fourth resistor R4 is connected to pin 5 of the second dual-channel operational amplifier chip IC2, and the other common terminal of the second capacitor C2 and the fourth resistor R4 is grounded.

[0064] Reference Figure 4As shown, the third unit includes a third dual-channel operational amplifier chip IC3, a third diode chip D3, a fifth resistor R5, a sixth resistor R6, and a third capacitor C3. Pin 8 of the third dual-channel operational amplifier chip IC3 is connected to a positive 5V power supply VCC, and pin 4 is grounded. Pin 3 of the third dual-channel operational amplifier chip IC3 receives the pulse signal IN3 from the third channel and is also grounded through the fifth resistor R5. Pin 2 of the third dual-channel operational amplifier chip IC3 is connected to its pin 6, and pin 6 is connected to its pin 7, serving as the output terminal OUT3 of the third channel. Pin 1 of the third dual-channel operational amplifier chip IC3 is connected to the cathode of the third diode D3, and pin 5 of the third dual-channel operational amplifier chip IC3 is connected to the anode of the third diode D3. One common terminal of the third capacitor C3 and the sixth resistor R6 is connected to pin 5 of the third dual-channel operational amplifier chip IC3, and the other common terminal of the third capacitor C3 and the sixth resistor R6 is grounded.

[0065] Reference Figure 5 As shown, the fourth unit includes a fourth dual-channel operational amplifier chip IC4, a fourth diode chip D4, a seventh resistor R7, an eighth resistor R8, and a fourth capacitor C4. Pin 8 of the fourth dual-channel operational amplifier chip IC4 is connected to the positive 5V power supply VCC, and pin 4 is grounded. Pin 3 of the fourth dual-channel operational amplifier chip IC4 receives the pulse signal IN4 from the fourth channel and is also grounded through the seventh resistor R7. Pin 2 of the fourth dual-channel operational amplifier chip IC4 is connected to its pin 6, and pin 6 is connected to its pin 7, serving as the output terminal OUT4 of the fourth channel. Pin 1 of the fourth dual-channel operational amplifier chip IC4 is connected to the cathode of the fourth diode D4, and pin 5 of the fourth dual-channel operational amplifier chip IC4 is connected to the anode of the fourth diode D4. One common terminal of the fourth capacitor C2 and the eighth resistor R4 is connected to pin 5 of the fourth dual-channel operational amplifier chip IC4, and the other common terminal of the fourth capacitor C2 and the eighth resistor R4 is grounded.

[0066] Figure 6 for Figure 1 Circuit diagram of the signal acquisition module. Figure 6 In this circuit, the signal acquisition module includes a microcontroller chip. Pins 18, 19, 20, and 26 of the microcontroller chip are connected to the output pins OUT1~OUT4 of the front-end four-channel peak hold module, respectively, for receiving analog input signals. Pins 59 and 60 are brought out externally as input / output pins for I2C digital control signals. Pins 63 and 67 are brought out externally as the download interface for the microcontroller's internal program. Pins 80 and 82 are brought out externally as input / output pins for UART digital control signals.

[0067] As a preferred embodiment, refer to Figure 6 As shown, the signal acquisition module uses a microcontroller chip, which includes four signal input ports. The input signals are the four output signals of the four-channel peak hold module, and the output signals are serial digital signals.

[0068] In a preferred embodiment, the microcontroller chip is an STM32F031. The I2C digital control signals conform to the I2C bus protocol standard, and the UART digital control signals conform to the UART communication protocol standard.

[0069] In this embodiment of the invention, the power supply voltage is 5V, the pulse width of signals IN1~IN4 is ≥200ns, and the amplitude is 0~4V.

[0070] The embodiments of the present invention can achieve the goals of versatility, high density, and miniaturization, while simplifying the complexity of applications.

[0071] This invention is designed based on multiple bare chips and peripheral components. It can simultaneously perform peak hold on four narrow pulse signals and acquire the held signals, outputting digital signals. The peak hold module, based on an operational amplifier, can process four signals simultaneously. The default hold time (100%~90%) is greater than 10µs and can be adjusted via an external resistor. The signal acquisition module integrates a microprocessor chip with a maximum operating frequency of 72MHz, an acquisition resolution of 12bit, a maximum conversion rate of 1MSPS, and provides UART and I2C interfaces. This invention can simultaneously perform peak hold operations on four channels of pulse signals with adjustable hold time. Simultaneously, it performs analog-to-digital conversion on the held output signals and can perform certain calculations and processing on the digital signals. Based on a miniaturized, high-density, and modular design, this circuit offers high flexibility and simplicity in application, significantly increasing its application range and reducing its ease of use compared to existing systems.

[0072] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A four-channel peak signal acquisition circuit based on SiP, characterized in that, include: The four-channel peak hold module and signal acquisition module are used. The input of the four-channel peak hold module is an analog pulse signal. After peak hold processing, the output is a held analog signal. The held analog signal is input to the signal acquisition module, which is converted from analog to digital and outputs a corresponding serial digital signal. The four-channel peak hold module includes four channels with identical circuit structures. Each channel includes a dual operational amplifier chip, a diode chip, a first resistor, a second resistor, and a capacitor. The dual operational amplifier chip includes two operational amplifiers connected in a cascaded manner, with its positive power supply pin connected to a positive power supply and its negative power supply pin grounded. The first positive input pin of the dual operational amplifier chip receives the analog pulse signal of the first channel and is grounded through the first resistor. The second negative input pin of the dual operational amplifier chip is connected to the first output pin of the dual operational amplifier chip and serves as the output pin of that channel. The first output pin of the dual operational amplifier chip is connected to the anode of the diode, and the cathode of the diode is connected to the second positive input pin of the dual operational amplifier chip and connected to a common terminal of the capacitor and the second resistor. The other common terminal of the capacitor and the second resistor is grounded.

2. The SiP-based four-channel peak signal acquisition circuit according to claim 1, characterized in that, In the four-channel peak hold module, the dual operational amplifier chip is a dual operational amplifier chip of model AD8042. Its pin (8) is connected to the positive power supply, its pin (4) is grounded, its pin (3) receives the pulse signal, its pin (3) is grounded through the first resistor, its pin (5) is connected to the anode of the diode, its pin (1) is connected to the cathode of the diode, and its pin (5) is connected to one common terminal of the capacitor and the second resistor. The other common terminal of the capacitor and the second resistor is grounded. Its pin (2), pin (6) and pin (7) are connected and used as the output terminal of the module.

3. The SiP-based four-channel peak signal acquisition circuit according to claim 1, characterized in that, The signal acquisition module uses a microcontroller chip, which includes four signal input ports. The input signals are the four output signals of the four-channel peak hold module, and the output signals are serial digital signals.

4. The SiP-based four-channel peak signal acquisition circuit according to claim 3, characterized in that, The microcontroller chip is an STM32F031.

5. The SiP-based four-channel peak signal acquisition circuit according to claim 1, characterized in that, The diode is model number SC070H100A5F.

6. The SiP-based four-channel peak signal acquisition circuit according to claim 1, characterized in that, The resistance values ​​of both the first resistor and the second resistor are 10kΩ.

7. The SiP-based four-channel peak signal acquisition circuit according to claim 1, characterized in that, The capacitance value of the capacitor is 0.01μF.

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