Semiconductor device and capacitor structure
By sandwiching an oxide layer in a semiconductor device and optimizing the capacitor structure, the problems of insufficient performance and reliability of dynamic random access memory were solved, and the performance of semiconductor devices was improved.
Patent Information
- Application Number
- CN202520288689.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-21
- Publication Date
- 2025-12-02
- Estimated Expiration
- 2035-02-21
AI Technical Summary
Existing dynamic random access memory (DRAM) suffers from insufficient performance and reliability.
In semiconductor devices, the design of the capacitor structure is optimized by sandwiching an oxide layer between the upper electrode and the semiconductor layer of the capacitor structure and forming the capacitor structure using a multilayer support structure and deposition process, including a lower electrode, a capacitor dielectric layer, an upper electrode and a semiconductor layer.
This improves the performance and reliability of semiconductor devices and capacitor structures.
Smart Images
Figure CN223626237U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of semiconductor technology, and in particular to a semiconductor device and capacitor structure. Background Technology
[0002] Dynamic random access memory (DRAM) is a type of volatile memory, comprising an array area consisting of multiple memory cells and a peripheral area consisting of control circuitry. Each memory cell consists of a transistor and a capacitor electrically connected to the transistor. The transistor controls the storage and release of charge in the capacitor to store data. The control circuitry addresses each memory cell and controls data access by using word lines (WL) and bit lines (BL) that span the array area and are electrically connected to each memory cell. However, due to limitations in manufacturing technology, existing DRAMs still have many shortcomings and require further improvement to effectively enhance the performance and reliability of related memory components. Utility Model Content
[0003] The purpose of this invention is to provide a semiconductor device and capacitor structure to improve the performance and reliability of the semiconductor device and capacitor structure.
[0004] In a first aspect, to solve the above-mentioned technical problems, this utility model provides a semiconductor device, which may include:
[0005] Base;
[0006] Multiple capacitor structures are disposed on the substrate at intervals, and each capacitor structure includes a lower electrode, a capacitor dielectric layer, an upper electrode, and a semiconductor layer stacked in sequence.
[0007] In at least one of the capacitor structures, an oxide layer is sandwiched between the upper electrode and the semiconductor layer.
[0008] Optionally, the semiconductor device may further include:
[0009] Multiple support structures are located between adjacent lower electrodes and include multiple support layers spaced apart in a vertical direction. The capacitor dielectric layer and the upper electrode also extend and cover the gaps between adjacent support layers in the support structures.
[0010] Optionally, the lower electrode of the capacitor structure may be cylindrical or cylindrical.
[0011] Optionally, the upper electrode of the capacitor structure having the lower electrode in the shape of the cylinder may form a first gap around it.
[0012] Optionally, the upper electrode in the interval between the support layers may form a second gap.
[0013] Optionally, the oxide layer is located on the inner surface of the first or second void and surrounds to form a third void.
[0014] Optionally, the oxide layer may include discontinuous oxides.
[0015] Optionally, the discontinuous oxide may have multiple air gaps, which break the discontinuous oxide into multiple spaced segments.
[0016] Optionally, the oxide layer has multiple notches.
[0017] Optionally, the semiconductor layer is located on the oxide layer and fills the third void.
[0018] Secondly, to solve the above-mentioned technical problems, this utility model also provides a capacitor structure, which may include at least:
[0019] The surrounding structure, from the outside to the inside, includes a semiconductor layer, an oxide layer, an upper electrode, a capacitor dielectric layer, and a lower electrode, wherein the oxide layer physically contacts the semiconductor layer and the upper electrode.
[0020] Optionally, the surrounding structure may further include the capacitor dielectric layer, the upper electrode, the oxide layer, and the semiconductor layer from the lower electrode inward.
[0021] Optionally, the lower electrode of the capacitor structure may be cylindrical or cylindrical.
[0022] In this invention, multiple capacitor structures each include a lower electrode, a capacitor dielectric layer, an upper electrode, and a semiconductor layer stacked in sequence. An oxide layer is also sandwiched between the upper electrode and the semiconductor layer in at least one capacitor structure, thereby proposing a new capacitor structure and simultaneously achieving the purpose of improving the performance and reliability of the semiconductor device and the capacitor structure. Attached Figure Description
[0023] The accompanying drawings are provided to further illustrate the present application and form part of the specification. They are used together with the following detailed description to explain the present application, but do not constitute a limitation thereof. In the drawings:
[0024] Figures 1-4This is a schematic diagram of the semiconductor device provided in the first embodiment of the present invention during the fabrication process.
[0025] Figures 5-8 This is a schematic diagram of the semiconductor device provided in the second embodiment of the present invention during the fabrication process.
[0026] Figures 9-10 This is a schematic diagram of the semiconductor device provided in the third embodiment of the present invention during the fabrication process.
[0027] Figures 11-12 This is a schematic diagram of the semiconductor device provided in the fourth embodiment of the present invention during the fabrication process.
[0028] The attached figures are labeled as follows:
[0029] 100 - Substrate, 110 - Support structure, 111 - First support layer, 113 - Second support layer, 115 - Third support layer, 120 - Capacitor structure, 121 - Lower electrode, 122 - Capacitor dielectric layer, 123 - Upper electrode, 130 - Oxide layer, 140 - Semiconductor layer, 101 - First gap, 102 - Second gap, 103 - Third gap, 104 - Air gap, 105 - Notch, 131 - Subsegment.
[0030] In the accompanying drawings, the same parts are referred to by the same reference numerals, and the drawings are not drawn to scale. Detailed Implementation
[0031] To make the technical solutions and advantages of the embodiments of this utility model clearer, the technical solutions of this utility model will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary implementation methods of this utility model are shown in the accompanying drawings, it should be understood that this utility model can be implemented in various forms and should not be limited to the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of this utility model and to fully convey the scope of this utility model to those skilled in the art.
[0032] The present invention will be described more specifically by way of example in the following paragraphs with reference to the accompanying drawings. The advantages and features of the present invention will become clearer from the following description and claims. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention. It is understood that the meanings of "on," "above," and "over" in the present invention should be interpreted in the broadest sense, such that "on" not only means "on" something without any intervening feature or layer (i.e., directly on something), but also includes "on" something with an intervening feature or layer.
[0033] Furthermore, for ease of description, spatial relative terms such as “on,” “above,” “above,” “upper,” “above,” “upper,” etc., may be used herein to describe the relationship between one element or feature and another element or feature as shown in the figures. In addition to the orientations depicted in the figures, the spatial relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatial relative descriptive terms used herein may be interpreted accordingly.
[0034] In the embodiments of this utility model, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be noted that the technical solutions described in the embodiments of this utility model can be combined arbitrarily without conflict.
[0035] Please refer to Figure 3 and Figure 4 ,in Figure 3 This is a cross-sectional schematic diagram of the semiconductor device in the first embodiment of this utility model. Figure 4 for Figure 3 The semiconductor device shown is a top view along tangent AA. This semiconductor device can be used to manufacture dynamic random access memory (DRAM), and without departing from the spirit of this invention, it can also be applied to other types of memory.
[0036] like Figure 3 and Figure 4 As shown, the semiconductor device includes a substrate 100, which may be a silicon substrate, a silicon-containing substrate (such as SiC, SiGe), or a silicon-on-insulator substrate, or a substrate made of other suitable materials, but is not limited thereto. A plurality of capacitor structures 120 are arranged at intervals on the substrate 100 along a direction parallel to the surface of the substrate 100 (hereinafter referred to as the horizontal direction). The details of each capacitor structure 120 may include a lower electrode 121, a capacitor dielectric layer 122, an upper electrode 123, and a semiconductor layer 140 stacked sequentially, and an oxide layer 130 is further sandwiched between the upper electrode 123 and the semiconductor layer 140 in at least one of the plurality of capacitor structures 120.
[0037] It should be understood that the substrate 100 may further form components such as position line structures, sidewall structures, contact structures, and connecting pad structures (not shown), but is not limited thereto.
[0038] Specifically, in the first embodiment of this utility model, the lower electrode 121 of the capacitor structure 120 is cylindrical in shape. Multiple lower electrodes 121 of the plurality of capacitor structures 120 are disposed on the substrate 100 with mutual spacing along the horizontal direction, and a support structure 110 is also disposed between adjacent lower electrodes 121. The capacitor dielectric layer 122, upper electrode 123, and oxide layer 130 in the capacitor structure 120 conformally cover the plurality of cylindrical lower electrodes 121, while the semiconductor layer 140 fills the gaps within the oxide layer 130 of the plurality of capacitor structures 120. Further, the support structure 110 may include multiple support layers sequentially disposed from bottom to top, such as a first support layer 111, a second support layer 113, and a third support layer 115 sequentially disposed from bottom to top along the vertical direction. The capacitor dielectric layer 122, the upper electrode 123, the oxide layer 130, and the semiconductor layer 140 in the plurality of capacitor structures 120 also extend and cover the intervals between adjacent support layers in the plurality of support structures 110, such as the interval between the first support layer 111 and the second support layer 113, and the interval between the second support layer 113 and the third support layer 115, but are not limited thereto.
[0039] In one embodiment, the capacitor structure 120 having the cylindrical lower electrode 121 is formed, for example, by first using a deposition process to form a multilayer structure of a support structure 110 on the substrate 100, such as a first support layer 111, a first sacrificial layer (not shown), a second support layer 113, a second sacrificial layer (not shown), and a third support layer 115. Then, multiple vias (not shown) are formed within the multilayer structure of the support structure 110, and a lower electrode material layer is conformally formed within the multiple vias using a deposition process such as physical vapor deposition, chemical vapor deposition, and atomic layer deposition, i.e., multiple lower electrodes 121 are formed on the substrate 100. Then, after removing a portion of the support structure 110 using photolithography and etching processes such as dry etching and / or wet etching, the capacitor dielectric layer 122 and the upper electrode 123 are conformally formed using a further deposition process. Figure 1 As shown; in this configuration, the conformally formed upper electrode 123 forms a first gap 101 around each capacitor structure 120, and forms a second gap 102 around the gap between adjacent support layers in the support structure 110; then, the oxide layer 130 is conformally formed using a deposition process, so that the conformally formed oxide layer 130 is specifically located on the upper electrode 123, and on the inner surface of the first gap 101 or the second gap 102, thereby forming a third gap 103 around the upper electrode 123 on the substrate 100, as shown. Figure 2As shown; finally, a semiconductor layer 140 is formed using a deposition process, which fills the third void 103 and has a top surface higher than the top surface of the oxide layer 130. For example, the materials of the lower electrode 121 and the upper electrode 123 may include titanium nitride, tantalum nitride, SiGe, combinations of the above materials, or other suitable multilayer conductive materials, but are not limited thereto; the capacitor dielectric layer 122 may include a high dielectric constant material layer, such as TaOO, TaAlO, TaON, AlO, AlSiO, HfO, HfSiO, ZrO, ZrSiO, TiO, TiAlO, BST ((Ba,Sr)TiO), STO (SrTiO), BTO (BaTiO), PZT (Pb(Zr,Ti)O), (Pb,La)(Zr,Ti)O, Ba(Zr,Ti)OO, Sr(Zr,Ti)O, combinations of the above materials, or other suitable dielectric materials, but are not limited thereto; the material of the oxide layer 130 may be an insulating material, such as an oxide or nitride, but is not limited thereto; the material of the semiconductor layer 140 may be crystalline silicon, polycrystalline silicon, or other suitable dielectric materials, but are not limited thereto. The materials used may be, but are not limited to, silicon, amorphous silicon, doped silicon, silicon-germanium (SiGe), or other suitable semiconductor materials. The materials of the first support layer 111, the second support layer 113, and the third support layer 115 within the support structure 110 may be oxide materials, such as silicon oxide, boro-phospho-silicate glass (BPSG), but are not limited to these.
[0040] Those skilled in the art will readily understand that, to meet actual product requirements, the semiconductor device of this utility model may have other forms and is not limited to those described above. The following will further describe other embodiments or variations of the semiconductor device of this utility model. For the sake of simplicity, the following description focuses on the differences between the embodiments, without repeating the similarities. Furthermore, identical components in the various embodiments of this utility model are designated with the same reference numerals to facilitate comparison between the embodiments.
[0041] Please refer to Figure 7 and Figure 8 ,in Figure 7 This is a cross-sectional schematic diagram of the semiconductor device in the second embodiment of this utility model. Figure 8 for Figure 7 The semiconductor device shown is a top view along the tangent line AA. Figure 7 and Figure 8As shown, the structure of the semiconductor device in this embodiment is largely the same as that in the first embodiment described above. For example, the semiconductor device also includes a substrate 100 and multiple capacitor structures 120 disposed on the substrate 100. The capacitor structure 120 may also include sequentially stacked lower electrodes 121, capacitor dielectric layers 122, upper electrodes 123, and semiconductor layers 140. Furthermore, at least one of the capacitor structures 120 has an oxide layer 130 sandwiched between the upper electrode 123 and the semiconductor layer 140. The similarities will not be repeated here. The main difference between the semiconductor device in this embodiment and the first embodiment is that the lower electrode 121 in the capacitor structure 120 in this embodiment is columnar. In this configuration, the capacitor dielectric layer 122, upper electrode 123, and oxide layer 130 in each capacitor structure 120 are sequentially conformally formed on the surface of multiple columnar lower electrodes 121. That is, in this embodiment, the first gap 101 is not provided within the upper electrode 123 located within each capacitor structure 120. Figure 5 As shown; similarly, the oxide layer 130 subsequently formed within the capacitor structure 120 also does not have a third gap 103, as... Figure 6 As shown.
[0042] It should be understood that the above Figures 5 to 7 The fabrication process of the semiconductor device provided in the second embodiment of this utility model is largely the same as that of the semiconductor device in the first embodiment, and the similarities will not be repeated here. The main difference lies in the shape of the lower electrode 121 formed in the through hole. Figure 5 As shown.
[0043] Please refer to Figure 9 and Figure 10 ,in Figure 9 This is a cross-sectional schematic diagram of the semiconductor device in the third embodiment of this utility model. Figure 10 for Figure 9 The semiconductor device shown is a top view along the tangent line AA. Figure 9 and Figure 10As shown, the structure of the semiconductor device in this embodiment is largely the same as that of the semiconductor device in the first or second embodiment described above. For example, the semiconductor device also includes a substrate 100 and a plurality of capacitor structures 120 disposed on the substrate 100. The details of the capacitor structure 120 may also include a lower electrode 121, a capacitor dielectric layer 122, an upper electrode 123, and a semiconductor layer 140 stacked in sequence. An oxide layer 130 is also sandwiched between the upper electrode 123 and the semiconductor layer 140 in at least one of the plurality of capacitor structures 120. The similarities will not be described again here. The main difference between the semiconductor device of this embodiment and the aforementioned first or second embodiments is that the oxide layer 130 located in the capacitor structure 120 and the space between adjacent support layers in the support structure 110 can be a discontinuous oxide (e.g., discontinuous silicon dioxide). Specifically, the oxide layer 130, being a discontinuous oxide, can have multiple air gaps 104, which break the oxide layer 130 (i.e., the discontinuous oxide) into multiple spaced segments 131. In this way, the subsequently formed semiconductor layer 140 not only fills the third gap 103 formed around the oxide layer 130, but also further fills the multiple air gaps 104 within the oxide layer 130, allowing the semiconductor layer 140 to pass through the oxide layer 130 via the air gaps 104 and directly contact the upper electrode 123 in the capacitor structure 120 or the support structure 110. In one embodiment, the width or depth of the plurality of air gaps 104 along the horizontal or vertical direction may be the same or different, and the spacing between adjacent air gaps 104 may be the same or different.
[0044] It should be understood that the semiconductor device fabrication process provided in the third embodiment of this utility model is largely the same as the semiconductor device fabrication process in the first or second embodiment described above. The similarities will not be repeated here. The main difference is that after the oxide layer 130 is conventionally formed by deposition process, an etching process, such as dry etching process, can be used to form a plurality of air gaps 104 in the oxide layer 130, which may be the same or different in width and / or depth, to expose part of the top surface of the upper electrode 123 located in the capacitor structure 120 or the support structure 110, but this is not a limitation.
[0045] Please refer to Figure 11 and Figure 12 ,in Figure 11 This is a cross-sectional schematic diagram of the semiconductor device in the fourth embodiment of this utility model. Figure 12 for Figure 11 The semiconductor device shown is a top view along the tangent line AA. Figure 11 and Figure 12As shown, the structure of the semiconductor device in this embodiment is largely the same as that of the semiconductor devices in the first to third embodiments described above. For example, the semiconductor device also includes a substrate 100 and a plurality of capacitor structures 120 disposed on the substrate 100. The details of the capacitor structure 120 may also include a lower electrode 121, a capacitor dielectric layer 122, an upper electrode 123, and a semiconductor layer 140 stacked in sequence. An oxide layer 130 is also sandwiched between the upper electrode 123 and the semiconductor layer 140 in at least one of the plurality of capacitor structures 120. The similarities will not be described again here. The main difference between the semiconductor device in this embodiment and the semiconductor devices in the first to third embodiments described above is that the oxide layer 130 located in the capacitor structure 120 and the interval between adjacent support layers in the support structure 110 may have a plurality of gaps 105, and the bottom of each of the plurality of gaps 105 has residual oxide layer 130. In this way, the plurality of gaps 105 make the surface of the oxide layer 130 uneven and wavy. The subsequently formed semiconductor layer 140 not only fills the third gap 103 formed around the oxide layer 130, but also further fills the plurality of gaps 105 within the oxide layer 130. However, in this embodiment, the semiconductor layer 140 is only in direct contact with the oxide layer 130. In one embodiment, the width, depth, or shape of the plurality of gaps 105 along the horizontal or vertical direction may be the same or different, and the spacing between adjacent gaps 105 may be the same or different.
[0046] It should be understood that the semiconductor device fabrication process provided in the fourth embodiment of this utility model is largely the same as the semiconductor device fabrication process in the first to third embodiments described above. The similarities will not be repeated here. The main difference is that after the oxide layer 130 is conventionally formed by deposition process, an etching process, such as dry etching process, can be used to form a plurality of notches 105 in the oxide layer 130, which may be the same or different in width, depth and / or shape. The notches 105 do not penetrate the oxide layer 130, but this is not a limitation.
[0047] Furthermore, based on the above description, the fifth embodiment of this utility model also provides a capacitor structure, such as... Figure 4 , Figure 8 , Figure 10 or Figure 12 As shown, the capacitor structure may specifically include:
[0048] The surrounding structure, from the outside to the inside, includes a semiconductor layer 140, an oxide layer 130, an upper electrode 123, a capacitor dielectric layer 122, and a lower electrode 121, wherein the oxide layer 130 physically contacts the semiconductor layer 140 and the upper electrode 123.
[0049] In one embodiment, the surrounding structure further includes, from the lower electrode 121 inwardly, the capacitor dielectric layer 122, the upper electrode 123, the oxide layer 130, and the semiconductor layer 140. Furthermore, the lower electrode 121 of the capacitor structure may be cylindrical or columnar, but is not limited thereto. Further, the oxide layer 130 may include discontinuous oxide; for example, the discontinuous oxide may have multiple air gaps 104 to break the oxide layer 130 (i.e., the discontinuous oxide) into multiple spaced segments 131 through the multiple air gaps 104; or, the oxide layer 130 may have multiple gaps 105, and the semiconductor layer 140 fills the third gap 103, multiple air gaps 104, or multiple gaps 105 formed around the oxide layer 130, but is not limited thereto.
[0050] It should be understood that "common shape" in this utility model refers to the construction of a continuous structural shape by utilizing the similarity and correlation between two or more shapes in terms of form; and the methods, processes and steps involved in this utility model are all existing technologies.
[0051] In summary, the multiple capacitor structures in this utility model each include a lower electrode, a capacitor dielectric layer, an upper electrode, and a semiconductor layer stacked in sequence, and at least one capacitor structure has an oxide layer sandwiched between the upper electrode and the semiconductor layer, so as to propose a new capacitor structure and simultaneously achieve the purpose of improving the performance and reliability of semiconductor devices.
[0052] The above description is merely a preferred embodiment of this utility model and is not intended to limit the scope of protection of this utility model. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this utility model are included within the scope of protection of this utility model.
Claims
1. A semiconductor device, characterized in that, include: Base; Multiple capacitor structures are disposed on the substrate at intervals, and each capacitor structure includes a lower electrode, a capacitor dielectric layer, an upper electrode, and a semiconductor layer stacked in sequence. In at least one of the capacitor structures, an oxide layer is sandwiched between the upper electrode and the semiconductor layer.
2. The semiconductor device as claimed in claim 1, characterized in that, Also includes: Multiple support structures are located between adjacent lower electrodes and include multiple support layers spaced apart in a vertical direction. The capacitor dielectric layer and the upper electrode also extend and cover the gaps between adjacent support layers in the support structures.
3. The semiconductor device as described in claim 1, characterized in that, The lower electrode of the capacitor structure is cylindrical or cylindrical.
4. The semiconductor device as described in claim 3, characterized in that, The upper electrode of the capacitor structure, which has a lower electrode in the shape of a cylinder, surrounds and forms a first gap.
5. The semiconductor device as claimed in claim 2, characterized in that, The upper electrode in the interval between the support layers forms a second gap.
6. The semiconductor device as claimed in claim 4 or 5, characterized in that, The oxide layer is located on the inner surface of the first or second void and surrounds to form a third void.
7. The semiconductor device as claimed in claim 6, characterized in that, The oxide layer comprises discontinuous oxides.
8. The semiconductor device as claimed in claim 7, characterized in that, The discontinuous oxide has multiple air gaps, which break the discontinuous oxide into multiple spaced segments.
9. The semiconductor device as claimed in claim 6, characterized in that, The oxide layer has multiple notches.
10. The semiconductor device as claimed in claim 8 or 9, characterized in that, The semiconductor layer is located on the oxide layer and fills the third void, the plurality of gaps, or the plurality of air gaps.
11. A capacitor structure, characterized in that, include: The surrounding structure, from the outside to the inside, includes a semiconductor layer, an oxide layer, an upper electrode, a capacitor dielectric layer, and a lower electrode, wherein the oxide layer physically contacts the semiconductor layer and the upper electrode.
12. The capacitor structure as described in claim 11, characterized in that, The surrounding structure, extending inward from the lower electrode, also includes the capacitor dielectric layer, the upper electrode, the oxide layer, and the semiconductor layer.
13. The capacitor structure as described in claim 11, characterized in that, The lower electrode of the capacitor structure is cylindrical or cylindrical.