Light-emitting diode and light-emitting equipment

Abstract

The utility model provides a light-emitting diode and a light-emitting device. The light-emitting diode comprises a substrate; a dielectric material layer; the dielectric material layer is arranged on the upper surface of the substrate and is composed of a plurality of circular truncated cones, and the circular truncated cones are uniformly arranged on the upper surface of the substrate and are arranged at intervals; and the LED chips are uniformly arranged on the upper surface of the dielectric material layer, and the bottoms of the LED chips are arranged corresponding to the circular truncated cone. According to the light-emitting diode and the light-emitting device, the dielectric material layer is arranged on the upper surface of the substrate, and the dielectric material layer is composed of the plurality of circular truncated cone bodies, so that a stripping interface between the substrate and an epitaxy is smoother, abnormal conditions of subfissure and stripping surface damage when the substrate is stripped are avoided, and the service life of the light-emitting diode and the light-emitting device is prolonged. And through the dielectric material layer composed of a plurality of circular truncated cones, the problem of low external quantum efficiency of a flat epitaxy serving as a light-emitting surface can be avoided.

Description

Technical Field

[0001] This utility model relates to the field of LED chip technology, and in particular to a light-emitting diode and a light-emitting device. Background Technology

[0002] An LED chip is a solid-state semiconductor device. The heart of an LED is a semiconductor wafer, with one end attached to a support, serving as the negative electrode, and the other end connected to the positive electrode of the power supply. The entire wafer is encapsulated in epoxy resin. Also known as an LED light-emitting chip, it is the core component of an LED lamp, specifically the PN junction. Its main function is to convert electrical energy into light energy. The primary material of the chip is monocrystalline silicon. The semiconductor wafer consists of two parts: a P-type semiconductor, where holes are the dominant energy source, and an N-type semiconductor, where electrons are the dominant energy source. When these two semiconductors are connected, they form a PN junction. When current flows through the wafer, electrons are pushed towards the P-region, where they recombine with holes, releasing energy in the form of photons. This is the principle behind LED light emission.

[0003] The epitaxial structure of existing LED chips is usually grown on patterned or unpatterned sapphire substrates. The epitaxial wafer includes a patterned sapphire substrate, an aluminum nitride buffer layer, an N-type gallium nitride layer, a light-emitting layer, and a P-type gallium nitride layer.

[0004] In existing technologies, MicroLED chips typically require substrate peeling. For patterned sapphire substrates, there are height differences and uneven interface tilt angles at the peeling interface between the substrate and the epitaxial layer. Peeling MicroLED chips off patterned substrates can easily lead to microcracks and damage to the peeling surface. Utility Model Content

[0005] Therefore, the purpose of this utility model is to provide a light-emitting diode and a light-emitting device to overcome the shortcomings of the prior art.

[0006] In a first aspect, this utility model provides a light-emitting diode, comprising:

[0007] Substrate;

[0008] A dielectric material layer is disposed on the upper surface of the substrate. The dielectric material layer is composed of a plurality of frustums, which are uniformly disposed on the upper surface of the substrate and spaced apart from each other.

[0009] A number of LED chips are evenly disposed on the upper surface of the dielectric material layer, and the bottom of the LED chips is disposed corresponding to the frustum.

[0010] Compared with the prior art, the beneficial effects of this utility model are: by setting a dielectric material layer on the upper surface of the substrate, and the dielectric material layer is composed of several frustums, the peeling interface between the substrate and the epitaxial layer is made smoother, avoiding abnormal situations such as microcracks and peeling surface damage during substrate peeling. Furthermore, the dielectric material layer composed of several frustums can also avoid the problem of low quantum efficiency of a smooth epitaxial layer as the light-emitting surface.

[0011] Furthermore, the substrate is a sapphire substrate.

[0012] Furthermore, the dielectric material layer is a silicon oxide heterolayer.

[0013] Furthermore, the thickness of the dielectric material layer is

[0014] Furthermore, the angle between the sidewall of the frustum and the substrate is 63°-78°.

[0015] Furthermore, the bottom of the LED chip is provided with several grooves, and the grooves are configured to cooperate with the frustum.

[0016] Furthermore, the perimeter of the LED chip is less than or equal to 200 μm.

[0017] Secondly, this utility model also provides a light-emitting device, including the light-emitting diode as described above. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the light-emitting diode structure in the first embodiment of the present invention. Figure 1 ;

[0019] Figure 2 This is a schematic diagram of the light-emitting diode structure in the first embodiment of the present invention. Figure 2 .

[0020] Explanation of key component symbols:

[0021] 1. Substrate;

[0022] 2. Dielectric material layer; 21. Frustum;

[0023] 3. LED chip; 31. Channel.

[0024] The following detailed description, in conjunction with the accompanying drawings, will further illustrate this utility model. Detailed Implementation

[0025] To facilitate understanding of this utility model, a more complete description will be given below with reference to the accompanying drawings. Several embodiments of this utility model are shown in the drawings. However, this utility model can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this utility model will be more thorough and complete.

[0026] It should be noted that when a component is said to be "fixed to" another component, it can be directly on the other component or there may be an intervening component. When a component is said to be "connected to" another component, it can be directly connected to the other component or there may be an intervening component. The terms "vertical," "horizontal," "left," "right," and similar expressions used in this document are for illustrative purposes only.

[0027] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0028] Example 1

[0029] Please see Figures 1 to 2 The image shows a light-emitting diode in an embodiment of the present invention, comprising a substrate 1, a dielectric material layer 2, and an LED chip 3.

[0030] The dielectric material layer 2 is disposed on the upper surface of the substrate 1. The dielectric material layer 2 is composed of a plurality of frustums 21. The plurality of frustums 21 are uniformly disposed on the upper surface of the substrate 1 and are spaced apart. There are a plurality of LED chips 3. The plurality of LED chips 3 are uniformly disposed on the upper surface of the dielectric material layer 2, and the bottom of the LED chips 3 is correspondingly disposed to the frustums 21.

[0031] Specifically, in this embodiment, the substrate 1 is a sapphire substrate, and the dielectric material layer 2 is a silicon oxide heterolayer.

[0032] In addition, the bottom of the LED chip 3 is provided with a plurality of grooves 31, and the grooves 31 are configured to cooperate with the frustum 21.

[0033] In practical implementation:

[0034] Step 1: Provide a sapphire substrate with a smooth surface;

[0035] Step 2: Form a silicon oxide heterolayer on the upper surface of a flat sapphire substrate;

[0036] Step 3: Form a patterned mask using nanoimprinting or photolithography;

[0037] Step 4: A patterned silicon oxide heterolayer is formed using dry etching. The angle between the silicon oxide heterolayer and the sapphire substrate is controlled at 63° to maximize the chip's light extraction efficiency.

[0038] Step 5: Remove the mask above the silicon oxide heterolayer and clean the sapphire substrate with the patterned silicon oxide heterolayer.

[0039] Step 6: Epitaxial structures such as N-GaN layer, quantum hydrazine layer, and P-GaN layer are sequentially grown on the above sapphire substrate using MOCVD.

[0040] Step 7: Sequentially fabricate chip structures such as MSA, ISO, and PAD on the epitaxial layer;

[0041] Step 8: After the LED chip is fabricated, a layer of photoresist is coated on the chip surface using photolithography to expose the ISO area of ​​the chip;

[0042] Step 9: Immerse the chip in BOE solution to etch away the silicon oxide layer beneath the epitaxial layer.

[0043] Step 10: Use laser lift-off to peel the chip off the sapphire substrate to obtain the Micro-LED chip with a patterned substrate structure.

[0044] It is worth noting that in this embodiment, the perimeter of the LED chip 3 is 168 μm, and the thickness of the silicon oxide heterolayer is... The top diameter of the frustum 21 is In this embodiment, D = 1 / 2-5 / 4H, and the center distance between the frustums 21 is L = 1.1-1.5D. At this point, the chip's external quantum efficiency is 63%, and the yield is 99.9%.

[0045] Additionally, it should be explained that, considering the application scenarios of MicroLED chips, optimizing the patterned sapphire substrate with a flat gallium nitride and sapphire interface at the bottom helps improve the substrate peeling yield. The substrate peeling process causes virtually no damage to the sapphire, which can be recycled.

[0046] Example 2

[0047] The difference between the second embodiment of this utility model and the first embodiment is as follows:

[0048] In this embodiment, the perimeter of the LED chip 3 is 168 μm, the angle between the sidewall of the frustum 21 and the substrate 1 is 68°, and the thickness of the silicon oxide heterolayer is... The top diameter of the frustum 21 is In this embodiment, D = 1 / 2-5 / 4H, and the center distance between the frustums 21 is L = 1.1-1.5D. At this point, the chip's external quantum efficiency is 69%, and the yield is 97.5%.

[0049] Example 3

[0050] The difference between the third embodiment of this utility model and the above embodiments is that:

[0051] In this embodiment, the LED chip 3 has a perimeter of 90 μm, the angle between the sidewall of the frustum 21 and the substrate 1 is 71°, and the thickness of the silicon oxide heterolayer is... The top diameter of the frustum 21 is In this embodiment, D = 1 / 2-5 / 4H, and the center distance between the frustums 21 is L = 1.1-1.5D. At this point, the chip's external quantum efficiency is 70%, and the yield is 98.7%.

[0052] Example 4

[0053] The difference between the fourth embodiment of this utility model and the above embodiments is that:

[0054] In this embodiment, the LED chip 3 has a perimeter of 90 μm, the sidewall of the frustum 21 forms an angle of 75° with the substrate 1, and the thickness of the silicon oxide heterolayer is [missing information]. The top diameter of the frustum 21 is In this embodiment, D = 1 / 2-5 / 4H, and the center distance between the frustums 21 is L = 1.1-1.5D. At this point, the chip's external quantum efficiency is 70%, and the yield is 98.7%.

[0055] Example 5

[0056] The difference between the fifth embodiment of this utility model and the above embodiments is that:

[0057] In this embodiment, the LED chip 3 has a perimeter of 70 μm, the angle between the sidewall of the frustum 21 and the substrate 1 is 78°, and the thickness of the silicon oxide heterolayer is... The top diameter of the frustum 21 is In this embodiment, D = 1 / 2-5 / 4H, and the center distance between the frustums 21 is L = 1.1-1.5D. At this point, the chip's external quantum efficiency is 69%, and the yield is 98.3%.

[0058] This utility model also proposes a light-emitting device, including the light-emitting diode in the above embodiments.

[0059] In summary, the light-emitting diode in the above embodiments of this utility model, by providing a dielectric material layer 2 on the upper surface of the substrate 1, and the dielectric material layer 2 being composed of a plurality of frustums 21, makes the peeling interface between the substrate 1 and the epitaxial layer smoother, avoiding abnormal situations such as microcracks and peeling surface damage during the peeling of the substrate 1. Furthermore, the dielectric material layer 2 composed of a plurality of frustums 21 can also avoid the problem of low quantum efficiency of the flat epitaxial layer as the light-emitting surface.

[0060] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0061] The embodiments described above are merely illustrative of several implementations of this utility model, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of this utility model patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this utility model, and these all fall within the protection scope of this utility model. Therefore, the protection scope of this utility model patent should be determined by the appended claims.

Claims

1. A light-emitting diode, characterized in that, include: Substrate; Dielectric material layer; The dielectric material layer is disposed on the upper surface of the substrate and is composed of a plurality of frustums. The plurality of frustums are uniformly disposed on the upper surface of the substrate and are spaced apart. A number of LED chips are evenly disposed on the upper surface of the dielectric material layer, and the bottom of the LED chips is disposed corresponding to the frustum.

2. The light-emitting diode according to claim 1, characterized in that, The substrate is a sapphire substrate.

3. The light-emitting diode according to claim 1, characterized in that, The dielectric material layer is a silicon oxide heterolayer.

4. The light-emitting diode according to claim 1, characterized in that, The thickness of the dielectric material layer is 5. The light-emitting diode according to claim 1, characterized in that, The angle between the sidewall of the frustum and the substrate is 63°-78°.

6. The light-emitting diode according to claim 1, characterized in that, The bottom of the LED chip is provided with several grooves, and the grooves are configured to cooperate with the frustum.

7. The light-emitting diode according to claim 1, characterized in that, The perimeter of the LED chip is less than or equal to 200 μm.

8. A light-emitting device, characterized in that, Includes the light-emitting diode as described in any one of claims 1 to 7.

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