Display panel

Abstract

The utility model relates to a display panel. The display panel includes: a driving element layer including a pixel driving portion; a light emitting element disposed on the driving element layer, and including: a first electrode; an intermediate layer disposed on the first electrode; and a second electrode disposed on the intermediate layer. The display panel further includes: a pixel defining layer disposed on the driving element layer and including a light emitting opening and a groove surrounding the light emitting opening; and a connection electrode disposed on the pixel defining layer and electrically connected to the pixel driving portion and the second electrode.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2023-0162965, filed on November 22, 2023, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to a display panel with improved contact reliability. Background Technology

[0004] Multimedia electronic devices such as televisions, mobile phones, tablet computers, navigation devices, and gaming devices include display panels that display images. The display panel includes light-emitting elements and circuitry that drives these elements. The light-emitting elements included in the display panel emit light and produce an image in response to a voltage applied to them via the circuitry. Research is underway regarding the connections between the light-emitting elements and the circuitry to improve the reliability of the display panels.

[0005] It will be understood that this background section is intended to provide part of the useful background for understanding the art. However, this background section may also include ideas, concepts, or knowledge that were not known or understood by a person skilled in the art prior to the corresponding valid submission date of the subject matter disclosed herein. Utility Model Content

[0006] This disclosure provides a display panel with improved contact reliability.

[0007] This disclosure provides a method for manufacturing a display panel with improved contact reliability.

[0008] This disclosure provides a display panel that may include: a driving element layer including a pixel driving portion; a light-emitting element disposed on the driving element layer, the light-emitting element including: a first electrode; an intermediate layer disposed on the first electrode; and a second electrode disposed on the intermediate layer; a pixel defining layer disposed on the driving element layer, the pixel defining layer including a light-emitting opening and a groove surrounding the light-emitting opening; and a connecting electrode disposed on the pixel defining layer, the connecting electrode being electrically connected to the pixel driving portion and the second electrode.

[0009] The light-emitting opening exposes at least a portion of the first electrode. The light-emitting element includes a plurality of light-emitting elements. The pixel driving part includes a plurality of pixel driving parts. The connecting electrode includes a plurality of connecting electrodes. The plurality of connecting electrodes electrically connect the plurality of light-emitting elements to the plurality of pixel driving parts respectively. The gap between adjacent connecting electrodes among the plurality of connecting electrodes overlaps with the groove.

[0010] The light-emitting opening exposes at least a portion of the first electrode, and the connecting electrode includes: a first edge; and a second edge surrounding the first edge, and the second edge overlapping the groove.

[0011] The light-emitting opening exposes at least a portion of the first electrode, and in the region adjacent to the groove, the second electrode is electrically connected to the connecting electrode.

[0012] The light-emitting opening exposes at least a portion of the first electrode, the connecting electrode includes a pointed portion protruding from the end of the groove, and in a plan view, the connecting electrode overlaps with the groove of the pixel defining layer.

[0013] The second electrode is electrically connected to the connecting electrode at the tip portion.

[0014] A via is further defined through the pixel defining layer, and the connection electrode is electrically connected to the pixel driving unit through the via.

[0015] The connection electrode includes: a first connection electrode layer disposed on the pixel defining layer; and a second connection electrode layer disposed on the first connection electrode layer, wherein the second connection electrode layer covers the first connection electrode layer.

[0016] The intermediate layer is disposed on the second connecting electrode layer, the second electrode is disposed on the intermediate layer, and the second electrode is electrically connected to the second connecting electrode layer at the tip portion.

[0017] The display panel further includes: a first dividing pattern; a second dividing pattern; and a third dividing pattern, wherein the first dividing pattern, the second dividing pattern, and the third dividing pattern are disposed in the groove, and wherein the first dividing pattern is electrically connected to the third dividing pattern.

[0018] The light-emitting opening exposes at least a portion of the first electrode, the connection electrode includes a first connection electrode layer disposed on the pixel defining layer, and the intermediate layer covers the first connection electrode layer, wherein the display panel further includes: a first separation pattern; and a second separation pattern, wherein the first separation pattern and the second separation pattern are disposed in the groove.

[0019] The light-emitting opening exposes at least a portion of the first electrode. The pixel defining layer includes: a first pixel defining layer portion; and a second pixel defining layer portion disposed on the first pixel defining layer portion, the first pixel defining layer portion and the second pixel defining layer portion being integral, and the groove being defined in the second pixel defining layer portion.

[0020] Embodiments of this disclosure provide a display panel, which may include: a driving element layer including a pixel driving portion; a light-emitting element disposed on the driving element layer; a pixel defining layer disposed on the driving element layer, and the pixel defining layer including a groove formed by removing a portion of the pixel defining layer in the thickness direction of the pixel defining layer; and a connecting electrode disposed on the pixel defining layer, and the connecting electrode including a pointed tip portion protruding from the end of the groove.

[0021] The light-emitting element includes: a first electrode; an intermediate layer disposed on the first electrode; and a second electrode disposed on the intermediate layer. The pixel defining layer further includes a light-emitting opening that exposes at least a portion of the first electrode, and the groove surrounds the light-emitting opening.

[0022] The light-emitting element includes: a first electrode; an intermediate layer disposed on the first electrode; and a second electrode disposed on the intermediate layer, wherein the connecting electrode electrically connects the pixel driving portion to the second electrode, and the second electrode is electrically connected to the connecting electrode at the tip portion.

[0023] A via is defined through the pixel defining layer, and the connection electrode is electrically connected to the pixel driving unit through the via.

[0024] The light-emitting element includes multiple light-emitting elements, the pixel driving part includes multiple pixel driving parts, the connecting electrode includes multiple connecting electrodes, the multiple connecting electrodes electrically connect the multiple light-emitting elements to the multiple pixel driving parts respectively, and the gap between adjacent connecting electrodes among the multiple connecting electrodes overlaps with the groove.

[0025] The connection electrode includes: a first edge; and a second edge surrounding the first edge, wherein the second edge overlaps the groove.

[0026] The light-emitting element includes: a first electrode; an intermediate layer disposed on the first electrode; and a second electrode disposed on the intermediate layer. The connecting electrode includes: a first connecting electrode layer disposed on the pixel defining layer; and a second connecting electrode layer disposed on the first connecting electrode layer. The second connecting electrode layer covers the first connecting electrode layer, and the second electrode is electrically connected to the second connecting electrode layer at the tip portion.

[0027] The display panel further includes: a first dividing pattern; a second dividing pattern; and a third dividing pattern, wherein the first dividing pattern, the second dividing pattern, and the third dividing pattern are disposed in the groove, and the first dividing pattern is electrically connected to the third dividing pattern.

[0028] The light-emitting element includes: a first electrode; an intermediate layer disposed on the first electrode; and a second electrode disposed on the intermediate layer. The connecting electrode includes a first connecting electrode layer disposed on the pixel defining layer, and the intermediate layer covers the first connecting electrode layer. The display panel further includes: a first separating pattern; and a second separating pattern, wherein the first separating pattern and the second separating pattern are disposed in the groove.

[0029] The pixel defining layer includes: a first pixel defining layer portion; and a second pixel defining layer portion disposed on the first pixel defining layer portion, the first pixel defining layer portion and the second pixel defining layer portion being integral, and the groove being defined in the second pixel defining layer portion.

[0030] Embodiments of this disclosure provide a display panel, which may include: a driving element layer including a pixel driving portion; a light-emitting element disposed on the driving element layer, wherein the light-emitting element includes a first electrode, an intermediate layer disposed on the first electrode, and a second electrode disposed on the intermediate layer; a pixel defining layer disposed on the driving element layer, wherein the pixel defining layer includes a light-emitting opening exposing at least a portion of the first electrode and a groove surrounding the light-emitting opening; and a connecting electrode disposed on the pixel defining layer, wherein the connecting electrode is electrically connected to the pixel driving portion and the second electrode.

[0031] The light-emitting element may include multiple light-emitting elements, the pixel driving unit may include multiple pixel driving units, and the connecting electrode may include multiple connecting electrodes. The multiple connecting electrodes can electrically connect the multiple light-emitting elements to the multiple pixel driving units respectively. The gap between adjacent connecting electrodes among the multiple connecting electrodes may overlap with the groove.

[0032] The connection electrode may include a first edge and a second edge surrounding the first edge, and the second edge may overlap with the groove.

[0033] In the region adjacent to the groove, the second electrode can be electrically connected to the connection electrode.

[0034] The connection electrode may include a pointed portion protruding from the end of the groove, and in a plan view, the connection electrode may overlap with the groove of the pixel defining layer.

[0035] The second electrode may be electrically connected to the connecting electrode at the tip portion.

[0036] A via can be further defined through the pixel defining layer, and the connection electrode can be electrically connected to the pixel driving unit through the via.

[0037] The connection electrode may include: a first connection electrode layer disposed on the pixel defining layer; and a second connection electrode layer disposed on the first connection electrode layer, wherein the second connection electrode layer may cover the first connection electrode layer.

[0038] The intermediate layer may be disposed on the second connecting electrode layer, the second electrode may be disposed on the intermediate layer, and the second electrode may be electrically connected to the second connecting electrode layer at the tip portion.

[0039] The display panel may further include a first separating pattern, a second separating pattern, and a third separating pattern. The first separating pattern and the second connecting electrode layer may contain the same material, the second separating pattern and the intermediate layer may contain the same material, and the third separating pattern and the second electrode may contain the same material. The first separating pattern, the second separating pattern, and the third separating pattern may be disposed in the groove.

[0040] The first dividing pattern can be electrically connected to the third dividing pattern.

[0041] The connection electrode may include a first connection electrode layer disposed on the pixel defining layer, and the intermediate layer may cover the first connection electrode layer.

[0042] The display panel may further include a first separating pattern and a second separating pattern. The first separating pattern and the intermediate layer may include the same material, and the second separating pattern and the second electrode may include the same material. The first separating pattern and the second separating pattern may be disposed in the groove.

[0043] The pixel defining layer may include a first pixel defining layer portion and a second pixel defining layer portion disposed on the first pixel defining layer portion. The first pixel defining layer portion may be integral with the second pixel defining layer portion, and the groove may be defined in the second pixel defining layer portion.

[0044] Embodiments of this disclosure provide a display panel, which may include: a driving element layer including a pixel driving portion; and a light-emitting element disposed on the driving element layer, wherein the light-emitting element includes a first electrode, an intermediate layer disposed on the first electrode, and a second electrode disposed on the intermediate layer. The display panel may further include: a pixel defining layer disposed on the driving element layer, wherein the pixel defining layer includes a groove formed by removing a portion of the pixel defining layer in the thickness direction; and a connecting electrode disposed on the pixel defining layer, wherein the connecting electrode includes a pointed tip protruding from the end of the groove.

[0045] The pixel defining layer may further include a light-emitting opening that exposes at least a portion of the first electrode, and the groove may surround the light-emitting opening.

[0046] The connecting electrode can electrically connect the pixel driving part to the second electrode, and the second electrode can be electrically connected to the connecting electrode at the tip.

[0047] A through-hole can be defined through the pixel defining layer, and the connection electrode can be electrically connected to the pixel driving unit through the through-hole.

[0048] The light-emitting element may include multiple light-emitting elements, the pixel driving unit may include multiple pixel driving units, and the connecting electrode may include multiple connecting electrodes. The multiple connecting electrodes can electrically connect the multiple light-emitting elements to the multiple pixel driving units respectively. The gap between adjacent connecting electrodes among the multiple connecting electrodes may overlap with the groove.

[0049] The connection electrode may include a first edge and a second edge surrounding the first edge, and the second edge may overlap with the groove.

[0050] The connection electrode may include: a first connection electrode layer disposed on the pixel defining layer; and a second connection electrode layer disposed on the first connection electrode layer. The second connection electrode layer may cover the first connection electrode layer, and the second electrode may be electrically connected to the second connection electrode layer at the tip portion.

[0051] The display panel may further include a first separating pattern, a second separating pattern, and a third separating pattern. The first separating pattern and the second connecting electrode layer may contain the same material, the second separating pattern and the intermediate layer may contain the same material, and the third separating pattern and the second electrode may contain the same material. The first separating pattern, the second separating pattern, and the third separating pattern may be disposed in the groove, and the first separating pattern may be electrically connected to the third separating pattern.

[0052] The connection electrode may include a first connection electrode layer disposed on the pixel defining layer, and the intermediate layer may cover the first connection electrode layer.

[0053] The display panel may further include a first separating pattern and a second separating pattern. The first separating pattern and the intermediate layer may include the same material, and the second separating pattern and the second electrode may include the same material. The first separating pattern and the second separating pattern may be disposed in the groove.

[0054] The pixel defining layer may include a first pixel defining layer portion and a second pixel defining layer portion disposed on the first pixel defining layer portion. The first pixel defining layer portion may be integral with the second pixel defining layer portion, and the groove may be defined in the second pixel defining layer portion.

[0055] Embodiments of this disclosure provide a method for manufacturing a display panel. The method may include: preparing a preliminary display panel, the preliminary display panel including a substrate layer, a driving element layer disposed on the substrate layer, and a pixel defining layer disposed on the driving element layer. The method may further include: depositing a first connection electrode layer on the preliminary display panel; etching a portion of the first connection electrode layer and a portion of the pixel defining layer to form a groove in the pixel defining layer overlapping at least a portion of the first connection electrode layer; etching the first connection electrode layer to form a connection electrode; and forming an intermediate layer and a cathode on the connection electrode and the pixel defining layer.

[0056] The method may further include forming a pointed portion at the end of the first connecting electrode layer.

[0057] The method may further include: depositing a second connection electrode layer on the first connection electrode layer; and forming tip portions at the ends of the first connection electrode layer and the second connection electrode layer. Forming the connection electrode may include etching the second connection electrode layer.

[0058] The pixel defining layer may include a first pixel defining layer portion and a second pixel defining layer portion disposed on the first pixel defining layer portion. The first pixel defining layer portion may be integral with the second pixel defining layer portion, and the groove may be defined in the second pixel defining layer portion.

[0059] Based on the above description, the light-emitting element and the pixel driving unit can be stably contacted each other, thus improving the contact reliability between them. As an example, since the connecting electrodes can be electrically connected to the cathode of the light-emitting element and the pixel driving unit over a relatively wide area rather than at a specific point, contact reliability can be enhanced. Therefore, external defects caused by contact defects (e.g., spots detected during illumination) can be reduced or eliminated. Consequently, the display quality and manufacturing yield of the display panel can be improved.

[0060] Furthermore, the lower surface of the connecting electrode and the upper surface of the intermediate connecting electrode can contact each other, improving contact reliability. Therefore, the size of the through-hole through which the connecting electrode connects to the intermediate connecting electrode can be reduced or minimized. Consequently, the size of the light-emitting portion and the resolution of the display panel can be increased.

[0061] Furthermore, the connecting electrode includes a pointed portion, and therefore, each of the intermediate layer and the second electrode can be separated at each pixel. This prevents lateral leakage current between adjacent pixels, and consequently prevents color mixing and brightness degradation between adjacent pixels. Attached Figure Description

[0062] The above and other advantages of this disclosure will become apparent when considered in conjunction with the accompanying drawings, and by referring to the following detailed description, in which:

[0063] Figure 1 This is a schematic block diagram of a display device according to an embodiment of the present disclosure;

[0064] Figures 2A to 2C This is a schematic diagram of the equivalent circuit of a pixel according to an embodiment of the present disclosure;

[0065] Figure 3A and Figure 3B This is a schematic plan view of a display panel according to an embodiment of the present disclosure;

[0066] Figures 4A to 4D This is an enlarged schematic plan view of some areas of a display panel according to an embodiment of the present disclosure;

[0067] Figure 5 This is a schematic cross-sectional view of a display panel according to an embodiment of the present disclosure;

[0068] Figure 6AThis is an enlarged schematic cross-sectional view of an area of ​​a display panel according to an embodiment of the present disclosure;

[0069] Figure 6B This is an enlarged schematic plan view of an area of ​​a display panel according to an embodiment of the present disclosure;

[0070] Figure 6C This is an enlarged schematic cross-sectional view of an area of ​​a display panel according to an embodiment of the present disclosure;

[0071] Figure 7 This is an enlarged schematic cross-sectional view of an area of ​​a display panel according to an embodiment of the present disclosure;

[0072] Figure 8 This is an enlarged schematic cross-sectional view of an area of ​​a display panel according to an embodiment of the present disclosure;

[0073] Figure 9 This is an enlarged schematic cross-sectional view of an area of ​​a display panel according to an embodiment of the present disclosure;

[0074] Figures 10A to 10F This is a schematic cross-sectional view illustrating the process of manufacturing a display panel according to an embodiment of the present disclosure;

[0075] Figures 11A to 11C This is a schematic cross-sectional view illustrating the process of manufacturing a display panel according to an embodiment of the present disclosure;

[0076] Figures 12A to 12F This is a schematic cross-sectional view illustrating the process of manufacturing a display panel according to an embodiment of the present disclosure; and

[0077] Figures 13A to 13C This is a schematic cross-sectional view illustrating the process of manufacturing a display panel according to an embodiment of the present disclosure. Detailed Implementation

[0078] This disclosure will now be described more fully below with reference to the accompanying drawings, in which embodiments are illustrated. However, this disclosure may be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art.

[0079] In this disclosure, it will be understood that when an element or layer (or region, portion) is referred to as being "on", "connected to", or "coupled to" another element or layer, the element or layer may be directly on, directly connected to, or directly coupled to the other element or layer, or there may be an intermediary element or layer.

[0080] The same reference numerals always refer to the same elements. In the drawings, for the purpose of effectively describing the technical content, the thickness, scale, and dimensions of components may be exaggerated. As used herein, the term "and / or" can include any and all combinations of one or more of the associated listed items. For example, "A and / or B" can be understood to mean "A, B, or A and B". The terms "and" and "or" can be used in a conjunctional or disjunctive sense and can be understood as equivalent to "and / or".

[0081] In the specification and claims, for purposes of meaning and interpretation, the phrase “at least one of…” is intended to include the meaning of “at least one of the group consisting of…”. For example, “at least one of A and B” can be understood to mean “A, B, or A and B”.

[0082] It will be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. Therefore, without departing from the teachings of this disclosure, the first element discussed below may be referred to as the second element. As used herein, unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” are also intended to include the plural forms.

[0083] For ease of description, spatial relative terms such as “below,” “under,” “down,” “above,” and “above” may be used in this document to describe the relationship between one element or feature and another element or feature as shown in the figure.

[0084] It will also be understood that when the terms “comprises,” “has,” “have,” “having,” and “include,” etc., are used in this specification, it indicates the presence of the stated features, wholes, steps, operations, elements, and / or components, but does not preclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or groups thereof.

[0085] The term “overlap” or “overlapping with” means that the first object may be above, below, or to the side of the second object, and vice versa. Additionally, the term “overlap” may include layering, stacking, facing or confronting, extending over (over), covering or partially covering, or any other suitable term that will be understood and appreciated by one of ordinary skill in the art.

[0086] Unless otherwise defined or implied, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that, unless expressly defined herein, terms (such as those defined in a general dictionary) shall be interpreted as having the meaning consistent with their meaning in the context of the relevant field and shall not be interpreted in an idealized or overly formalized sense.

[0087] Figure 1 This is a schematic block diagram of a display device DD according to an embodiment of the present disclosure.

[0088] refer to Figure 1 The display device DD may include a display panel DP, panel drivers SDC, EDC, and DDC, a power supply unit PWS, and a timing controller TC. The display panel DP may be a light-emitting display panel. The light-emitting display panel may be an organic light-emitting display panel, an inorganic light-emitting display panel, or a quantum dot light-emitting display panel. In the following description, an organic light-emitting display panel will be used as a representative example of a display panel DP. The panel drivers SDC, EDC, and DDC may include a scan driver SDC, an emitter driver EDC, and a data driver DDC.

[0089] The display panel DP may include scan lines GWL1 to GWLn, GCL1 to GCLn, GIL1 to GILn, GBL1 to GBLn and GRL1 to GRLn, emission lines ESL1 to ESLn and data lines DL1 to DLm. The display panel DP may include pixels connected to scan lines GWL1 to GWLn, GCL1 to GCLn, GIL1 to GILn, GBL1 to GBLn and GRL1 to GRLn, emission lines ESL1 to ESLn and data lines DL1 to DLm. Each of “m” and “n” is an integer greater than or equal to 1.

[0090] As an example, a pixel PXij (where “i” is an integer greater than or equal to 1 and less than or equal to “n”, and “j” is an integer greater than or equal to 1 and less than or equal to “m”) positioned to correspond to the i-th horizontal line (or the i-th pixel row) and the j-th vertical line (or the j-th pixel column) can be connected to the i-th first scan line (or write scan line) GWLi, the i-th second scan line (or compensation scan line) GCLi, the i-th third scan line (or first initialization scan line) GILi, the i-th fourth scan line (or second initialization scan line) GBLi, the i-th fifth scan line (or reset scan line) GRLi, the j-th data line DLj, and the i-th transmit line ESLi.

[0091] Pixel PXij may include a light-emitting element, a transistor, and a capacitor. Pixel PXij may receive a first power voltage VDD, a second power voltage VSS, a third power voltage (or reference voltage) VREF, a fourth power voltage (or first initialization voltage) VINT1, a fifth power voltage (or second initialization voltage) VINT2, and a sixth power voltage (or compensation voltage) VCOMP from the power supply unit PWS.

[0092] The first power voltage VDD and the second power voltage VSS can have voltage values ​​set to allow current to flow through the light-emitting element, and thus light can be emitted from the light-emitting element. As an example, the first power voltage VDD can be set to a voltage level that is higher than the second power voltage VSS.

[0093] The third power voltage VREF can be a voltage used to initialize the gate of the driving transistor included in pixel PXij. Utilizing the voltage difference between the third power voltage VREF and the data signal, the third power voltage VREF can be used to achieve a predetermined or selected grayscale level. Therefore, the third power voltage VREF can be set to a predetermined or selected voltage within the voltage range of the data signal.

[0094] A fourth power voltage VINT1 can be used to initialize the capacitor included in pixel PXij. The fourth power voltage VINT1 can be set to a voltage level lower than the third power voltage VREF. As an example, the fourth power voltage VINT1 can be set to a voltage level lower than the voltage difference between the third power voltage VREF and the threshold voltage of the driving transistor; however, this disclosure should not be limited thereto or thereby restricted.

[0095] The fifth power voltage VINT2 can be used to initialize the cathode of the light-emitting element included in pixel PXij. The fifth power voltage VINT2 can be set to a voltage level lower than the first power voltage VDD or the fourth power voltage VINT1, or it can be set to a voltage level similar to or the same as the third power voltage VREF; however, the embodiment should not be limited thereto or thereby restricted. The fifth power voltage VINT2 can be set to a voltage level similar to or the same as the first power voltage VDD.

[0096] When the threshold voltage of the driving transistor is compensated, the sixth power voltage VCOMP can provide a predetermined or selected current to the driving transistor.

[0097] Figure 1The diagram illustrates a structure in which all the first power voltages VDD, second power voltage VSS, third power voltage VREF, fourth power voltage VINT1, fifth power voltage VINT2, and sixth power voltage VCOMP are supplied from the power supply unit PWS. However, this disclosure should not be limited thereto or thereby restricted. As an example, regardless of the structure of pixel PXij, both the first power voltage VDD and the second power voltage VSS can be provided, and depending on the structure of pixel PXij, at least one of the third power voltage VREF, fourth power voltage VINT1, fifth power voltage VINT2, and sixth power voltage VCOMP may not be provided.

[0098] According to this disclosure, the signal lines connected to the pixel PXij can be designed in various ways by taking into account the structure of the pixel PXij.

[0099] The scan driver SDC can receive a first control signal SCS from the timing controller TC, and can provide scan signals to the first scan lines GWL1 to GWLn, the second scan lines GCL1 to GCLn, the third scan lines GIL1 to GILn, the fourth scan lines GBL1 to GBLn, and the fifth scan lines GRL1 to GRLn in response to the first control signal SCS.

[0100] The scan signal can be configured to have a voltage that allows the transistor to turn on in response to the scan signal. As an example, the scan signal provided to a P-type transistor can be configured to have a logic low level, and the scan signal provided to an N-type transistor can be configured to have a logic high level. In the following text, the phrase "provide a scan signal" may mean providing a scan signal having a logic level that turns the transistor on to the transistor controlled by that scan signal.

[0101] For ease of explanation, Figure 1 A scan driver SDC is shown; however, this disclosure should not be limited thereto or thereby restricted. According to an embodiment, the display device DD may include a plurality of scan drivers to provide scan signals to first scan lines GWL1 to GWLn, second scan lines GCL1 to GCLn, third scan lines GIL1 to GILn, fourth scan lines GBL1 to GBLn, and fifth scan lines GRL1 to GRLn.

[0102] The transmit driver EDC can provide transmit signals to transmit lines ESL1 to ESLn in response to the second control signal ECS. As an example, the transmit signals can be provided sequentially to transmit lines ESL1 to ESLn.

[0103] Each transistor connected to emitter lines ESL1 to ESLn can be an N-type transistor. The emitter signal provided to emitter lines ESL1 to ESLn can have a gate turn-on voltage. The transistor receiving the emitter signal can be turned on when the emitter signal is received, and can be turned off under other conditions.

[0104] The second control signal ECS may include a transmit start signal and a clock signal, and the transmit driver EDC may be implemented by a shift register that uses the clock signal to sequentially shift the pulse-shaped transmit start signal to sequentially generate and output pulse-shaped transmit signals.

[0105] The data driver DDC can receive the third control signal DCS and image data RGB from the timing controller TC. The data driver DDC can convert the digital image data RGB into an analog data signal. The data driver DDC can provide data signals to data lines DL1 to DLm in response to the third control signal DCS.

[0106] The third control signal DCS may include a data enable signal, a horizontal start signal, and a data clock signal to indicate the output of a valid data signal. As an example, the data driver DDC may include a shift register that shifts the horizontal start signal in sync with the data clock signal to generate a sampled signal, a latch that latches image data RGB in response to the sampled signal, a digital-to-analog converter (or decoder) that converts the latched image data RGB (e.g., digital data) into an analog data signal, and a buffer (or amplifier) ​​that outputs the data signal to data lines DL1 to DLm.

[0107] The power supply unit PWS can provide the display panel DP with a first power voltage VDD, a second power voltage VSS, and a third power voltage VREF to drive the pixel PXij. Furthermore, the power supply unit PWS can provide the display panel DP with at least one of a fourth power voltage VINT1, a fifth power voltage VINT2, and a sixth power voltage VCOMP.

[0108] As an example, the power supply unit PWS can be transmitted via a method not in... Figure 1 The first power line VDL shown in the figure (reference) Figure 2A ), Second power line VSL (reference) Figure 2A ), Third power line (or reference voltage line) VRL (reference) Figure 2A ), Fourth power line (or first initialization voltage line) VIL1 (reference) Figure 2A ), Fifth power line (or second initialization voltage line) VIL2 (reference) Figure 2A ) and the sixth power line (or compensating voltage line) VCL (reference) Figure 2AThe first power voltage VDD, the second power voltage VSS, the third power voltage VREF, the fourth power voltage VINT1, the fifth power voltage VINT2, and the sixth power voltage VCOMP are respectively supplied to the display panel DP.

[0109] The power supply unit PWS can be implemented by a power management integrated circuit (IC); however, this disclosure should not be limited thereto or thereby restricted.

[0110] The timing controller TC can generate a first control signal SCS, a second control signal ECS, a third control signal DCS, and a fourth control signal PCS based on the input image data IRGB, a synchronization signal Sync (e.g., vertical synchronization signal, horizontal synchronization signal, etc.), a data enable signal DE, and a clock signal. The first control signal SCS can be applied to the scan driver SDC, the second control signal ECS can be applied to the transmit driver EDC, the third control signal DCS can be applied to the data driver DDC, and the fourth control signal PCS can be applied to the power supply unit PWS. The timing controller TC can rearrange the input image data IRGB to correspond to the arrangement of pixels PXij in the display panel DP, and can generate image data RGB (or frame data).

[0111] The scan driver SDC, transmit driver EDC, data driver DDC, power supply unit PWS, and / or timing controller TC can be directly formed in the display panel DP, or can be manufactured in a separate driver chip and then connected to the display panel DP. Alternatively, at least two of the scan driver SDC, transmit driver EDC, data driver DDC, power supply unit PWS, and timing controller TC can be provided in a single driver chip. As an example, the data driver DDC and timing controller TC can be provided in a single driver chip.

[0112] Although referenced in the above description Figure 1 A display device DD according to an embodiment has been described, but the display device DD of this disclosure should not be limited thereto or thereby restricted. Signal lines can be added or omitted depending on the structure of the pixels. Furthermore, the connection relationship between a pixel and a signal line can be changed. If one of the signal lines is omitted, it can be replaced with another signal line.

[0113] Figure 2A , Figure 2B and Figure 2C This is a schematic diagram of the equivalent circuit of pixels PXij, PXij-1 and PXij-2 according to embodiments of the present disclosure. Figure 2A , Figure 2B and Figure 2CThe equivalent circuit diagram of pixels PXij, PXij-1 and PXij-2 is shown. Pixels PXij, PXij-1 and PXij-2 are connected to the i-th first scan line GWLi (hereinafter referred to as the write scan line GWLi) and the j-th data line DLj (hereinafter referred to as the data line DLj).

[0114] refer to Figure 2A Pixel PXij may include a light-emitting element (LD) and a pixel driving unit (PDC). The light-emitting element (LD) may be connected to a first power line (VDL) and the pixel driving unit (PDC).

[0115] The pixel driving unit (PDC) can be connected to scan lines GWLi, GCLi, GILi, GBLi, and GRLi, data line DLj, the i-th emitter line ESLi, and power lines VDL, VSL, VIL1, VIL2, VRL, and VCL. The PDC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and an eighth transistor T8, a first capacitor C1, and a second capacitor C2. In the following description, each of the first transistor T1, second transistor T2, third transistor T3, fourth transistor T4, fifth transistor T5, sixth transistor T6, seventh transistor T7, and eighth transistor T8 will be described as an N-type transistor; however, this disclosure should not be limited thereto. According to embodiments, some of the first transistors T1 to the eighth transistor T8 may be N-type transistors, and the other transistors may be P-type transistors, or each of the first transistors T1 to the eighth transistor T8 may be a P-type transistor, and this disclosure should not be particularly limited.

[0116] The gate of the first transistor T1 can be connected to the first node N1. The first electrode of the first transistor T1 can be connected to the second node N2, and the second electrode of the first transistor T1 can be connected to the third node N3. The first transistor T1 can be a driving transistor. The first transistor T1 can control the driving current ILD flowing from the first power line VDL to the second power line VSL via the light-emitting element LD in response to the voltage of the first node N1. The first power voltage VDD can be set to a voltage having a potential higher than the potential of the second power voltage VSS.

[0117] In this disclosure, the phrase "transistor connected to a signal line" means that one of the source, drain, and gate electrodes of the transistor is integrally provided with or connected to the signal line via a connection electrode. Conversely, the phrase "one transistor electrically connected to another transistor" means that one of the source, drain, and gate electrodes of the one transistor is integrally provided with or connected to one of the source, drain, and gate electrodes of the other transistor via a connection electrode.

[0118] The second transistor T2 may include a gate connected to the write scan line GWLi, a first electrode connected to the data line DLj, and a second electrode connected to the first node N1. The second transistor T2 can provide a data signal DATA to the first node N1 in response to a write scan signal GW applied to it via the write scan line GWLi. When the write scan signal GW is applied to the second transistor T2 via the write scan line GWLi, the second transistor T2 can be turned on, and therefore, the data line DLj can be electrically connected to the first node N1.

[0119] A third transistor T3 can be connected between the first node N1 and the reference voltage line VRL. The first electrode of the third transistor T3 can receive a reference voltage VREF via the reference voltage line VRL, and the second electrode of the third transistor T3 can be connected to the first node N1. In an embodiment, the gate of the third transistor T3 can receive a reset scan signal GR via the i-th fifth scan line GRLi (hereinafter referred to as the reset scan line GRLi). The third transistor T3 can be turned on when the reset scan signal GR is applied to it via the reset scan line GRLi, and can provide the reference voltage VREF to the first node N1.

[0120] A fourth transistor T4 can be connected between the third node N3 and the first initialization voltage line VIL1. The first electrode of the fourth transistor T4 can be connected to the third node N3, and the second electrode of the fourth transistor T4 can be connected to the first initialization voltage line VIL1 through which the first initialization voltage VINT1 is provided. The fourth transistor T4 can be referred to as the first initialization transistor. The gate of the fourth transistor T4 can receive the first initialization scan signal GI via the i-th third scan line GILi (hereinafter referred to as the first initialization scan line GILi). The fourth transistor T4 can be turned on when the first initialization scan signal GI is provided to it via the first initialization scan line GILi, and can provide the first initialization voltage VINT1 to the third node N3.

[0121] A fifth transistor T5 can be connected between the compensation voltage line VCL and the second node N2. The first electrode of the fifth transistor T5 can receive the compensation voltage VCOMP via the compensation voltage line VCL, and the second electrode of the fifth transistor T5 can be connected to the second node N2 to be electrically connected to the first electrode of the first transistor T1. The gate of the fifth transistor T5 can receive the compensation scan signal GC via the i-th second scan line GCLi (hereinafter referred to as the compensation scan line GCLi). The fifth transistor T5 can be turned on when the compensation scan signal GC is provided to it via the compensation scan line GCLi, and can provide the compensation voltage VCOMP to the second node N2, thus compensating the threshold voltage of the first transistor T1 during the compensation period.

[0122] A sixth transistor T6 can be connected between the first transistor T1 and the light-emitting element LD. Specifically, the gate of the sixth transistor T6 can receive the emission signal EM via the i-th emission line ESLi (hereinafter referred to as emission line ESLi). The first electrode of the sixth transistor T6 can be connected to the cathode of the light-emitting element LD via the fourth node N4, and the second electrode of the sixth transistor T6 can be connected to the first electrode of the first transistor T1 via the second node N2. The sixth transistor T6 can be referred to as the first emission control transistor. The sixth transistor T6 can be turned on when the emission signal EM is supplied to it via the emission line ESLi, and therefore, the light-emitting element LD can be electrically connected to the first transistor T1.

[0123] A seventh transistor T7 can be connected between the second power line VSL and the third node N3. The first electrode of the seventh transistor T7 can be connected to the second electrode of the first transistor T1 via the third node N3, and the second electrode of the seventh transistor T7 can receive a second power voltage VSS via the second power line VSL. The gate of the seventh transistor T7 can be electrically connected to the emitter line ESLi. The seventh transistor T7 can be referred to as the second emitter control transistor. The seventh transistor T7 can be turned on when an emitter signal EM is provided to it via the emitter line ESLi, and therefore, the second electrode of the first transistor T1 can be electrically connected to the second power line VSL.

[0124] According to an embodiment, the sixth transistor T6 and the seventh transistor T7 can be connected to the same emitter line ESLi and can be turned on in response to the same emitter signal EM; however, this is merely an example. According to an embodiment, the sixth transistor T6 and the seventh transistor T7 can be turned on independently in response to different signals that are distinct from each other. Additionally, according to an embodiment, either the sixth transistor T6 or the seventh transistor T7 can be omitted from the pixel driving unit PDC.

[0125] The eighth transistor T8 can be connected between the second initialization voltage line VIL2 and the fourth node N4. That is, the eighth transistor T8 may include a gate connected to the i-th fourth scan line GBLi (hereinafter referred to as the second initialization scan line GBLi), a first electrode connected to the second initialization voltage line VIL2, and a second electrode connected to the fourth node N4. The eighth transistor T8 may be referred to as the second initialization transistor. The eighth transistor T8 can provide a second initialization voltage VINT2 to the fourth node N4 corresponding to the cathode of the light-emitting element LD in response to the second initialization scan signal GB applied to it via the second initialization scan line GBLi. The cathode of the light-emitting element LD can be initialized by the second initialization voltage VINT2.

[0126] According to an embodiment, some of the transistors, including the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8, can be turned on substantially simultaneously in response to the same scan signal. As an example, the eighth transistor T8 and the fifth transistor T5 can be turned on substantially simultaneously in response to the same scan signal. As an example, the eighth transistor T8 and the fifth transistor T5 can operate in response to the same compensation scan signal GC. The eighth transistor T8 and the fifth transistor T5 can be turned on and off substantially simultaneously in response to the same compensation scan signal GC. The compensation scan line GCLi and the second initialization scan line GBLi can be provided substantially as a single scan line. Therefore, the initialization of the cathode of the light-emitting element LD and the compensation of the threshold voltage of the first transistor T1 can be performed simultaneously. However, this disclosure should not be limited thereto or thereby restricted.

[0127] Furthermore, according to this disclosure, the initialization of the cathode of the light-emitting element LD and the compensation of the threshold voltage of the first transistor T1 can be performed in response to the same power voltage. As an example, the compensation voltage line VCL and the second initialization voltage line VIL2 can be essentially provided as a single power line. The initialization operation of the cathode and the compensation operation of the driving transistor can be performed using a single power voltage, and therefore, the design of the driver can be simplified. However, this is merely an example, and this disclosure should not be considered particularly limiting.

[0128] A first capacitor C1 can be positioned between the first node N1 and the third node N3. The first capacitor C1 can be charged with a voltage corresponding to the difference between the voltage at the first node N1 and the voltage at the third node N3. The first capacitor C1 can be referred to as a storage capacitor.

[0129] A second capacitor C2 can be disposed between the third node N3 and the second electric field line VSL. That is, one electrode of the second capacitor C2 can be connected to the second electric field line VSL that receives the second electric field voltage VSS, and the other electrode of the second capacitor C2 can be connected to the third node N3. The second capacitor C2 can be charged with a charge corresponding to the voltage difference between the second electric field voltage VSS and the voltage at the third node N3. The second capacitor C2 can be referred to as a holding capacitor. Compared to the first capacitor C1, the second capacitor C2 can have a higher storage capacity. Therefore, the second capacitor C2 can reduce the voltage change at the third node N3 caused by the voltage change at the first node N1.

[0130] In one embodiment, the light-emitting element (LD) can be connected to the pixel driving unit (PDC) via a fourth node N4. The LD may include an anode connected to the first power line VDL and a cathode opposite the anode. In another embodiment, the LD can be connected to the PDC via its cathode. That is, according to pixel PXij, the connection node where the LD connects to the PDC can be the fourth node N4, and the fourth node N4 can correspond to the connection node between the first electrode of the sixth transistor T6 and the cathode of the LD. Therefore, the potential of the fourth node N4 can correspond to the potential of the cathode of the LD.

[0131] In detail, the anode of the light-emitting element (LD) can be connected to the first power line VDL, a first power voltage VDD as a constant voltage can be applied to the anode, and the cathode can be electrically connected to the first transistor T1 via the sixth transistor T6. That is, in embodiments where each of the first transistors T1 to the eighth transistor T8 is an N-type transistor, the potential of the third node N3 corresponding to the source of the first transistor T1 is not directly affected by the characteristics of the light-emitting element (LD). Therefore, even if the characteristics of the light-emitting element (LD) deteriorate, the impact of the deterioration on the gate-source voltage (Vgs) of the transistors (especially the driving transistors) constituting the pixel driving unit (PDC) can be reduced. In other words, since the change in the amount of driving current ILD caused by the deterioration of the light-emitting element (LD) can be reduced, image retention defects in the display panel caused by increased usage time can be reduced, and the lifespan of the display panel can be improved.

[0132] like Figure 2B As shown, pixel PXij-1 may include a pixel driving unit PDC-1, which includes two transistors T1 and T2 and a first capacitor C1. Pixel driving unit PDC-1 may be connected to a light-emitting element LD, a write scan line GWLi, a data line DLj, and a second power line VSL. Figure 2BThe pixel driving unit PDC-1 shown can have the same characteristics as that obtained from... Figure 2A The circuit configuration shown is the circuit configuration obtained by removing the third transistor T3 to the eighth transistor T8 and the second capacitor C2 from the pixel driving unit PDC.

[0133] Each of the first transistor T1 and the second transistor T2 can be an N-type transistor or a P-type transistor. In this embodiment, each of the first transistor T1 and the second transistor T2 will be described as an N-type transistor.

[0134] The first transistor T1 may include a gate connected to a first node N1, a first electrode connected to a second node N2, and a second electrode connected to a third node N3. The second node N2 may be connected to a first power line VDL, and the third node N3 may be connected to a second power line VSL. The first transistor T1 may be connected to a light-emitting element LD via the second node N2, and may be connected to the second power line VSL via the third node N3. The first transistor T1 may be a driving transistor.

[0135] The second transistor T2 may include a gate for receiving a write scan signal GW via a write scan line GWLi, a first electrode connected to a data line DLj, and a second electrode connected to a first node N1. The second transistor T2 may provide a data signal DATA to the first node N1 in response to the write scan signal GW applied to it via the write scan line GWLi.

[0136] The first capacitor C1 may include an electrode connected to the first node N1 and an electrode connected to the third node N3. The first capacitor C1 may be charged with a voltage corresponding to the data signal DATA applied to the first node N1.

[0137] The light-emitting element (LD) may include an anode and a cathode. In one embodiment, the anode of the LD may be connected to a first power line VDL, and the cathode of the LD may be connected to a pixel driving unit PDC-1 via a second node N2. In another embodiment, the cathode of the LD may be connected to a first transistor T1. The LD may emit light in response to the amount of current flowing through the first transistor T1 of the pixel driving unit PDC-1.

[0138] In embodiments where each of the first transistor T1 and the second transistor T2 is an N-type transistor, the cathode of the light-emitting element LD is connected to the second node N2 where the pixel driving unit PDC-1 is located, which can correspond to the drain of the first transistor T1. That is, changes in the gate-source voltage (Vgs) of the first transistor T1 caused by the light-emitting element LD can be prevented. Therefore, changes in the amount of drive current ILD due to degradation of the light-emitting element LD can be reduced, image retention defects in the display panel caused by increased usage time can be reduced, and the lifespan of the display panel can be improved.

[0139] refer to Figure 2C Pixel PXij-2 may include a pixel driving unit PDC-2, which includes six transistors T1, T2, T3, T4a, T5a and T6a and two capacitors C1 and C2.

[0140] The pixel driving unit PDC-2 can be connected to the light-emitting element LD, the write scan line GWLi, the reset scan line GRLi, the compensation scan line GCLi, the i-th first emitter line ESL1i (hereinafter referred to as the first emitter line ESL1i), the i-th second emitter line ESL2i (hereinafter referred to as the second emitter line ESL2i), the data line DLj, the first power line VDL, the second power line VSL, the third power line VRL, and the initialization voltage line VIL.

[0141] Figure 2C The pixel driving unit PDC-2 shown can have the same characteristics as that obtained from... Figure 2A The circuit configuration obtained by removing the fourth transistor T4 and the fifth transistor T5 from the pixel driving unit PDC shown is similar to the circuit configuration obtained by the pixel driving unit PDC-2. Because the pixel driving unit PDC-2 has a smaller... Figure 2A The area of ​​the pixel driving unit PDC shown is large enough to make it easier to achieve high resolution.

[0142] Each of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4a, the fifth transistor T5a, and the sixth transistor T6a can be an N-type transistor or a P-type transistor. In an embodiment, as a representative example, each of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4a, the fifth transistor T5a, and the sixth transistor T6a will be described as an N-type transistor.

[0143] The first transistor T1 may include a gate connected to a first node N1, a first electrode connected to a second node N2, and a second electrode connected to a third node N3. The second node N2 may be connected to a first power line VDL, and the third node N3 may be connected to a second power line VSL. The first transistor T1 may be connected to a light-emitting element LD via the second node N2, and may be connected to the second power line VSL via the third node N3. The first transistor T1 may be a driving transistor.

[0144] The second transistor T2 may include a gate for receiving a write scan signal GW via a write scan line GWLi, a first electrode connected to a data line DLj, and a second electrode connected to a first node N1. The second transistor T2 may provide a data signal DATA to the first node N1 in response to the write scan signal GW applied to it via the write scan line GWLi.

[0145] A third transistor T3 can be connected between the first node N1 and the reference voltage line VRL. The first electrode of the third transistor T3 can receive a reference voltage VREF via the reference voltage line VRL, and the second electrode of the third transistor T3 can be connected to the first node N1. In an embodiment, the gate of the third transistor T3 can receive a reset scan signal GR via the reset scan line GRLi. The third transistor T3 can be turned on when the reset scan signal GR is applied to it via the reset scan line GRLi, and can provide the reference voltage VREF to the first node N1.

[0146] A fourth transistor T4a can be connected between the first transistor T1 and the light-emitting element LD. Specifically, the gate of the fourth transistor T4a can receive a first emission signal EM1 via the first emission line ESL1i. The first electrode of the fourth transistor T4a can be connected to the cathode of the light-emitting element LD via the fourth node N4, and the second electrode of the fourth transistor T4a can be connected to the first electrode of the first transistor T1 via the second node N2. The fourth transistor T4a can be referred to as the first emission control transistor. The fourth transistor T4a can be turned on when the first emission signal EM1 is applied to it via the first emission line ESL1i, and therefore, the light-emitting element LD can be electrically connected to the first transistor T1.

[0147] A fifth transistor T5a can be connected between the second power line VSL and the third node N3. The first electrode of the fifth transistor T5a can be connected to the second electrode of the first transistor T1 via the third node N3, and the second electrode of the fifth transistor T5a can receive a second power voltage VSS via the second power line VSL. The gate of the fifth transistor T5a can be electrically connected to the second emitter line ESL2i. The fifth transistor T5a can be referred to as the second emitter control transistor. The fifth transistor T5a can be turned on when a second emitter signal EM2 is applied to it via the second emitter line ESL2i, and therefore, the second electrode of the first transistor T1 can be electrically connected to the second power line VSL.

[0148] In this embodiment, the fourth transistor T4a and the fifth transistor T5a can be connected to the first emitter line ESL1i and the second emitter line ESL2i, which are distinct from each other, respectively, and can be turned on in response to the first emitter signal EM1 and the second emitter signal EM2, which are distinct from each other, respectively. That is, the fourth transistor T4a and the fifth transistor T5a can be turned on independently; however, this is merely an example. As an example, the fourth transistor T4a and the fifth transistor T5a can be connected to the same emitter line and can be controlled by the same emitter signal. Furthermore, the fourth transistor T4a or the fifth transistor T5a can be omitted from the pixel driving unit PDC-2.

[0149] The sixth transistor T6a can be connected between the initialization voltage line VIL and the fourth node N4. That is, the sixth transistor T6a can include a gate connected to the compensation scan line GCLi, a first electrode connected to the initialization voltage line VIL, and a second electrode connected to the fourth node N4. The sixth transistor T6a can be referred to as the initialization transistor. The sixth transistor T6a can provide an initialization voltage VINT to the fourth node N4 corresponding to the cathode of the light-emitting element LD in response to the compensation scan signal GC applied to it via the compensation scan line GCLi. The cathode of the light-emitting element LD can be initialized by the initialization voltage VINT.

[0150] A first capacitor C1 can be positioned between the first node N1 and the third node N3. The first capacitor C1 can be charged with a voltage corresponding to the difference between the voltage at the first node N1 and the voltage at the third node N3. The first capacitor C1 can be referred to as a storage capacitor.

[0151] A second capacitor C2 can be disposed between the third node N3 and the second electric field line VSL. That is, one electrode of the second capacitor C2 can be connected to the second electric field line VSL to which the second electric field voltage VSS is applied, and the other electrode of the second capacitor C2 can be connected to the third node N3. The second capacitor C2 can be charged with a charge corresponding to the voltage difference between the second electric field voltage VSS and the voltage at the third node N3. The second capacitor C2 can be referred to as a holding capacitor.

[0152] The light-emitting element (LD) may include an anode and a cathode. In one embodiment, the anode of the LD may be connected to a first power line VDL, and the cathode of the LD may be connected to the pixel driving unit PDC-2 via a fourth node N4. In another embodiment, the cathode of the LD may be connected to a first transistor T1 via a fourth transistor T4a. The LD may emit light in response to the amount of current flowing through the first transistor T1 of the pixel driving unit PDC-2.

[0153] In embodiments where each of the first transistor T1, second transistor T2, third transistor T3, fourth transistor T4a, fifth transistor T5a, and sixth transistor T6a is an N-type transistor, the potential of the third node N3, corresponding to the source of the first transistor T1 (which serves as the driving transistor), is not directly affected by the characteristics of the light-emitting element (LD). Therefore, even if the LD deteriorates, the impact of this deterioration on the gate-source voltage (Vgs) of the transistors (especially the driving transistors) constituting the pixel driving unit PDC-2 can be reduced. In other words, since the change in the amount of driving current ILD caused by the deterioration of the LD can be reduced, image retention defects in the display panel caused by increased usage time can be reduced, and the lifespan of the display panel can be improved.

[0154] Figure 2A , Figure 2B and Figure 2C Circuits for pixel driving units PDC, PDC-1, and PDC-2 according to embodiments of the present disclosure are shown, and the number and arrangement of transistors and capacitors can be designed in various ways, as long as the circuit is connected to the cathode of the light-emitting element LD in the display panel.

[0155] Figure 3A and Figure 3B This is a schematic plan view of a display panel DP according to an embodiment of the present disclosure. For ease of explanation, in Figure 3A and Figure 3B Some components are omitted from each of them. These will be referenced below. Figure 3A and Figure 3B This disclosure is described.

[0156] refer to Figure 3A The display panel DP may include a display area DA and a peripheral area (or non-display area) NDA. The display area DA may include a light-emitting portion EP.

[0157] The luminescent part EP can be pixel PXij (reference) Figure 1 The region that emits light. Specifically, each of the light-emitting portions EP can correspond to the light-emitting opening OP-PDL (see reference EP) described later. Figure 5 ).

[0158] The peripheral region NDA can be defined as being adjacent to the display region DA. In an embodiment, the peripheral region NDA may have a shape surrounding the edge of the display region DA; however, this is merely an example. According to an embodiment, the peripheral region NDA may be defined as being adjacent to one side of the display region DA, or the peripheral region NDA may be omitted.

[0159] In this embodiment, the scan driver SDC and the data driver DDC can be mounted on the display panel DP. The scan driver SDC can be disposed in the display area DA, and the data driver DDC can be disposed in the peripheral area NDA. The scan driver SDC can overlap at least some of the light-emitting portions EP arranged in the display area DA in a plan view. Since the scan driver SDC is disposed in the display area DA, the size of the peripheral area NDA can be reduced compared to the size of the peripheral area of ​​a conventional display panel in which the scan driver is disposed in the peripheral area, and therefore, a narrow bezel of the display device can be easily achieved.

[0160] and Figure 3A Unlike the scan driver SDC shown, the scan driver SDC can be provided in two separate parts. The two scan driver SDCs can be located on the left and right sides of the display area DA, respectively, and can be spaced apart from each other. According to embodiments, three or more scan driver SDCs can be used, but the number of scan driver SDCs should not be particularly limited.

[0161] Figure 3A A representative example of a display panel DP is shown, and the data driver DDC can also be set in the display area DA. When the data driver DDC is set in the display area DA, some of the light-emitting portions EP arranged in the display area DA can overlap with the data driver DDC in the plan view.

[0162] According to an embodiment, the data driver DDC can be provided in a separate driver chip formed independently of the display panel DP, and can be connected to the display panel DP; however, this is merely an example. According to an embodiment, the data driver DDC can be formed in the same process as the scan driver SDC to form the display panel DP, and the embodiment should not be limited thereto or thereby restricted.

[0163] refer to Figure 3B The display panel DP may have a length in the first direction DR1 that is longer than its length in the second direction DR2. The display panel DP may include pixels PX11 to PXnm arranged in n rows by m columns in the display area DA. In an embodiment, the display panel DP may include scan drivers SDC1 and SDC2. Scan drivers SDC1 and SDC2 may include a first scan driver SDC1 and a second scan driver SDC2 spaced apart from each other in the first direction DR1.

[0164] The first scan driver SDC1 can be connected to some of the scan lines GL1 to GLn, and the second scan driver SDC2 can be connected to the other scan lines GL1 to GLn. As an example, the first scan driver SDC1 can be connected to the odd-numbered scan lines GL1 to GLn, and the second scan driver SDC2 can be connected to the even-numbered scan lines GL1 to GLn.

[0165] For ease of explanation, Figure 3B The pads PD for data lines DL1 to DLm are shown. Pads PD can be placed at the ends of data lines DL1 to DLm. Data lines DL1 to DLm can be connected to a data driver (reference) via pads PD. Figure 3A Data drive (DDC).

[0166] According to this disclosure, pads PD can be arranged in spaced-apart areas of the peripheral area NDA, and the display area DA is located between said areas of the peripheral area NDA. As an example, some pads in the pads PD can be arranged in the upper part of the display panel DP adjacent to the first scan line GL1 of scan lines GL1 to GLn, and other pads in the pads PD can be arranged in the lower part of the display panel DP adjacent to the last scan line GLn of scan lines GL1 to GLn. In an embodiment, pads in the pads PD connected to odd-numbered data lines can be arranged in the upper part, and pads in the pads PD connected to even-numbered data lines can be arranged in the lower part.

[0167] Although not shown in the figures, the display panel DP may include a plurality of upper data drivers connected to pads PD arranged in the upper part and a plurality of lower data drivers connected to pads PD arranged in the lower part; however, these are merely examples. According to an embodiment, the display panel DP may include one upper data driver connected to pads PD arranged in the upper part and one lower data driver connected to pads PD arranged in the lower part. According to an embodiment, the pads PD may be arranged in only one side and may be connected to a single data driver, and this disclosure should not be particularly limited.

[0168] Additionally, as referenced Figure 3A As described, Figure 3B The scan driver and / or data driver of the display panel DP can be set in the display area DA, and therefore, some of the light-emitting parts arranged in the display area DA can overlap with the scan driver and / or data driver in the plan view.

[0169] Figures 4A to 4D The display panel DP according to an embodiment of this disclosure (see...) Figure 1 Enlarged schematic plan view of some areas.

[0170] Figure 4A The light-emitting units UT11, UT12, UT21, and UT22 are shown arranged in two rows by two columns. (Reference) Figure 4A The light-emitting portion arranged in the first row Rk may include the light-emitting portion constituting the light-emitting unit UT11 arranged in the first row and the first column and the light-emitting unit UT12 arranged in the first row and the second column, and the light-emitting portion arranged in the second row Rk+1 may include the light-emitting portion constituting the light-emitting unit UT21 arranged in the second row and the first column and the light-emitting unit UT22 arranged in the second row and the second column.

[0171] Each of the light-emitting portions EP1, EP2, and EP3 can correspond to the light-emitting opening OP-PDL described later (reference). Figure 5 In other words, each of the light-emitting portions EP1, EP2, and EP3 can be a region from which a light-emitting element emits light. The light-emitting portions EP1, EP2, and EP3 can correspond to providing light through the display panel DP (reference). Figure 1 The unit of the image displayed. More specifically, each of the light-emitting portions EP1, EP2 and EP3 may correspond to the area defined by the light-emitting opening OP-PDL, which will be described later (in particular, the area defined by the lower part of the light-emitting opening OP-PDL).

[0172] The light-emitting portions EP1, EP2, and EP3 may include a first light-emitting portion EP1, a second light-emitting portion EP2, and a third light-emitting portion EP3. The first light-emitting portion EP1, the second light-emitting portion EP2, and the third light-emitting portion EP3 may emit light of different colors from each other. For example, the first light-emitting portion EP1 may emit red light, the second light-emitting portion EP2 may emit green light, and the third light-emitting portion EP3 may emit blue light; however, the combination of colors of the first light-emitting portion EP1, the second light-emitting portion EP2, and the third light-emitting portion EP3 should not be limited to or restricted by this. Furthermore, at least two of the light-emitting portions EP1, EP2, and EP3 may emit light of the same color. For example, the first light-emitting portion EP1, the second light-emitting portion EP2, and the third light-emitting portion EP3 may all emit either blue light or white light.

[0173] Among the first light-emitting portion EP1, the second light-emitting portion EP2, and the third light-emitting portion EP3, the third light-emitting portion EP3, which displays an image corresponding to the light emitted by the third light-emitting element, may include two sub-light-emitting portions EP31 and EP32 spaced apart from each other in the second direction DR2; however, this is merely an example. According to embodiments, the third light-emitting portion EP3 may be provided as a single pattern formed as a single entity, like the first light-emitting portion EP1 and the second light-emitting portion EP2, or at least one of the first light-emitting portion EP1 and the second light-emitting portion EP2 may include sub-light-emitting portions spaced apart from each other, and this disclosure should not be particularly limited.

[0174] The light-emitting portion arranged in the first row Rk may include the first light-emitting portion EP1, the second light-emitting portion EP2, and the third light-emitting portion EP3 constituting the light-emitting unit UT11 arranged in the first row and the first column, and the first light-emitting portion EP1, the second light-emitting portion EP2, and the third light-emitting portion EP3a constituting the light-emitting unit UT12 arranged in the first row and the second column. The light-emitting portion arranged in the second row Rk+1 may include the first light-emitting portion EP1, the second light-emitting portion EP2, and the third light-emitting portion EP3a constituting the light-emitting unit UT21 arranged in the second row and the first column, and the first light-emitting portion EP1, the second light-emitting portion EP2, and the third light-emitting portion EP3 constituting the light-emitting unit UT22 arranged in the second row and the second column.

[0175] The light-emitting portion of the light-emitting unit UT11 arranged in the first row and first column can have approximately the same shape as the light-emitting portion of the light-emitting unit UT22 arranged in the second row and second column. Furthermore, the light-emitting portion of the light-emitting unit UT12 arranged in the first row and second column can have approximately the same shape as the light-emitting portion of the light-emitting unit UT21 arranged in the second row and first column. The light-emitting portion of the light-emitting unit UT11 arranged in the first row and first column can have a different shape than the light-emitting portion of the light-emitting unit UT12 arranged in the first row and second column. As an example, some of the light-emitting portions arranged in the first row Rk can have a shape symmetrical with respect to some of the light-emitting portions arranged in the second row Rk+1.

[0176] The third light-emitting portion EP3a of the light-emitting unit UT21 arranged in the second row and the first column and the third light-emitting portion EP3 of the light-emitting unit UT11 arranged in the first row and the first column may have a line-symmetrical shape and arrangement relative to an axis that is generally parallel to the first direction DR1. The third light-emitting portion EP3 of the light-emitting unit UT22 arranged in the second row and the second column and the third light-emitting portion EP3a of the light-emitting unit UT12 arranged in the first row and the second column may also have a line-symmetrical shape and arrangement relative to an axis that is generally parallel to the first direction DR1. However, this disclosure should not be limited to or restricted by this.

[0177] Figure 4B The luminous components arranged in a row are shown. For ease of explanation, Figure 4B The diagram shows second electrodes EL2_1, EL2_2 and EL2_3, pixel driving units PDC1, PDC2 and PDC3, first connecting electrode CNE1, second connecting electrode CNE2 and third connecting electrode CNE3, and groove GV. Figure 4C The diagram shows the recess GV in the components of the display panel DP, and the light-emitting portions EP1, EP2, and EP3 disposed in the area defined by the recess GV (see [link]). Figure 4B ), and connecting electrodes CNE1, CNE2 and CNE3.

[0178] refer to Figure 4B and Figure 4CThe second electrodes EL2_1, EL2_2, and EL2_3 can be separated from each other by the groove GV and can be electrically disconnected from each other. In an embodiment, the light-emitting unit UT11 may include three light-emitting portions EP1, EP2, and EP3. Therefore, the light-emitting unit UT11 may include three second electrodes EL2_1, EL2_2, and EL2_3 (hereinafter referred to as the first cathode EL2_1, the second cathode EL2_2, and the third cathode EL2_3), three pixel driving units PDC1, PDC2, and PDC3, and three connecting electrodes CNE1, CNE2, and CNE3; however, this is merely an example. The number and arrangement of the light-emitting portions included in the light-emitting unit UT11 can be designed in various ways, and this disclosure should not be particularly limited.

[0179] The first pixel driving unit PDC1, the second pixel driving unit PDC2, and the third pixel driving unit PDC3 can be electrically connected to the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3, which include the first light-emitting portion EP1, the second light-emitting portion EP2, and the third light-emitting portion EP3, respectively. In this disclosure, the statement that component A is connected to component B can mean not only the case where component A is directly and physically connected to component B, but also the case where component A is electrically connected to component B.

[0180] In addition, such as Figure 4B As shown, each of the regions defining the first pixel driving unit PDC1, the second pixel driving unit PDC2, and the third pixel driving unit PDC3 in the plan view can correspond to a pixel driving unit PDC (see reference) that includes a light-emitting element constituting a pixel for driving a pixel. Figure 2A ( ) is a unit of transistors and capacitors.

[0181] The first pixel driving unit PDC1, the second pixel driving unit PDC2, and the third pixel driving unit PDC3 can be arranged sequentially on the first direction DR1. The arrangement position and shape of the first pixel driving unit PDC1, the second pixel driving unit PDC2, and the third pixel driving unit PDC3 can be designed independently of the position and shape of the first light-emitting part EP1, the second light-emitting part EP2, and the third light-emitting part EP3.

[0182] As an example, the first pixel driving unit PDC1, the second pixel driving unit PDC2, and the third pixel driving unit PDC3 can be placed at locations different from the area divided by the groove GV (i.e., the location where the first cathode EL2_1, the second cathode EL2_2, and the third cathode EL2_3 are placed), or can be designed to have shapes and dimensions different from those of the first cathode EL2_1, the second cathode EL2_2, and the third cathode EL2_3. According to an embodiment, the first pixel driving unit PDC1, the second pixel driving unit PDC2, and the third pixel driving unit PDC3 can be placed to overlap with the locations where the first light-emitting portion EP1, the second light-emitting portion EP2, and the third light-emitting portion EP3 are placed, respectively, and can be designed to have shapes and dimensions similar to those of the area divided by the groove GV (i.e., the shape and dimensions of the first cathode EL2_1, the second cathode EL2_2, and the third cathode EL2_3).

[0183] In the embodiment, each of the first pixel driving unit PDC1, the second pixel driving unit PDC2, and the third pixel driving unit PDC3 may have a rectangular shape. Each of the first light-emitting portion EP1, the second light-emitting portion EP2, and the third light-emitting portion EP3 may have a size smaller than that of the first pixel driving unit PDC1, the second pixel driving unit PDC2, and the third pixel driving unit PDC3, and a shape different from that of the first pixel driving unit PDC1, the second pixel driving portion PDC2, and the third pixel driving unit PDC3. Furthermore, the first cathode EL2_1, the second cathode EL2_2, and the third cathode EL2_3 may be placed at a position overlapping with the first light-emitting portion EP1, the second light-emitting portion EP2, and the third light-emitting portion EP3, and may have atypical shapes.

[0184] Accordingly, such as Figure 4B As shown, the first pixel driving unit PDC1 can be placed at a position overlapping with the first light-emitting portion EP1, the second light-emitting portion EP2, and a portion of another light-emitting unit adjacent to the first light-emitting portion EP1 and the second light-emitting portion EP2. The second pixel driving unit PDC2 can be placed at a position overlapping with the first light-emitting portion EP1, the second light-emitting portion EP2, and the third cathode EL2_3. The third pixel driving unit PDC3 can be placed at a position overlapping with the third light-emitting portion EP3; however, these are merely examples. According to embodiments, the arrangement and shape of the first pixel driving unit PDC1, the second pixel driving unit PDC2, and the third pixel driving unit PDC3 can be independent of the position and shape design of the light-emitting portions EP1, EP2, and EP3, and should not be particularly limited.

[0185] The light-emitting unit UT11 may include a first connecting electrode CNE1, a second connecting electrode CNE2, and a third connecting electrode CNE3. The first connecting electrode CNE1 can electrically connect a first light-emitting element LD1, in which a first light-emitting portion EP1 is formed (or a first light-emitting portion EP1 is defined), to a first pixel driving unit PDC1. The second connecting electrode CNE2 can electrically connect a second light-emitting element LD2, in which a second light-emitting portion EP2 is formed, to a second pixel driving unit PDC2. And the third connecting electrode CNE3 can electrically connect a third light-emitting element LD3, in which a third light-emitting portion EP3 is formed, to a third pixel driving unit PDC3.

[0186] In detail, the first connecting electrode CNE1, the second connecting electrode CNE2, and the third connecting electrode CNE3 can be electrically connected to the first cathode EL2_1, the second cathode EL2_2, and the third cathode EL2_3 with the first pixel driving unit PDC1, the second pixel driving unit PDC2, and the third pixel driving unit PDC3 in a one-to-one correspondence.

[0187] Each of the first connecting electrode CNE1, the second connecting electrode CNE2, and the third connecting electrode CNE3 may be disposed in the pixel defining layer PDL (see reference ) described later. Figure 5 The first connecting electrode CNE1, the second connecting electrode CNE2, and the third connecting electrode CNE3 may each have an annular shape surrounding a corresponding light-emitting portion among the first light-emitting portion EP1, the second light-emitting portion EP2, and the third light-emitting portion EP3. In an embodiment, as a representative example, each of the first connecting electrode CNE1, the second connecting electrode CNE2, and the third connecting electrode CNE3 may have a closed-loop shape; however, the embodiment should not be limited thereto or thereby restricted. As an example, at least one of the first connecting electrode CNE1, the second connecting electrode CNE2, and the third connecting electrode CNE3 may have an open-loop shape with a portion of it cut off.

[0188] Because the first connecting electrode CNE1, the second connecting electrode CNE2, and the third connecting electrode CNE3 have an annular shape, the freedom in determining the connection positions of these electrodes to the first pixel driving unit PDC1, the second pixel driving unit PDC2, and the third pixel driving unit PDC3 can be improved. As an example, the first connecting electrode CNE1 can be connected to the first pixel driving unit PDC1 via the first connecting portion CE1, the second connecting electrode CNE2 can be connected to the second pixel driving unit PDC2 via the second connecting portion CE2, and the third connecting electrode CNE3 can be connected to the third pixel driving unit PDC3 via the connecting line CN3. In other words, the additional connecting lines to the first connecting electrode CNE1 and the second connecting electrode CNE2 can be omitted.

[0189] Connector CN3 electrically connects the third pixel driving unit PDC3 to the third light-emitting element LD3 of the third light-emitting part EP3. Specifically, connector CN3 corresponds to the light-emitting element LD (see reference). Figure 2A Connected to Figure 2A Pixel driver unit (PDC), Figure 2B Pixel driving unit PDC-1 or Figure 2C The node where the pixel driving unit PDC-2 is located (reference) Figure 2A The fourth node N4, Figure 2B The second node N2 or Figure 2C The fourth node N4).

[0190] The connecting line CN3 may include a third connecting portion CE3 and a driving connecting portion CD3. The third connecting portion CE3 may be provided at one end of the connecting line CN3, and the driving connecting portion CD3 may be provided at the other end of the connecting line CN3.

[0191] The driving connection portion CD3 can be the part of the connecting line CN3 that connects to the pixel driving unit PDC3. In an embodiment, the driving connection portion CD3 can be connected to the electrode of the transistor in the pixel driving unit PDC3. Specifically, the driving connection portion CD3 can be connected to... Figure 2A The drain of the sixth transistor T6 shown, Figure 2B The drain of the first transistor T1 shown is or Figure 2C The drain of the fourth transistor T4a is shown. Therefore, the position of the drive connection portion CD3 can correspond to the position of the transistor physically connected to the connection line CN3 in the pixel driving unit. The third connection portion CE3 can be the portion of the connection line CN3 connected to the third light-emitting element LD3. In an embodiment, the third connection portion CE3 can be connected to the third connection electrode CNE3.

[0192] The first connecting electrode CNE1 may include a first edge EG11 surrounding at least a portion of the first light-emitting portion EP1 and a second edge EG12 surrounding the first edge EG11. The second connecting electrode CNE2 may include a first edge EG21 surrounding at least a portion of the second light-emitting portion EP2 and a second edge EG22 surrounding the first edge EG21. The third connecting electrode CNE3 may include a first edge EG31 surrounding at least a portion of the third light-emitting portion EP3 and a second edge EG32 surrounding the first edge EG31.

[0193] The first connecting electrode CNE1, the second connecting electrode CNE2, and the third connecting electrode CNE3 can be arranged spaced apart from each other. As an example, the gaps GP1, GP2, and GP3 between adjacent connecting electrodes of the first connecting electrode CNE1, the second connecting electrode CNE2, and the third connecting electrode CNE3 can overlap with the groove GV. As an example, the first edge EG11 of the first connecting electrode CNE1, the first edge EG21 of the second connecting electrode CNE2, and the first edge EG31 of the third connecting electrode CNE3 can not overlap with the groove GV, and the second edges EG12 of the first connecting electrode CNE1, the second edge EG22 of the second connecting electrode CNE2, and the second edge EG32 of the third connecting electrode CNE3 can overlap with the groove GV.

[0194] The first connecting portion CE1, the second connecting portion CE2, and the third connecting portion CE3 can be positioned in the plan view at locations that do not overlap with the first light-emitting portion EP1, the second light-emitting portion EP2, and the third light-emitting portion EP3. As an example, the light-emitting opening OP-PDL (see reference) can be defined through the pixel-limiting layer PDL. Figure 5 ) and through-holes OP-P spaced apart from the light-emitting opening OP-PDL (reference) Figure 5 ).

[0195] The through-hole OP-P may include a first through-hole OP-P1, a second through-hole OP-P2, and a third through-hole OP-P3. The first connecting portion CE1, the second connecting portion CE2, and the third connecting portion CE3 may be arranged corresponding to the first through-hole OP-P1, the second through-hole OP-P2, and the third through-hole OP-P3, respectively. The light-emitting opening OP-PDL may include a first light-emitting opening OP-PDL1, a second light-emitting opening OP-PDL2, and a third light-emitting opening OP-PDL3. The first light-emitting portion EP1, the second light-emitting portion EP2, and the third light-emitting portion EP3 may be defined to correspond to the first light-emitting opening OP-PDL1, the second light-emitting opening OP-PDL2, and the third light-emitting opening OP-PDL3, respectively. Therefore, the first connecting portion CE1, the second connecting portion CE2, and the third connecting portion CE3 may be arranged at positions spaced apart from the first light-emitting portion EP1, the second light-emitting portion EP2, and the third light-emitting portion EP3.

[0196] The first connecting electrode CNE1, the second connecting electrode CNE2, and the third connecting electrode CNE3 can be disposed in the pixel limiting layer PDL (see reference). Figure 5 In the plan view, the first connecting electrode CNE1 can surround the first light-emitting opening OP-PDL1, the second connecting electrode CNE2 can surround the second light-emitting opening OP-PDL2, and the third connecting electrode CNE3 can surround the third light-emitting opening OP-PDL3.

[0197] The transistor TR (reference) is the third pixel driving unit PDC3 of the connecting line CN3. Figure 5 The driving connection portion CD3, which is connected to the connecting line CN3, can be positioned in the plan view at a location that does not overlap with the third connecting portion CE3, and can be positioned at a location that overlaps with the third light-emitting portion EP3. Because the third cathode EL2_3 is connected to the third pixel driving unit PDC3 via the connecting line CN3, the design limitations of the third pixel driving unit PDC3 due to the position or shape of the third light-emitting portion EP3 can be reduced, and the freedom of circuit design can be improved.

[0198] The first cathode EL2_1, the second cathode EL2_2, and the third cathode EL2_3 can be connected to the first connecting electrode CNE1, the second connecting electrode CNE2, and the third connecting electrode CNE3, respectively. As an example, the first cathode EL2_1, the second cathode EL2_2, and the third cathode EL2_3 can be connected to the first connecting electrode CNE1, the second connecting electrode CNE2, and the third connecting electrode CNE3, respectively, in a region adjacent to the groove GV.

[0199] Furthermore, the connection regions of the first cathode EL2_1, the second cathode EL2_2, and the third cathode EL2_3 connected to the first connecting electrode CNE1, the second connecting electrode CNE2, and the third connecting electrode CNE3 can respectively surround at least a portion of the first light-emitting opening OP-PDL1, the second light-emitting opening OP-PDL2, and the third light-emitting opening OP-PDL3. The first cathode EL2_1, the second cathode EL2_2, and the third cathode EL2_3 can be connected to the first connecting electrode CNE1, the second connecting electrode CNE2, and the third connecting electrode CNE3 in regions adjacent to the groove GV, and each of these connection regions can be defined as being adjacent to the groove GV. In other words, the first cathode EL2_1, the second cathode EL2_2, and the third cathode EL2_3 may not be connected to the first connecting electrode CNE1, the second connecting electrode CNE2, and the third connecting electrode CNE3 at specific points. Instead, they may be connected to the first connecting electrode CNE1, the second connecting electrode CNE2, and the third connecting electrode CNE3 in a relatively large (relatively wide) region (e.g., in a region having a shape similar to that of each of the first connecting electrode CNE1, the second connecting electrode CNE2, and the third connecting electrode CNE3). That is, the size of the connection region can be increased, and therefore, the connection between the first cathode EL2_1, the second cathode EL2_2, and the third cathode EL2_3 and the first connecting electrode CNE1, the second connecting electrode CNE2, and the third connecting electrode CNE3 can be stable.

[0200] Figure 4D The groove GV, the light-emitting portions EP1, EP2 and EP3, and the first electrode EL1 are shown.

[0201] refer to Figure 4D Also refer to Figure 3A Light-emitting element LD (reference) Figure 5 The first electrode EL1 (hereinafter referred to as anode EL1) of the light-emitting element LD can be commonly disposed in the light-emitting portions EP1, EP2, and EP3. That is, anode EL1 can extend throughout the display area DA having a single main body layer, and therefore, anode EL1 can overlap with the recess GV. According to an embodiment, the anode EL1 of the light-emitting element LD can be formed as conductive patterns that are independent of each other and can be electrically connected to each other via other conductive layers, and therefore, anode EL1 can be configured not to overlap with the recess GV.

[0202] As described above, the first power voltage VDD (reference) can be used. Figure 2A A common voltage can be applied to the anode EL1, and can be applied to all light-emitting parts. The anode EL1 can be connected in the peripheral region NDA to the first power line VDL (reference) that provides the first power voltage VDD. Figure 2AAlternatively, it can be connected to the first power line VDL in the display area DA (see reference). Figure 2A Furthermore, the embodiments should not be limited thereto or thereby restricted.

[0203] An opening can be defined by the anode EL1, and the opening can penetrate the anode EL1. The opening defined by the anode EL1 can be positioned so as not to interact with the light-emitting portion EP (reference). Figure 3A The opening overlaps with and can be defined as substantially overlapping with the groove GV. The opening facilitates discharge from the organic layer (e.g., the sixth insulating layer 60, referenced below the anode EL1). Figure 5 The gases generated are thus reduced. Therefore, since the gases from the organic layer located beneath the light-emitting element (LD) are sufficiently expelled during the manufacturing process of the display panel (DP), the gases generated from the organic layer after the manufacturing process is completed can be reduced, and thus the degradation rate of the light-emitting element (LD) can be decreased.

[0204] Figure 5 This is a schematic cross-sectional view of a display panel DP according to an embodiment of the present disclosure. Figure 5 It shows along Figure 4C The cross-sectional view taken from line I-I'.

[0205] refer to Figure 5 Also refer to Figure 3A and Figure 4C The display panel DP may include a substrate layer BS, a driving element layer DDL, a light-emitting element layer LDL, an encapsulation layer ECL, and a sensing layer ISL; however, this is merely an example. According to an embodiment, the display panel DP may not include the sensing layer ISL.

[0206] The driving element layer (DDL) may include insulating layers 10, 20, 30, 40, 50, and 60 disposed on the substrate layer (BS), and conductive and semiconductor patterns disposed between the insulating layers 10, 20, 30, 40, 50, and 60. The conductive and semiconductor patterns disposed between the insulating layers 10, 20, 30, 40, 50, and 60 can form a pixel driving unit (PDC). For ease of explanation, Figure 5 A cross-section of a portion of the area in which a light-emitting part is located is shown.

[0207] The substrate layer BS can provide a substrate surface on which the pixel driving unit PDC is disposed. The substrate layer BS can be a rigid substrate or a flexible substrate that is bendable, foldable, or rollable. The substrate layer BS can be a glass substrate, a metal substrate, or a polymer substrate; however, the embodiments should not be limited thereto or thereby restricted. According to an embodiment, the substrate layer BS can be an inorganic layer, an organic layer, or a composite material layer.

[0208] The substrate layer BS can have a multilayer structure. The substrate layer BS may include a first polymer resin layer and silicon dioxide (SiO₂) disposed on the first polymer resin layer. x The structure comprises a silicon oxide layer, an amorphous silicon (a-Si) layer disposed on the silicon oxide layer, and a second polymer resin layer disposed on the amorphous silicon (a-Si) layer. Silicon oxide (SiO₂) x The amorphous silicon (a-Si) layer can be referred to as the substrate barrier layer.

[0209] Each of the first polymer resin layer and the second polymer resin layer may comprise a polyimide resin. Furthermore, each of the first polymer resin layer and the second polymer resin layer may comprise at least one selected from acrylic resins, methacrylic resins, polyisoprene resins, vinyl resins, epoxy resins, urethane resins, cellulose resins, siloxane resins, polyamide resins, and perylene resins. In this disclosure, as used herein, the term "X-type resin" refers to a resin containing an X functional group.

[0210] The insulating layer, conductive layer, and semiconductor layer disposed on the substrate layer BS can be formed by coating and deposition processes. The insulating layer, semiconductor layer, and conductive layer can be selectively patterned by several photolithography processes, and therefore, through-holes can be defined through the insulating layer, or semiconductor patterns, conductive patterns, and signal lines can be formed.

[0211] The driving element layer (DDL) may include a first insulating layer 10, a second insulating layer 20, a third insulating layer 30, a fourth insulating layer 40, a fifth insulating layer 50, and a sixth insulating layer 60, and a pixel driving unit (PDC), which are sequentially stacked on the substrate layer (BS). Figure 5 The image shows a transistor TR and two capacitors C1 and C2 in the pixel drive unit PDC.

[0212] Transistor TR can correspond to a transistor connected to the light-emitting element LD via intermediate connection electrode CN and connection electrode CNE, that is, connected to the node corresponding to the cathode of the light-emitting element LD. Figure 2A The fourth node N4, Figure 2B The second node N2 or Figure 2C The fourth node N4) is connected to the transistor. Specifically, transistor TR can correspond to... Figure 2A The sixth transistor T6, Figure 2B The first transistor T1 or Figure 2C The fourth transistor, T4a. Although not shown in the figure, the other transistors constituting the pixel drive unit (PDC) may have the same characteristics. Figure 5The structure of the transistor TR shown (hereinafter referred to as the connection transistor TR) is substantially the same; however, this is merely an example. According to embodiments, other transistors constituting the pixel driving unit PDC may have structures different from those of the connection transistor TR, and should not be particularly limited thereto.

[0213] The first insulating layer 10 may be disposed on the substrate layer BS. The first insulating layer 10 may be an inorganic layer and / or an organic layer, and may have a single-layer structure or a multilayer structure. The first insulating layer 10 may include at least one of alumina, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. In an embodiment, the first insulating layer 10 may have a single-layer structure of silicon oxide. The insulating layers described later may be inorganic layers and / or organic layers, and may have a single-layer structure or a multilayer structure. Inorganic layers may include at least one of the materials described above; however, the embodiments should not be limited thereto or thereby restricted.

[0214] The first insulating layer 10 may cover the lower conductive layer BCL. That is, the display panel DP may further include a lower conductive layer BCL overlapping the connecting transistor TR. The lower conductive layer BCL can prevent the potential caused by the polarization phenomenon of the substrate layer BS from affecting the connecting transistor TR. Additionally, the lower conductive layer BCL can block light incident on the connecting transistor TR from below the lower conductive layer BCL. At least one of an inorganic blocking layer and a buffer layer may be further disposed between the lower conductive layer BCL and the substrate layer BS.

[0215] The lower conductive layer (BCL) may include reflective metallic materials and metal nitrides. As examples, the lower conductive layer (BCL) may include titanium (Ti), molybdenum (Mo), alloys including molybdenum (Mo), aluminum (Al), alloys including aluminum (Al), aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), and copper (Cu).

[0216] In an embodiment, the lower conductive layer BCL can be connected to the source of the connecting transistor (or transistor) TR via the source electrode pattern W1. The lower conductive layer BCL can be synchronized with the source of the transistor TR; however, this is merely an example. According to an embodiment, the lower conductive layer BCL can be connected to and synchronized with the gate of the transistor TR. According to an embodiment, the lower conductive layer BCL can be connected to another electrode to independently receive a constant voltage or pulse signal. According to an embodiment, the lower conductive layer BCL can be provided in an isolated form, isolated from other conductive patterns. The lower conductive layer BCL can be provided in various forms and should not be particularly limited.

[0217] A connecting transistor TR may be disposed on the first insulating layer 10. The connecting transistor TR may include a semiconductor pattern SP and a gate electrode GE. The semiconductor pattern SP may be disposed on the first insulating layer 10. The semiconductor pattern SP may include an oxide semiconductor. As an example, the oxide semiconductor may include a transparent conductive oxide (TCO), such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), or indium oxide (In2O3), however, the material used for the semiconductor pattern SP should not be limited thereto or thereby restricted. As an example, the semiconductor pattern SP may include amorphous silicon or polycrystalline silicon (such as low-temperature polycrystalline silicon).

[0218] The semiconductor pattern SP may include a source region SR, a drain region DR, and a channel region CR, which are separated from each other according to their conductivity. The channel region CR may overlap with the gate electrode GE in the planar diagram. The source region SR and the drain region DR may be spaced apart from each other, and the channel region CR is located between the source region SR and the drain region DR. When the semiconductor pattern SP is an oxide semiconductor, each of the source region SR and the drain region DR may be a reduced region. Therefore, the source region SR and the drain region DR may have a relatively high content of reduced metal compared to the channel region CR. According to an embodiment, when the semiconductor pattern SP is polysilicon, each of the source region SR and the drain region DR may be a highly doped region.

[0219] Compared to the channel region CR, the source region SR and drain region DR can have relatively high conductivity. The source region SR can correspond to the source electrode connected to the transistor TR, and the drain region DR can correspond to the drain electrode connected to the transistor TR. For example... Figure 5 As shown, the connecting transistor TR may further include source electrode patterns W1 and drain electrode patterns W2 that are separate from each other and respectively connected to the source region SR and the drain region DR. Specifically, each of the source electrode pattern W1 and drain electrode pattern W2 can be associated with a pixel driving unit PDC (see reference). Figure 2A ), Pixel driving unit PDC-1 (reference) Figure 2B ) and pixel driving unit PDC-2 (reference) Figure 2C The lines are integrally formed; however, the embodiments should not be limited thereto or thereby restricted.

[0220] The second insulating layer 20 may commonly overlap with the pixel and may cover the semiconductor pattern SP. The second insulating layer 20 may be an inorganic layer and / or an organic layer, and may have a single-layer structure or a multi-layer structure. The second insulating layer 20 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. In an embodiment, the second insulating layer 20 may have a single-layer structure of silicon oxide.

[0221] The gate electrode GE can be disposed on the second insulating layer 20. The gate electrode GE can correspond to the gate of the transistor TR. Alternatively, the gate electrode GE can be disposed on the semiconductor pattern SP; however, this is merely an example. According to an embodiment, the gate electrode GE can be disposed below the semiconductor pattern SP, and the embodiment should not be particularly limited.

[0222] The gate electrode GE may include titanium (Ti), silver (Ag), molybdenum (Mo), aluminum (Al), tungsten (W), copper (Cu) or alloys thereof, aluminum nitride (AlN) and tungsten nitride (WN), however, the embodiments should not be particularly limited.

[0223] The third insulating layer 30 can be disposed on the gate electrode GE. The third insulating layer 30 can be an inorganic layer and / or an organic layer, and can have a single-layer structure or a multi-layer structure.

[0224] In the conductive patterns W1, W2, CPE1, CPE2, and CPE3, the first capacitor electrode CPE1 and the second capacitor electrode CPE2 can form a first capacitor C1. The first capacitor electrode CPE1 and the second capacitor electrode CPE2 can be spaced apart from each other, and the first insulating layer 10 and the second insulating layer 20 are located between the first capacitor electrode CPE1 and the second capacitor electrode CPE2.

[0225] According to an embodiment, the first capacitor electrode CPE1 and the lower conductive layer BCL can be provided integrally with each other. Additionally, the second capacitor electrode CPE2 can be provided integrally with the gate electrode GE.

[0226] The third capacitor electrode CPE3 can be disposed on the third insulating layer 30. The third capacitor electrode CPE3 can be spaced apart from the second capacitor electrode CPE2, and the third insulating layer 30 is located between the third capacitor electrode CPE3 and the second capacitor electrode CPE2. The third capacitor electrode CPE3 can overlap with the second capacitor electrode CPE2 in a planar view. The third capacitor electrode CPE3 and the second capacitor electrode CPE2 can form a second capacitor C2.

[0227] The fourth insulating layer 40 may be disposed on the third insulating layer 30 and / or the third capacitor electrode CPE3. The fourth insulating layer 40 may be an inorganic layer and / or an organic layer, and may have a single-layer structure or a multi-layer structure. The fourth insulating layer 40 may include at least one of alumina, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide.

[0228] Source electrode pattern W1 and drain electrode pattern W2 can be disposed on the fourth insulating layer 40. Source electrode pattern W1 can be connected to the source region SR of the transistor TR via the first contact hole CNT1, and both source electrode pattern W1 and the source region SR of the semiconductor pattern SP can serve as the source of the transistor TR. Drain electrode pattern W2 can be connected to the drain region DR of the transistor TR via the second contact hole CNT2, and both drain electrode pattern W2 and the drain region DR of the semiconductor pattern SP can serve as the drain of the transistor TR. A fifth insulating layer 50 can be disposed on the source electrode pattern W1 and drain electrode pattern W2.

[0229] The intermediate connection electrode CN can be disposed on the fifth insulating layer 50. The intermediate connection electrode CN can electrically connect the pixel driving unit PDC to the light-emitting element LD. That is, the intermediate connection electrode CN can electrically connect the connection transistor TR to the light-emitting element LD. The intermediate connection electrode CN can be a connection node connecting the pixel driving unit PDC to the light-emitting element LD. In other words, the intermediate connection electrode CN can correspond to... Figure 2A The fourth node N4 shown can correspond to Figure 2B The second node N2 shown Figure 2C The fourth node N4 is shown in the diagram.

[0230] The intermediate connecting electrode CN may comprise a first layer L1, a second layer L2, and a third layer L3 sequentially stacked on the third-direction DR3. The second layer L2 may comprise a material different from that of the first layer L1. The second layer L2 may comprise a material different from that of the third layer L3. The second layer L2 may have a thickness relatively greater than that of the first layer L1. The second layer L2 may have a thickness relatively greater than that of the third layer L3. The second layer L2 may comprise a material with high conductivity. As an example, the second layer L2 may comprise aluminum (Al).

[0231] A sixth insulating layer 60 may be disposed on the intermediate connecting electrode CN. The sixth insulating layer 60 may be disposed on the fifth insulating layer 50 and may cover at least a portion of the intermediate connecting electrode CN. Each of the fifth insulating layer 50 and the sixth insulating layer 60 may be an organic layer. As an example, each of the fifth insulating layer 50 and the sixth insulating layer 60 may include general polymers such as polystyrene (PS), benzocyclobutene (BCB), hexamethyldisiloxane (HMDSO), polymethyl methacrylate (PMMA), polymer derivatives having phenolic groups, acrylic polymers, imide polymers (such as polyimide), aryl ether polymers, amide polymers, fluorinated polymers, p-xylene polymers, vinyl alcohol polymers, or blends thereof.

[0232] The sixth insulating layer 60 may be provided with a through-hole OP-60, which is defined in the sixth insulating layer 60 to expose at least a portion of the intermediate connection electrode CN. The intermediate connection electrode CN may be connected to the connection electrode CNE via a portion exposed by the sixth insulating layer 60 but not covered by the sixth insulating layer 60, and thus may be electrically connected to the light-emitting element LD. That is, the intermediate connection electrode CN and the connection electrode CNE can electrically connect the connection transistor TR to the light-emitting element LD. According to embodiments, the sixth insulating layer 60 may be omitted, or multiple sixth insulating layers 60 may be provided in the display panel DP; however, embodiments should not be particularly limited. In the case of omitting the sixth insulating layer 60, the intermediate connection electrode CN may also be omitted.

[0233] According to the embodiment, since the lower surface of the connecting electrode CNE contacts the upper surface of the intermediate connecting electrode CN, contact reliability can be improved. Therefore, the size of the through-holes OP-P and OP-60 required to connect the connecting electrode CNE and the intermediate connecting electrode CN can be reduced. Therefore, the size and resolution of the light-emitting portion of the display panel DP can be easily increased.

[0234] The light-emitting element layer (LDL) can be set on the driving element layer (DDL). The light-emitting element layer (LDL) may include the pixel definition layer (PDL) and the light-emitting element (LD).

[0235] The pixel-defining layer (PDL) can be an organic layer. As an example, the pixel-defining layer (PDL) may include general polymers such as polystyrene (PS), benzocyclobutene (BCB), hexamethyldisiloxane (HMDSO), polymethyl methacrylate (PMMA), polymer derivatives having phenolic groups, acrylic polymers, imide polymers (such as polyimide), aryl ether polymers, amide polymers, fluorinated polymers, p-xylene polymers, vinyl alcohol polymers, or blends thereof.

[0236] Pixel-defined layers (PDLs) can have light-absorbing properties. For example, a pixel-defined layer (PDL) can be black. That is, the pixel-defined layer (PDL) can include a black colorant. The black colorant can include a black dye or a black pigment. The black colorant can include carbon black, a metallic material (such as chromium), or an oxide thereof. The pixel-defined layer (PDL) can correspond to a light-blocking pattern with light-blocking properties.

[0237] The pixel-defining layer (PDL) may provide an opening (OP-PDL) defined within the PDL to expose at least a portion of the first electrode EL1 (hereinafter referred to as a light-emitting opening OP-PDL). Multiple light-emitting openings OP-PDLs may be provided, and each OP-PDL may correspond to a light-emitting element (LD). All components of the light-emitting element (LD) may overlap each other within the OP-PDLs, and each OP-PDL may correspond to an area that substantially displays light emitted from the light-emitting element (LD). Therefore, the first light-emitting portion EP1 (refer to...) Figure 4A The shape of the light-emitting opening (OP-PDL) can be basically corresponding to the shape of the light-emitting opening in the plan view.

[0238] The connecting electrode CNE can be disposed on the pixel definition layer PDL. The connecting electrode CNE can electrically connect the pixel driving unit PDC to the light-emitting element LD. That is, the pixel driving unit PDC can be electrically connected to the light-emitting element LD through the intermediate connecting electrode CN and the connecting electrode CNE. The connecting electrode CNE can correspond to... Figure 4A The first connection electrode CNE1 is shown. The second connection electrode CNE2 (reference) Figure 4A ) and the third connecting electrode CNE3 (reference) Figure 4A It can have a structure similar to that of the connecting electrode CNE.

[0239] The connecting electrode CNE may include a first edge EG1c adjacent to the light-emitting opening OP-PDL and a second edge EG2c surrounding the first edge EG1c. The second electrode EL2 of the light-emitting element LD may contact the connecting electrode CNE in the region adjacent to the second edge EG2c. That is, the second electrode EL2 and the connecting electrode CNE may be connected to each other in the region adjacent to the groove GV.

[0240] The connecting electrode CNE may include transparent conductive oxides (TCOs), such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), or indium oxide (In2O3), however, the materials used for the connecting electrode CNE should not be limited to or restricted by these.

[0241] The connecting electrode CNE may have a first light-emitting portion EP1 (reference) defined in the light-emitting element LD. Figure 4A The shape of at least a portion of the electrode CNE is thus improved. Therefore, the degree of freedom in designing the position of the connecting electrode CNE connected to the light-emitting element LD and the degree of freedom in designing the position of the connecting electrode CNE connected to the pixel driving unit PDC can be improved.

[0242] Furthermore, since the lower surface of the connecting electrode CNE contacts the upper surface of the intermediate connecting electrode CN, contact reliability can be improved. Therefore, the size of the vias OP-P and OP-60 required to connect the connecting electrode CNE to the intermediate connecting electrode CN can be reduced. Consequently, the size and resolution of the light-emitting portion of the display panel DP can be easily increased.

[0243] The groove GV can be defined within the pixel-defining layer PDL to surround the light-emitting opening OP-PDL. The groove GV can be formed by removing a portion of the pixel-defining layer PDL in its thickness direction (e.g., third-direction DR3). The groove GV can overlap with the gap between two adjacent connecting electrodes CNE disposed on the pixel-defining layer PDL.

[0244] A portion of the connecting electrode CNE can protrude from the end of the groove GV toward the center of the groove GV. This portion of the connecting electrode CNE can be defined as the tip portion TP. That is, the connecting electrode CNE may include the tip portion TP. Because the tip portion TP protrudes into the groove GV, the connecting electrode CNE can partially overlap with the groove GV in a planar view. The second electrode EL2 of the light-emitting element LD and the connecting electrode CNE can be connected to each other at the tip portion TP or can contact each other at the tip portion TP.

[0245] According to an embodiment, an aperture mask can be used to deposit and form the second electrode EL2 and the functional layer FNL across the pixel common ground. A portion of the functional layer FNL may include an organic layer. In the case of forming an organic layer across the common ground, lateral leakage current may occur due to the organic layer provided across the common ground of adjacent pixels, resulting in color mixing and brightness defects between adjacent pixels. In this disclosure, the term "lateral leakage current" refers to current flowing in a direction intersecting a third direction DR3 (i.e., the direction of image display) corresponding to the stacking direction of the light-emitting elements LD, rather than current flowing on the third direction DR3. Lateral leakage current may refer to current flowing in a direction substantially parallel to the plane defined by the first direction DR1 and the second direction DR2.

[0246] According to this disclosure, each of the intermediate layer IML and the second electrode EL2 can be divided into multiple portions by the tip portion TP of the connecting electrode CNE, and these multiple portions can be respectively disposed in multiple pixels to prevent lateral leakage current between adjacent pixels. Therefore, lateral leakage current can be prevented, as well as color mixing and brightness degradation between adjacent pixels can be prevented. The tip portion TP of the connecting electrode CNE can have a closed-line shape relative to each of the multiple light-emitting portions, and thus, each of the second electrode EL2 and the functional layer FNL can be divided into multiple portions respectively corresponding to the multiple light-emitting portions. That is, each of the second electrode EL2 and the intermediate layer IML can be electrically independent between adjacent pixels.

[0247] The tip portion TP can have a reverse taper shape. That is, the taper angle between the lower surface of the connecting electrode CNE and the side surface of the connecting electrode CNE can be an obtuse angle; however, this is merely an example. The taper angle can be set in various ways, as long as the second electrode EL2 is electrically disconnected through the tip portion TP of the connecting electrode CNE in each pixel. As an example, in the connecting electrode CNEa (reference... Figure 7 Only the first connecting electrode layer LL1 (reference) is included. Figure 7 In the case of ), the taper angle between the lower surface of the connecting electrode CNEa and the side surface of the connecting electrode CNEa can be an acute angle or a right angle.

[0248] A dummy pattern DMP can be set in a groove GV. A portion of the connecting electrode CNE (e.g., the second connecting electrode layer LL2) can be connected by the tip portion TP of the connecting electrode CNE. Figure 6A The second electrode EL2 and the functional layer FNL are separated to form a dummy pattern DMP; however, this is merely an example. (See reference...) Figures 6A to 9 This will be described in detail.

[0249] The via OP-P can be defined through the pixel defining layer PDL and can be spaced apart from the light-emitting opening OP-PDL. Multiple vias OP-P can be provided, and each via OP-P can be respectively provided corresponding to a light-emitting element LD. The via OP-P defined through the pixel defining layer PDL can have a larger size than the via OP-60 defined through the sixth insulating layer 60. A connecting electrode CNE can be provided in both the via OP-P and the via OP-60 and can be connected to an intermediate connecting electrode CN. That is, the connecting electrode CNE can be connected to the pixel driving unit PDC via the vias OP-P and OP-60.

[0250] The light-emitting element (LD) may include a first electrode EL1, an intermediate layer IML, and a second electrode EL2.

[0251] The first electrode EL1 can be a semi-transparent electrode, a transmissive electrode, or a reflective electrode. According to an embodiment, the first electrode EL1 may include a reflective layer formed of silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or compounds thereof, and a transparent or semi-transparent electrode layer formed on the reflective layer. The transparent or semi-transparent electrode layer may include at least one selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium oxide (In2O3), and aluminum-doped zinc oxide (AZO). For example, the first electrode EL1 may have an ITO / Ag / ITO stacked structure.

[0252] In this embodiment, the first electrode EL1 can be the anode of the light-emitting element LD. That is, the first electrode EL1 can be connected to the first electric field line VDL (reference). Figure 2A It can receive the first power voltage VDD (reference). Figure 2A The first electrode EL1 can be used in the display area DA (reference). Figure 3A or Figure 3B The first electrode EL1 can be connected to the first electric field line VDL in the outer region NDA, or it can be connected to the first electric field line VDL in the outer region NDA. When the first electrode EL1 is connected to the first electric field line VDL in the outer region NDA, the first electric field line VDL can be located in the outer region NDA (see reference). Figure 3A or Figure 3B In the NDA region, the first electrode EL1 can extend to the peripheral region NDA.

[0253] exist Figure 5 In the cross-sectional view, the first electrode EL1 overlaps with the light-emitting opening OP-PDL but not with the groove GV; however, the embodiment should not be limited thereto or thereby restricted. (See reference...) Figure 4D The first electrodes EL1 of the light-emitting elements LD can be integrally provided with each other and can have a grid shape or lattice shape in which openings are defined in some areas. That is, the first electrodes EL1 can have a variety of shapes, as long as the light-emitting elements LD receive the same first electrical voltage VDD through their first electrodes EL1; however, the embodiments should not be limited to this or thereby restricted.

[0254] An intermediate layer IML can be disposed between the first electrode EL1 and the second electrode EL2. The intermediate layer IML may include a light-emitting layer EML and a functional layer FNL having a size larger than that of the light-emitting layer EML. The light-emitting element LD may include an intermediate layer IML with various structures and should not be particularly limited. As an example, the functional layer FNL may include multiple layers, or may include two or more layers spaced apart from each other, with the light-emitting layer EML situated between the two or more layers.

[0255] The light-emitting layer (EML) may include organic light-emitting materials. According to embodiments, the EML may include inorganic light-emitting materials or may include a layer obtained by mixing organic and inorganic light-emitting materials. In embodiments, the EMLs included in adjacent light-emitting portions (EPs) may include light-emitting materials displaying different colors from each other. As an example, the EML included in each light-emitting portion (EP) may emit light having at least one color selected from blue, red, and green; however, embodiments should not be limited thereto. According to embodiments, the EMLs commonly disposed in the light-emitting portions (EPs) may include light-emitting materials displaying the same color. The EML may provide blue or white light.

[0256] The functional layer FNL can be disposed between the first electrode EL1 and the second electrode EL2. Specifically, the functional layer FNL may include a first intermediate functional layer disposed between the first electrode EL1 and the light-emitting layer EML, and a second intermediate functional layer disposed between the second electrode EL2 and the light-emitting layer EML. According to an embodiment, either the first or second intermediate functional layer may be omitted. In an embodiment, the light-emitting layer EML can be inserted into the functional layer FNL. That is, the light-emitting layer EML can be disposed between the first and second intermediate functional layers.

[0257] The functional layer FNL can control the movement of charge between the first electrode EL1 and the second electrode EL2. As an example, the first intermediate functional layer may include a hole injection / transport material and / or an electron injection / transport material. The second intermediate functional layer may include at least one of an electron blocking layer, a hole transport layer, a hole injection layer, a hole blocking layer, an electron transport layer, an electron injection layer, and a charge generation layer.

[0258] The second electrode EL2 can be disposed on the intermediate layer IML. As described above, the second electrode EL2 can be electrically connected to the pixel driving unit PDC via the connection electrode CNE. In an embodiment, the second electrode EL2 can be electrically connected to the connection transistor TR via the connection electrode CNE.

[0259] The encapsulation layer ECL can be disposed on the light-emitting element layer LDL. The encapsulation layer ECL can cover the light-emitting element LD and the recess GV. The encapsulation layer ECL may include a first inorganic layer IL1, an organic layer OL, and a second inorganic layer IL2, which are stacked sequentially.

[0260] However, this disclosure should not be limited thereto or thereby. According to embodiments, the encapsulation layer ECL may further include multiple inorganic layers and multiple organic layers. As an example, the encapsulation layer ECL may include a first encapsulation layer instead of a first inorganic layer. The first encapsulation layer may include sub-encapsulation layers. At least one of the sub-encapsulation layers may include an organic material. As an example, the first encapsulation layer may include a first sub-encapsulation layer, a second sub-encapsulation layer, and a third sub-encapsulation layer, the first and third sub-encapsulation layers may include inorganic materials, and the second sub-encapsulation layer may include an organic material. Even if a gap is formed in the first sub-encapsulation layer, which is an inorganic material layer, the gap may be filled by the second sub-encapsulation layer. The first encapsulation layer may smoothly cover the groove GV defined in the pixel defining layer PDL and the tip portion TP of the connecting electrode CNE. Therefore, the protective function of the encapsulation layer ECL protecting the light-emitting element LD can be improved. However, this disclosure should not be limited thereto or thereby, and the encapsulation layer ECL may be a glass substrate.

[0261] The first inorganic layer IL1 and the second inorganic layer IL2 protect the light-emitting element (LD) from moisture and oxygen outside the display panel (DP), and the organic layer OL protects the LD from foreign matter such as dust particles remaining from the process of forming the first inorganic layer IL1. The first inorganic layer IL1 and the second inorganic layer IL2 may comprise a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The organic layer OL may comprise an acrylic organic layer; however, the embodiments should not be particularly limited.

[0262] The sensing layer ISL can sense external input. The sensing layer ISL can be formed on the encapsulation layer ECL via a continuous process. The sensing layer ISL can also be directly disposed on the encapsulation layer ECL. In this disclosure, the statement "the sensing layer ISL is directly disposed on the encapsulation layer ECL" means that there is no intermediary element between the sensing layer ISL and the encapsulation layer ECL. That is, a separate adhesive member may not be provided between the sensing layer ISL and the encapsulation layer ECL; however, this is merely an example. According to embodiments, the sensing layer ISL can be provided after separate formation and can be coupled to the display panel DP via an adhesive member, and embodiments should not be limited thereto or thereby restricted.

[0263] The sensing layer ISL may include a conductive layer and an insulating layer. The conductive layer may include a first sensing conductive layer MTL1 and a second sensing conductive layer MTL2, and the insulating layer may include a first sensing insulating layer 71, a second sensing insulating layer 72, and a third sensing insulating layer 73. However, this is merely an example, and the number of insulating layers should not be particularly limited.

[0264] Each of the first sensing insulating layer 71, the second sensing insulating layer 72, and the third sensing insulating layer 73 may have a single-layer structure or a multilayer structure of multiple layers stacked on the third-direction DR3. The first sensing insulating layer 71, the second sensing insulating layer 72, and the third sensing insulating layer 73 may include an inorganic layer. The inorganic layer may include at least one of alumina, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. The first sensing insulating layer 71, the second sensing insulating layer 72, and the third sensing insulating layer 73 may include an organic layer. The organic layer may include at least one of acrylic resins, methacrylic resins, polyisoprene resins, vinyl resins, epoxy resins, urethane resins, cellulose resins, siloxane resins, polyimide resins, polyamide resins, and perylene resins.

[0265] A first sensing conductive layer MTL1 may be disposed between a first sensing insulating layer 71 and a second sensing insulating layer 72, and a second sensing conductive layer MTL2 may be disposed between the second sensing insulating layer 72 and a third sensing insulating layer 73. A portion of the second sensing conductive layer MTL2 may be connected to the first sensing conductive layer MTL1 via a contact hole CNT formed through the second sensing insulating layer 72. Each of the first sensing conductive layer MTL1 and the second sensing conductive layer MTL2 may have a single-layer structure or a multilayer structure of multiple layers stacked on a third-direction DR3.

[0266] The sensing conductive layer with a single-layer structure may include a metal layer or a transparent conductive layer. The metal layer may include molybdenum, silver, titanium, copper, aluminum, or alloys thereof. The transparent conductive layer may include transparent conductive oxides, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium zinc tin oxide (IZTO). Furthermore, the transparent conductive layer may include conductive polymers (such as poly(3,4-ethylenedioxythiophene) (PEDOT)), metal nanowires, or graphene.

[0267] A multilayer sensing conductive layer may include a metal layer. The metal layer may have a three-layer structure of titanium (Ti) / aluminum (Al) / titanium (Ti). A multilayer sensing conductive layer may include at least one metal layer and at least one transparent conductive layer.

[0268] The first sensing conductive layer MTL1 and the second sensing conductive layer MTL2 can form a sensor to sense external inputs in the sensing layer ISL. The sensor can be driven by a capacitive method (e.g., a mutual capacitance method or a self-capacitance method); however, this is merely an example. According to embodiments, the sensor can be driven by a resistive film method, an ultrasonic method, or an infrared method instead of a capacitive method, and the embodiments should not be particularly limited.

[0269] Each of the first sensing conductive layer MTL1 and the second sensing conductive layer MTL2 may include a transparent conductive oxide, or may have a metal mesh shape formed of an opaque conductive material. The first sensing conductive layer MTL1 and the second sensing conductive layer MTL2 may include various materials and various shapes, as long as the visibility of the image displayed by the display panel DP is not degraded.

[0270] Figure 6A Display panel DP (reference) according to embodiments of the present disclosure Figure 5 A magnified schematic cross-sectional view of the region. Figure 6A yes Figure 5 Enlarged cross-sectional view of region AA'.

[0271] refer to Figure 5 and Figure 6A The connection electrode CNE may include a first connection electrode layer LL1 disposed on the pixel defining layer PDL and a second connection electrode layer LL2 disposed on the first connection electrode layer LL1. The second connection electrode layer LL2 may cover the first connection electrode layer LL1. As an example, the second connection electrode layer LL2 may cover the upper surface and side surface S_LL1 of the first connection electrode layer LL1. Therefore, the side surface S_LL1 of the first connection electrode layer LL1 may not be exposed to the outside. The end of the first connection electrode layer LL1 and the end of the second connection electrode layer LL2 covering the end of the first connection electrode layer LL1 may form the tip portion TP of the connection electrode CNE.

[0272] The second connecting electrode layer LL2 can be patterned through the end of the first connecting electrode layer LL1, and a portion of the second connecting electrode layer LL2 can be disposed in the groove GV. Since the second connecting electrode layer LL2 is disposed on and patterned on the first connecting electrode layer LL1, the connecting electrode CNE can have a reverse tapered shape. As an example, the tapering angle between the lower surface of the first connecting electrode layer LL1 and the side surface S_LL1 of the first connecting electrode layer LL1 can be an acute angle or a right angle. Since the second connecting electrode layer LL2 is patterned through the protruding end of the first connecting electrode layer LL1, the second connecting electrode layer LL2 can smoothly cover the side surface S_LL1 of the first connecting electrode layer LL1, and the tip portion TP of the connecting electrode CNE can have a reverse tapered shape.

[0273] The first connecting electrode layer LL1 and the second connecting electrode layer LL2 may include transparent conductive oxides (TCOs), such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), or indium oxide (In2O3), etc. However, the materials used for the first connecting electrode layer LL1 and the second connecting electrode layer LL2 should not be limited thereto or restricted thereto.

[0274] An intermediate layer IML can be disposed on the second connecting electrode layer LL2. The intermediate layer IML can cover the upper surface of the second connecting electrode layer LL2 and a portion of the side surface S_LL2 of the second connecting electrode layer LL2. The intermediate layer IML can be patterned by the tip portion TP of the connecting electrode CNE, and a portion of the intermediate layer IML can be disposed in the groove GV.

[0275] The second electrode EL2 can be disposed on the intermediate layer IML. The second electrode EL2 can cover the upper surface and side surface S_IML of the intermediate layer IML. The second electrode EL2 can be patterned via the tip portion TP of the connecting electrode CNE, and a portion of the second electrode EL2 can be disposed in the groove GV. The second electrode EL2 can be connected to or contact the second connecting electrode layer LL2. As an example, at the tip portion TP of the connecting electrode CNE, the portions of the second electrode EL2 and the second connecting electrode layer LL2 not covered by the intermediate layer IML can be connected to or contact each other.

[0276] A dummy pattern (DMP) can be set in the groove (GV). The dummy pattern (DMP) may include a first separator pattern (PP1), a second separator pattern (PP2), and a third separator pattern (PP3).

[0277] The first separator pattern PP1 may be made of the same material as the second connecting electrode layer LL2. The first separator pattern PP1 may be formed substantially simultaneously with the second connecting electrode layer LL2 by a single process, and may be separated from the second connecting electrode layer LL2 by the ends of the first connecting electrode layer LL1.

[0278] The second separator pattern PP2 may be made of the same material as the intermediate layer IML. The second separator pattern PP2 may be formed substantially simultaneously with the intermediate layer IML by a single process, and may be separated from the intermediate layer IML by the tip portion TP of the connecting electrode CNE.

[0279] The third separator pattern PP3 may be made of the same material as the second electrode EL2. The third separator pattern PP3 may be formed substantially simultaneously with the second electrode EL2 by a single process and may be separated from the second electrode EL2 by the tip portion TP of the connecting electrode CNE. The first separator pattern PP1 may be electrically connected to the third separator pattern PP3 in the groove GV.

[0280] Figure 6B Display panel DP (reference) according to embodiments of the present disclosure Figure 3A An enlarged schematic plan view of the area, and Figure 6C Display panel DP (reference) according to embodiments of the present disclosure Figure 3A A magnified schematic cross-sectional view of the region. Figure 6B yes Figure 3A An enlarged plan view of region XX', and Figure 6C It is along Figure 6B An enlarged schematic cross-sectional view of the line Y-Y'. Figure 6B and Figure 6C The outer portion of the display panel DP is shown.

[0281] refer to Figures 6A to 6C Also refer to Figure 2A The connecting electrode CNE does not need to be located in the display area DA of the display panel DP (see reference). Figure 3A ) and non-display area NDA (reference) Figure 3A At the boundary between the display area DA and the non-display area NDA. That is, a portion of the tip portion TP of the connecting electrode CNE may not be formed in the outer portion of the display panel DP. In other embodiments of the present invention, the tip portion N_TP of the connecting electrode CNE (hereinafter referred to as the outer tip portion N_TP) formed in the outer portion of the display panel DP may be formed adjacent to the area in which the light-emitting portions EP1, EP2 and EP3 are disposed, and may not be formed in the area in which the light-emitting portions EP1, EP2 and EP3 are not disposed. The outer groove N_GV may be formed in the area in which the outer tip portion N_TP is not formed. The outer groove N_GV may be formed along the boundary between the display area DA and the non-display area NDA. The outer groove N_GV may have a shape connected to the groove GV formed between the light-emitting portions EP1, EP2 and EP3.

[0282] The outer dummy pattern N_DMP can be set in the outer groove N_GV. The outer dummy pattern N_DMP may include a first outer separator pattern N_PP1, a second outer separator pattern N_PP2, and a third outer separator pattern N_PP3.

[0283] The first outer separator pattern N_PP1 may comprise the same material as the second connecting electrode layer LL2. The first outer separator pattern N_PP1 may be formed substantially simultaneously with the second connecting electrode layer LL2 in a single process, and may be separated from the second connecting electrode layer LL2 through an end of the first connecting electrode layer LL1. The first outer separator pattern N_PP1 may be attached to the first separator pattern PP1, and may be provided integrally with the first separator pattern PP1.

[0284] The second outer separator pattern N_PP2 may comprise the same material as the intermediate layer IML. The second outer separator pattern N_PP2 can be formed substantially simultaneously with the intermediate layer IML via a single process, and can be separated from the intermediate layer IML via the outer tip portion N_TP of the connecting electrode CNE. The second outer separator pattern N_PP2 may be attached to the second separator pattern PP2, and may be provided integrally with the second separator pattern PP2.

[0285] The third outer separator pattern N_PP3 may be made of the same material as the second electrode EL2. The third outer separator pattern N_PP3 may be formed substantially simultaneously with the second electrode EL2 in a single process, and may be separated from the second electrode EL2 by the outer tip portion N_TP of the connecting electrode CNE. The third outer separator pattern N_PP3 may be attached to the third separator pattern PP3, and may be provided integrally with the third separator pattern PP3.

[0286] A first electrical voltage VDD, acting as a constant voltage, can be applied to the third outer partition pattern N_PP3. The first outer partition pattern N_PP1 can be electrically connected to the third outer partition pattern N_PP3 within the outer groove N_GV, and therefore, the first electrical voltage VDD can be applied to the first outer partition pattern N_PP1. Since the outer groove N_GV has a shape that connects to the groove GV formed between the light-emitting portions EP1, EP2, and EP3, the first electrical voltage VDD can be applied to the first partition pattern PP1 and the third partition pattern PP3 disposed within the groove GV.

[0287] According to an embodiment, when a first power voltage VDD, which is a constant voltage, is applied to the first partition pattern PP1 and the first outer partition pattern N_PP1, noise coupling caused by the first partition pattern PP1 and the first outer partition pattern N_PP1 can be reduced or eliminated.

[0288] Figure 7 This is an enlarged schematic cross-sectional view of a region of a display panel according to an embodiment of the present disclosure. Figure 7 yes Figure 5 An enlarged cross-sectional view of region AA'. Figure 7 In the figures, the same / similar reference numerals indicate... Figures 1 to 6CThe same / similar elements in the text will be omitted, and therefore, detailed descriptions of the same elements will be omitted.

[0289] refer to Figure 5 and Figure 7 The connection electrode CNEa can be disposed on the pixel defining layer PDL. The connection electrode CNEa can be electrically connected to the pixel driving unit PDC and the light-emitting element LD. The connection electrode CNEa may include a first connection electrode layer LL1 disposed on the pixel defining layer PDL. That is, the connection electrode CNEa can have the capability to connect from... Figure 6A The second connection electrode layer LL2 is removed from the CNE connection electrode (reference). Figure 6A The structure obtained is as follows. The end of the first connecting electrode layer LL1 may form the tip portion TPa of the connecting electrode CNEa. The taper angle between the lower surface of the connecting electrode CNEa and the side surface of the connecting electrode CNEa may be an acute angle or a right angle. However, this disclosure should not be limited to or restricted by this, and the tip portion TPa may have a reverse taper shape.

[0290] An intermediate layer IML can be disposed on the first connecting electrode layer LL1. The intermediate layer IML can cover the upper surface of the first connecting electrode layer LL1 and a portion of the side surface S_LL1 of the first connecting electrode layer LL1. The intermediate layer IML can be patterned by the tip portion TPa of the connecting electrode CNEa, and a portion of the intermediate layer IML can be disposed in the groove GV.

[0291] The second electrode EL2 can be disposed on the intermediate layer IML. The second electrode EL2 can cover the upper surface and side surface S_IML of the intermediate layer IML. The second electrode EL2 can be patterned at the tip portion TPa of the connecting electrode CNEa, and a portion of the second electrode EL2 can be disposed in the groove GV. The second electrode EL2 can be connected to or contact the first connecting electrode layer LL1. As an example, at the tip portion TPa of the connecting electrode CNEa, the end of the second electrode EL2 can be connected to or contact the portion of the end of the first connecting electrode layer LL1 not covered by the intermediate layer IML.

[0292] A dummy pattern DMPa can be set in the groove GV. The dummy pattern DMPa may include a first separator pattern PP1a and a second separator pattern PP2a.

[0293] The first separator pattern PP1a may be made of the same material as the intermediate layer IML. The first separator pattern PP1a may be formed substantially simultaneously with the intermediate layer IML by a single process, and may be separated from the intermediate layer IML by the tip portion TPa of the connecting electrode CNEa.

[0294] The second separator pattern PP2a may be made of the same material as the second electrode EL2. The second separator pattern PP2a may be formed substantially simultaneously with the second electrode EL2 by a single process, and may be separated from the second electrode EL2 by the tip portion TPa of the connecting electrode CNEa.

[0295] Figure 8 This is an enlarged schematic cross-sectional view of a region of a display panel according to an embodiment of the present disclosure. Figure 8 yes Figure 5 An enlarged cross-sectional view of region AA'. Figure 8 In the figures, the same / similar reference numerals indicate... Figures 1 to 7 The same / similar elements in the text will be omitted, and therefore, detailed descriptions of the same elements will be omitted.

[0296] refer to Figure 5 and Figure 8 The pixel defining layer PDLa may include a first pixel defining layer portion PDL1 and a second pixel defining layer portion PDL2. The first pixel defining layer portion PDL1 and the second pixel defining layer portion PDL2 can be formed in a single process and can have a single body. The first pixel defining layer portion PDL1 may be disposed on the sixth insulating layer 60, and the second pixel defining layer portion PDL2 may be disposed on the first pixel defining layer portion PDL1. The first pixel defining layer portion PDL1 may correspond to... Figure 6A The second pixel-defining layer portion PDL2 may have a shape that protrudes from the first pixel-defining layer portion PDL1 in the thickness direction (e.g., third direction DR3). A groove GV may be defined in the second pixel-defining layer portion PDL2.

[0297] A connection electrode CNEb can be disposed on the pixel defining layer PDLa. The connection electrode CNEb electrically connects the pixel driving unit PDC to the light-emitting element LD. The connection electrode CNEb may include a first connection electrode layer LL1a disposed on the pixel defining layer PDLa and a second connection electrode layer LL2a disposed on the first connection electrode layer LL1a. The second connection electrode layer LL2a may cover the first connection electrode layer LL1a. As an example, the second connection electrode layer LL2a may cover the upper surface and side surface S_LL1a of the first connection electrode layer LL1a. Therefore, the side surface S_LL1a of the first connection electrode layer LL1a may not be exposed to the outside. The end of the first connection electrode layer LL1a and the end of the second connection electrode layer LL2a covering the end of the first connection electrode layer LL1a may form the tip portion TPb of the connection electrode CNEb.

[0298] The second connecting electrode layer LL2a can be patterned through the end of the first connecting electrode layer LL1a, and a portion of the second connecting electrode layer LL2a can be disposed in the groove GV. Since the second connecting electrode layer LL2a is disposed on and patterned on the first connecting electrode layer LL1a, the connecting electrode CNEb can have a reverse tapered shape. As an example, the tapering angle between the lower surface of the first connecting electrode layer LL1a and the side surface S_LL1a of the first connecting electrode layer LL1a can be an acute angle or a right angle. Since the second connecting electrode layer LL2a is patterned through the protruding end of the first connecting electrode layer LL1a, the second connecting electrode layer LL2a can smoothly cover the side surface S_LL1a of the first connecting electrode layer LL1a, and the tip portion TPb of the connecting electrode CNEb can have a reverse tapered shape. In addition, since the pixel defining layer PDLa includes a second pixel defining layer portion PDL2 that protrudes from the first pixel defining layer portion PDL1, the tip portion TPb of the connecting electrode CNEb can have a reverse tapered shape through the slope of the second pixel defining layer portion PDL2.

[0299] The first connecting electrode layer LL1a and the second connecting electrode layer LL2a may include transparent conductive oxides (TCOs), such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), or indium oxide (In2O3), etc. However, the materials used for the first connecting electrode layer LL1a and the second connecting electrode layer LL2a should not be limited thereto or restricted thereto.

[0300] An intermediate layer IML can be disposed on the second connecting electrode layer LL2a. The intermediate layer IML can cover the upper surface of the second connecting electrode layer LL2a and a portion of the side surface S_LL2a of the second connecting electrode layer LL2a. The intermediate layer IML can be patterned through the tip portion TPb of the connecting electrode CNEb, and a portion of the intermediate layer IML can be disposed in the groove GV.

[0301] The second electrode EL2 can be disposed on the intermediate layer IML. The second electrode EL2 can cover the upper surface and side surface S_IML of the intermediate layer IML. The second electrode EL2 can be patterned through the tip portion TPb of the connecting electrode CNEb, and a portion of the second electrode EL2 can be disposed in the groove GV. The second electrode EL2 can be connected to or contact the second connecting electrode layer LL2a. As an example, at the tip portion TPb of the connecting electrode CNEb, the end of the second electrode EL2 can be connected to or contact the portion of the end of the second connecting electrode layer LL2a not covered by the intermediate layer IML.

[0302] A dummy pattern DMPb can be set in the groove GV. The dummy pattern DMPb may include a first separator pattern PP1, a second separator pattern PP2, and a third separator pattern PP3. The first separator pattern PP1, the second separator pattern PP2, and the third separator pattern PP3 can be respectively... Figure 6A The first dividing pattern PP1, the second dividing pattern PP2, and the third dividing pattern PP3 are basically the same.

[0303] Figure 9 This is an enlarged schematic cross-sectional view of a region of a display panel according to an embodiment of the present disclosure. Figure 9 yes Figure 5 An enlarged cross-sectional view of region AA'. Figure 9 In the figures, the same / similar reference numerals indicate... Figures 1 to 8 The same / similar elements are included, therefore, detailed descriptions of identical elements will be omitted.

[0304] refer to Figure 5 and Figure 9 The pixel defining layer PDLa may include a first pixel defining layer portion PDL1 and a second pixel defining layer portion PDL2. A connecting electrode CNEc may be disposed on the pixel defining layer PDLa. The connecting electrode CNEc can electrically connect the pixel driving unit PDC to the light-emitting element LD. The connecting electrode CNEc may include a first connecting electrode layer LL1a disposed on the pixel defining layer PDLa. That is, the connecting electrode CNEc may have the ability to connect via... Figure 8 The second connecting electrode layer LL2a is omitted from the connecting electrode CNEb (reference). Figure 8 The structure obtained is as follows. The end of the first connecting electrode layer LL1a can form the tip portion TPc of the connecting electrode CNEC. The taper angle between the lower surface of the connecting electrode CNEC and the side surface of the connecting electrode CNEC can be an acute angle or a right angle; however, this disclosure should not be limited to or construed as such. According to an embodiment, the tip portion TPc can have a reverse taper shape. As an example, since the pixel defining layer PDLa includes a second pixel defining layer portion PDL2 protruding from the first pixel defining layer portion PDL1, the tip portion TPc of the connecting electrode CNEC can have a reverse taper shape through the ramp of the second pixel defining layer portion PDL2.

[0305] An intermediate layer IML can be disposed on the first connecting electrode layer LL1a. The intermediate layer IML can cover the upper surface and side surface S_LL1a of the first connecting electrode layer LL1a. The intermediate layer IML can be patterned by the tip portion TPc of the connecting electrode CNEc, and a portion of the intermediate layer IML can be disposed in the groove GV.

[0306] The second electrode EL2 can be disposed on the intermediate layer IML. The second electrode EL2 can cover the upper surface and side surface S_IML of the intermediate layer IML. The second electrode EL2 can be patterned via the tip portion TPc of the connecting electrode CNEc, and a portion of the second electrode EL2 can be disposed in the groove GV. The second electrode EL2 can be connected to or contact the first connecting electrode layer LL1a. As an example, at the tip portion TPc of the connecting electrode CNEc, the end of the second electrode EL2 can be connected to or contact the portion of the end of the first connecting electrode layer LL1a not covered by the intermediate layer IML.

[0307] A dummy pattern DMPc can be set in the groove GV. The dummy pattern DMPc can include a first separator pattern PP1a and a second separator pattern PP2a. The first separator pattern PP1a and the second separator pattern PP2a can be respectively connected to... Figure 7 The first dividing pattern PP1a and the second dividing pattern PP2a are basically the same.

[0308] Figures 10A to 10F This is a schematic cross-sectional view illustrating the process of manufacturing a display panel according to an embodiment of the present disclosure. Figures 10A to 10F In the figures, the same / similar reference numerals indicate... Figures 1 to 9 Identical / similar elements will be included, and therefore, detailed descriptions of identical elements will be omitted. Figures 10A to 10F The display panel manufactured by the manufacturing method shown can correspond to Figure 6A The display panel shown.

[0309] According to this disclosure, a method for manufacturing a display panel may include: preparing a preliminary display panel comprising a substrate layer, a driving element layer disposed on the substrate layer, and a pixel defining layer disposed on the driving element layer; depositing a first connection electrode layer on the preliminary display panel; etching a portion of the first connection electrode layer and a portion of the pixel defining layer to form a groove in the pixel defining layer that overlaps with a portion of the first connection electrode layer; etching the first connection electrode layer to form a connection electrode; and forming an intermediate layer and a cathode on the connection electrode and the pixel defining layer.

[0310] refer to Figure 10A The method for manufacturing a display panel may include preparing a preliminary display panel DP_I and depositing a first interconnect electrode layer LL1. The preliminary display panel DP_I may include a substrate layer BS, a driving element layer DDL disposed on the substrate layer BS, and a pixel defining layer PDL disposed on the driving element layer DDL.

[0311] The substrate layer (BS) can provide the substrate surface, and the pixel driving unit (PDC) (reference) Figure 5 The driving element layer (DDL) is disposed on the surface of the substrate. The DDL can be formed using conventional manufacturing processes for circuit elements, in which insulating layers, conductive layers, and semiconductor layers are formed by coating and deposition processes, and the insulating layers, semiconductor layers, and conductive layers are selectively patterned by photolithography and etching processes to form semiconductor patterns, conductive patterns, and signal lines. The driving element layer (DDL) may include a first insulating layer 10, a second insulating layer 20, a third insulating layer 30, a fourth insulating layer 40, a fifth insulating layer 50, and a sixth insulating layer 60 (see reference) sequentially stacked on the substrate layer BS. Figure 5 ) and pixel drive unit (PDC).

[0312] A pixel-defining layer (PDL) can be formed on the driving element layer (DDL). An open-ended pixel-defining layer (OP-PDL) can be formed by depositing a preliminary pixel-defining layer on the driving element layer (DDL) and selectively patterning the preliminary pixel-defining layer using photolithography and etching processes (see reference). Figure 5 ) and through-hole OP-P (reference) Figure 5 ) pixel-limited layer PDL.

[0313] A first connection electrode layer LL1 can be deposited on the initial display panel DP_I. The deposition of the first connection electrode layer LL1 can be performed by a process of depositing a conductive material. The conductive material used to form the first connection electrode layer LL1 may include transparent conductive oxides (TCOs), such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), or indium oxide (In2O3), however, the material used for the first connection electrode layer LL1 should not be limited to or restricted by this.

[0314] A method for manufacturing a display panel may include forming a first photoresist layer PR1. The first photoresist layer PR1 may be formed on a first connecting electrode layer LL1. The first photoresist layer PR1 may be formed by forming a preliminary photoresist layer on the first connecting electrode layer LL1 and patterning the preliminary photoresist layer using a photomask. Through a patterning process, the first photoresist layer PR1, which defines a first light aperture OP_PR1, can be formed.

[0315] refer to Figure 10B and Figure 10C The manufacturing method of the display panel may include forming a recess GV for a pixel defining layer PDL, the recess GV overlapping a portion of a first connecting electrode layer LL1.

[0316] refer to Figure 10BThe formation of the groove GV of the pixel defining layer PDL may include etching a portion of the first connecting electrode layer LL1. The etching process for the first connecting electrode layer LL1 may be a wet etching process. The portion of the first connecting electrode layer LL1 can be removed by the wet etching process, and thus, a first opening OP_LL1 can be formed through the first connecting electrode layer LL1. The first opening OP_LL1 may overlap with a first optical opening OP_PR1 of the first photoresist layer PR1. The end of the first connecting electrode layer LL1 defining the first opening OP_LL1 may have a tapered shape. As an example, the tapering angle between the lower surface and the side surface of the first connecting electrode layer LL1 may be an acute angle or a right angle; however, embodiments should not be limited to or construed as such.

[0317] refer to Figure 10C The formation of the groove GV in the pixel defining layer PDL may include etching a portion of the pixel defining layer PDL. The etching process for the pixel defining layer PDL may be a dry etching process. The portion of the pixel defining layer PDL can be removed by a dry etching process, and the groove GV can be formed in the pixel defining layer PDL. The groove GV may overlap with the first opening OP_LL1 of the first connecting electrode layer LL1 and the first photoresist layer PR1. The groove GV may overlap with a portion of the first connecting electrode layer LL1. That is, the portion of the first connecting electrode layer LL1 may protrude from the end of the groove GV towards the center of the groove GV.

[0318] refer to Figure 10D The manufacturing method of the display panel may include: removing the first photoresist layer PR1 (reference). Figure 10C ); depositing a second connecting electrode layer LL2; and forming a tip portion TP.

[0319] A second connection electrode layer LL2 can be deposited on the first connection electrode layer LL1. The deposition of the second connection electrode layer LL2 can be performed using a process that deposits a conductive material. The conductive material used to form the second connection electrode layer LL2 can include transparent conductive oxides (TCOs), such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), or indium oxide (In2O3), however, the material used for the second connection electrode layer LL2 should not be limited to or restricted by these. The tip portion TP can be defined by the end of the first connection electrode layer LL1 and the end of the second connection electrode layer LL2 that covers the end of the first connection electrode layer LL1.

[0320] The second connecting electrode layer LL2 can be patterned through the end of the first connecting electrode layer LL1, and a portion of the second connecting electrode layer LL2 can be disposed in the groove GV. The portion of the second connecting electrode layer LL2 that separates from the second connecting electrode layer LL2 through the end of the first connecting electrode layer LL1 can be defined as a first separating pattern PP1. The first separating pattern PP1 can comprise the same material as the second connecting electrode layer LL2, and the first separating pattern PP1 can be formed substantially simultaneously with the second connecting electrode layer LL2 in a single process.

[0321] A method for manufacturing a display panel may include forming a second photoresist layer PR2. The second photoresist layer PR2 may be formed on a second connection electrode layer LL2. The second photoresist layer PR2 may be formed by forming a preliminary photoresist layer on the second connection electrode layer LL2 and patterning the preliminary photoresist layer using a photomask. Through the patterning process, the second photoresist layer PR2 can be formed, and the second photoresist layer PR2 may overlap with the groove GV.

[0322] refer to Figure 10E The manufacturing method of the display panel may include etching a first connection electrode layer LL1 and a second connection electrode layer LL2 to form a connection electrode CNE. The etching process for the first connection electrode layer LL1 and the second connection electrode layer LL2 may be a wet etching process. The portion of the first connection electrode layer LL1 that is not connected to the second photoresist layer PR2 (see reference) may be etched and removed. Figure 10D The overlapping portion of the second connecting electrode layer LL2 is not with the second photoresist layer PR2 (reference). Figure 10D The overlapping portion. The remaining first connecting electrode layer LL1 and the second connecting electrode layer LL2, which overlap with the second photoresist layer PR2, can form the connecting electrode CNE. The second photoresist layer PR2 can be removed.

[0323] refer to Figure 10F The manufacturing method of the display panel may include forming an intermediate layer IML and a second electrode EL2 (or cathode) on a connecting electrode CNE and a pixel defining layer PDL. The formation of the intermediate layer IML and the second electrode EL2 can be performed by a deposition process.

[0324] The intermediate layer IML can be patterned via the tip portion TP of the connecting electrode CNE, and a portion of the intermediate layer IML can be disposed in the groove GV. The portion of the intermediate layer IML separated from the intermediate layer IML by the tip portion TP of the connecting electrode CNE can be defined as a second separator pattern PP2. The second separator pattern PP2 can comprise the same material as the intermediate layer IML, and the second separator pattern PP2 can be formed substantially simultaneously with the intermediate layer IML in a single process.

[0325] The second electrode EL2 can be patterned via the tip portion TP of the connecting electrode CNE, and a portion of the second electrode EL2 can be disposed in the groove GV. The portion of the second electrode EL2 separated from the second electrode EL2 by the tip portion TP of the connecting electrode CNE can be defined as a third separator pattern PP3. The third separator pattern PP3 can comprise the same material as the second electrode EL2, and the third separator pattern PP3 can be formed substantially simultaneously with the second electrode EL2 in a single process. The first separator pattern PP1, the second separator pattern PP2, and the third separator pattern PP3 can form a dummy pattern DMP.

[0326] Figures 11A to 11C This is a schematic cross-sectional view illustrating the process of manufacturing a display panel according to an embodiment of the present disclosure. Figures 11A to 11C In the figures, the same / similar reference numerals indicate... Figures 1 to 10F Identical / similar elements will be included, and therefore, detailed descriptions of identical elements will be omitted. Figures 11A to 11C The display panel manufactured by the manufacturing method shown can correspond to Figure 7 The display panel shown.

[0327] refer to Figures 11A to 11C The manufacturing method of the display panel may include: preparing a preliminary display panel DP_I (reference) Figure 10A ); depositing a first connecting electrode layer LL1; and forming a recess GV for a pixel defining layer PDL to overlap a portion of the first connecting electrode layer LL1. Preliminary display panel DP_I (reference) Figure 10A The fabrication of the first connecting electrode layer LL1, the deposition of the first connecting electrode layer LL1, and the formation of the groove GV of the pixel limiting layer PDL overlapping a portion of the first connecting electrode layer LL1 can be combined with... Figures 10A to 10C The fabrication of the initial display panel DP_I, the deposition of the first connecting electrode layer LL1, and the formation of the groove GV of the pixel limiting layer PDL that overlaps with a portion of the first connecting electrode layer LL1 are essentially the same.

[0328] refer to Figure 11A The manufacturing method of the display panel may include: forming a tip portion TPa; and removing the first photoresist layer PR1 (reference 1). Figure 10C Then a second photoresist layer PR2 is formed. The tip portion TPa can be defined by the end of the first connecting electrode layer LL1.

[0329] A second photoresist layer PR2 can be formed on the first connecting electrode layer LL1. The second photoresist layer PR2 can be formed by forming a preliminary photoresist layer on the first connecting electrode layer LL1 and patterning the preliminary photoresist layer using a photomask. Through the patterning process, the second photoresist layer PR2 overlapping with the groove GV can be formed.

[0330] refer to Figure 11B The manufacturing method of the display panel may include etching a first connection electrode layer LL1 to form a connection electrode CNEa. The etching process for the first connection electrode layer LL1 may be a wet etching process. The portion of the first connection electrode layer LL1 that is not connected to the second photoresist layer PR2 (see reference) may be etched and removed. Figure 11A The overlapping portion, and the remaining portion overlapping with the second photoresist layer PR2, can form the first connecting electrode CNEa. The second photoresist layer PR2 can be removed.

[0331] refer to Figure 11C The manufacturing method of the display panel may include forming an intermediate layer IML and a second electrode EL2 (or cathode) on a connecting electrode CNEa and a pixel defining layer PDL. The formation of the intermediate layer IML and the second electrode EL2 can be performed by a deposition process.

[0332] The intermediate layer IML can be patterned via the tip portion TPa of the connecting electrode CNEa, and a portion of the intermediate layer IML can be disposed in the groove GV. The portion of the intermediate layer IML separated from the intermediate layer IML by the tip portion TPa of the connecting electrode CNEa can be defined as a first separator pattern PP1a. The first separator pattern PP1a can comprise the same material as the intermediate layer IML, and the first separator pattern PP1a can be formed substantially simultaneously with the intermediate layer IML in a single process.

[0333] The second electrode EL2 can be patterned via the tip portion TPa of the connecting electrode CNEa, and a portion of the second electrode EL2 can be disposed in the groove GV. The portion of the second electrode EL2 separated from the second electrode EL2 by the tip portion TPa of the connecting electrode CNEa can be defined as a second separator pattern PP2a. The second separator pattern PP2a can comprise the same material as the second electrode EL2, and the second separator pattern PP2a can be formed substantially simultaneously with the second electrode EL2 in a single process. The first separator pattern PP1a and the second separator pattern PP2a can form a dummy pattern DMPa.

[0334] Figures 12A to 12F This is a schematic cross-sectional view illustrating the process of manufacturing a display panel according to an embodiment of the present disclosure. Figures 12A to 12FIn the figures, the same / similar reference numerals indicate... Figures 1 to 11C Identical / similar elements will be included, and therefore, detailed descriptions of identical elements will be omitted. Figures 12A to 12F The display panel manufactured by the manufacturing method shown can correspond to Figure 8 The display panel shown.

[0335] refer to Figure 12A The method for manufacturing a display panel may include: preparing a preliminary display panel DPa_I; and depositing a first connecting electrode layer LL1a. The preliminary display panel DPa_I may include a substrate layer BS, a driving element layer DDL disposed on the substrate layer BS, and a pixel defining layer PDLa disposed on the driving element layer DDL.

[0336] A pixel-defining layer PDLa can be formed on the driving element layer DDL. A preliminary pixel-defining layer can be deposited on the driving element layer DDL, and the preliminary pixel-defining layer can be selectively patterned using photolithography and etching processes. Therefore, a pixel-defining layer PDLa can be formed, comprising a first pixel-defining layer portion PDL1 and a second pixel-defining layer portion PDL2 having a shape protruding from the first pixel-defining layer portion PDL1. The first pixel-defining layer portion PDL1 and the second pixel-defining layer portion PDL2 can be formed in a single process and can have a single body. A halftone mask can be used in the process of forming the pixel-defining layer PDLa; however, the method of forming the pixel-defining layer PDLa should not be limited to or restricted by this. Furthermore, a light-emitting opening OP-PDL (see reference) can be defined through the pixel-defining layer PDLa. Figure 5 ) and through-hole OP-P (reference) Figure 5 ).

[0337] A first connection electrode layer LL1a can be deposited on the initial display panel DPa_I. Specifically, the first connection electrode layer LL1a can be deposited on the first pixel-defining layer portion PDL1 and the second pixel-defining layer portion PDL2 of the pixel-defining layer PDLa. The deposition of the first connection electrode layer LL1a can be performed by a process of depositing conductive material. The conductive material used to form the first connection electrode layer LL1a may include transparent conductive oxides (TCOs), such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), or indium oxide (In2O3), etc. However, the material used for the first connection electrode layer LL1a should not be limited to or restricted by this.

[0338] A method for manufacturing a display panel may include forming a first photoresist layer PR1. The first photoresist layer PR1 may be formed on a first connecting electrode layer LL1a. The first photoresist layer PR1 may be formed by forming a preliminary photoresist layer on the first connecting electrode layer LL1a and patterning the preliminary photoresist layer using a photomask. Through a patterning process, the first photoresist layer PR1, which defines a first light aperture OP_PR1, can be formed.

[0339] refer to Figure 12B and Figure 12C The manufacturing method of the display panel may include forming a recess GV for a pixel defining layer PDLa, the recess GV overlapping a portion of a first connecting electrode layer LL1a.

[0340] refer to Figure 12B The formation of the groove GV of the pixel defining layer PDLa may include etching a portion of the first connecting electrode layer LL1a. The etching process for the first connecting electrode layer LL1a may be a wet etching process. The portion of the first connecting electrode layer LL1a can be removed by the etching process, and thus, a first opening OP_LL1a can be formed through the first connecting electrode layer LL1a. The first opening OP_LL1a may overlap with a first optical opening OP_PR1 of the first photoresist layer PR1. The end of the first connecting electrode layer LL1a defining the first opening OP_LL1a may have a tapered shape. As an example, the tapering angle between the lower surface and the side surface of the first connecting electrode layer LL1a may be an acute angle or a right angle; however, this disclosure should not be limited to or construed as such.

[0341] refer to Figure 12C The formation of the groove GV in the pixel defining layer PDLa may include etching a portion of the pixel defining layer PDLa. The etching process for the pixel defining layer PDLa may be a dry etching process. The portion of the pixel defining layer PDLa can be removed by the etching process, and thus, the groove GV can be formed in the pixel defining layer PDLa. The groove GV may overlap with the first opening OP_LL1a of the first connecting electrode layer LL1a and the first photoresist layer PR1. The groove GV may overlap with a portion of the first connecting electrode layer LL1a. That is, the portion of the first connecting electrode layer LL1a may protrude from the end of the groove GV towards the center of the groove GV.

[0342] refer to Figure 12D The manufacturing method of the display panel may include: removing the first photoresist layer PR1 (reference). Figure 12C ); depositing a second connecting electrode layer LL2a; and forming a tip portion TPb.

[0343] A second connection electrode layer LL2a can be deposited on the first connection electrode layer LL1a. The deposition of the second connection electrode layer LL2a can be performed using a process that deposits a conductive material. The conductive material used to form the second connection electrode layer LL2a can include transparent conductive oxides (TCOs), such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), or indium oxide (In2O3), etc. However, the material used for the second connection electrode layer LL2a should not be limited to or restricted by these. The tip portion TPb can be defined by the end of the first connection electrode layer LL1a and the end of the second connection electrode layer LL2a covering the end of the first connection electrode layer LL1a.

[0344] According to this disclosure, since the second connecting electrode layer LL2a is patterned through the protruding end of the first connecting electrode layer LL1a, the second connecting electrode layer LL2a can smoothly surround the side surface S_LL1a of the first connecting electrode layer LL1a (see [link to disclosure]). Figure 8 ), and connect electrode CNEb (see Figure 8 The tip portion TPb of the electrode CNEb can have a reverse tapered shape. In addition, since the pixel defining layer PDLa includes a second pixel defining layer portion PDL2 protruding from the first pixel defining layer portion PDL1, the tip portion TPb of the electrode CNEb can have a reverse tapered shape due to the slope of the second pixel defining layer portion PDL2.

[0345] The second connecting electrode layer LL2a can be patterned through the end of the first connecting electrode layer LL1a, and a portion of the second connecting electrode layer LL2a can be disposed in the groove GV. The portion of the second connecting electrode layer LL2a that separates from the second connecting electrode layer LL2a through the end of the first connecting electrode layer LL1a can be defined as a first separating pattern PP1. The first separating pattern PP1 can comprise the same material as the second connecting electrode layer LL2a, and the first separating pattern PP1 can be formed substantially simultaneously with the second connecting electrode layer LL2a in a single process.

[0346] A method for manufacturing a display panel may include forming a second photoresist layer PR2. The second photoresist layer PR2 may be formed on a second connecting electrode layer LL2a. The second photoresist layer PR2 may be formed by forming a preliminary photoresist layer on the second connecting electrode layer LL2a and patterning the preliminary photoresist layer using a photomask. Through the patterning process, a second photoresist layer PR2 overlapping with the groove GV can be formed.

[0347] refer to Figure 12EThe manufacturing method of the display panel may include etching a first connection electrode layer LL1a and a second connection electrode layer LL2a to form a connection electrode CNEb. The etching process for the first connection electrode layer LL1a and the second connection electrode layer LL2a may be a wet etching process. The portion of the first connection electrode layer LL1a that is not bonded to the second photoresist layer PR2 (see reference) may be etched and removed. Figure 12D The overlapping portion of the second connecting electrode layer LL2a is not with the second photoresist layer PR2 (reference). Figure 12D The overlapping portion. The remaining first connecting electrode layer LL1a and the second connecting electrode layer LL2a, which overlap with the second photoresist layer PR2, can form the connecting electrode CNEb. The second photoresist layer PR2 can be removed.

[0348] refer to Figure 12F The manufacturing method of the display panel may include forming an intermediate layer IML and a second electrode EL2 (or cathode) on the connecting electrode CNEb and the pixel defining layer PDLa. Each of the formation of the intermediate layer IML and the formation of the second electrode EL2 can be performed by a deposition process.

[0349] The intermediate layer IML can be patterned via the tip portion TPb of the connecting electrode CNEb, and a portion of the intermediate layer IML can be disposed in the groove GV. The portion of the intermediate layer IML separated from the intermediate layer IML by the tip portion TPb of the connecting electrode CNEb can be defined as a second separator pattern PP2. The second separator pattern PP2 can comprise the same material as the intermediate layer IML, and the second separator pattern PP2 can be formed substantially simultaneously with the intermediate layer IML in a single process.

[0350] The second electrode EL2 can be patterned via the tip portion TPb of the connecting electrode CNEb, and a portion of the second electrode EL2 can be disposed in the groove GV. The portion of the second electrode EL2 separated from it by the tip portion TPb of the connecting electrode CNEb can be defined as a third separator pattern PP3. The third separator pattern PP3 can comprise the same material as the second electrode EL2, and the third separator pattern PP3 can be formed substantially simultaneously with the second electrode EL2 in a single process. The first separator pattern PP1, the second separator pattern PP2, and the third separator pattern PP3 can form a dummy pattern DMPb.

[0351] Figures 13A to 13C This is a schematic cross-sectional view illustrating the process of manufacturing a display panel according to an embodiment of the present disclosure. Figures 13A to 13C In the figures, the same / similar reference numerals indicate... Figures 1 to 12F Identical / similar elements will be included, and therefore, detailed descriptions of identical elements will be omitted. Figures 13A to 13CThe display panel manufactured by the manufacturing method shown can correspond to Figure 9 The display panel shown.

[0352] refer to Figures 13A to 13C The manufacturing method of the display panel may include: preparing a preliminary display panel DPa_I (reference) Figure 12A ); depositing a first connecting electrode layer LL1a; and forming a recess GV for a pixel-defining layer PDLa to overlap a portion of the first connecting electrode layer LL1a. Preliminary display panel DPa_I (reference) Figure 12A The fabrication of the first connecting electrode layer LL1a, the deposition of the first connecting electrode layer LL1a, and the formation of the groove GV of the pixel defining layer PDLa that overlaps with a portion of the first connecting electrode layer LL1a can be combined with... Figures 12A to 12C The fabrication of the initial display panel DPa_I, the deposition of the first connecting electrode layer LL1a, and the formation of the recess GV of the pixel limiting layer PDLa that overlaps with a portion of the first connecting electrode layer LL1a are essentially the same.

[0353] refer to Figure 13A The manufacturing method of the display panel may include: removing the first photoresist layer PR1 (reference). Figure 12C The process involves forming a tip portion TPc and a second photoresist layer PR2. The tip portion TPc can be defined by the end of the first connecting electrode layer LL1a.

[0354] According to this disclosure, since the pixel defining layer PDLa includes a second pixel defining layer portion PDL2 protruding from the first pixel defining layer portion PDL1, the tip portion TPc of the connecting electrode CNEc can have a reverse tapered shape due to the slope of the second pixel defining layer portion PDL2.

[0355] A second photoresist layer PR2 can be formed on the first connecting electrode layer LL1a. The second photoresist layer PR2 can be formed by forming a preliminary photoresist layer on the first connecting electrode layer LL1a and patterning the preliminary photoresist layer using a photomask. Through the patterning process, the second photoresist layer PR2, overlapping with the groove GV, can be formed.

[0356] refer to Figure 13B The manufacturing method of the display panel may include etching a first connection electrode layer LL1a to form a connection electrode CNEc. The etching process for the first connection electrode layer LL1a may be a wet etching process. The portion of the first connection electrode layer LL1a that is not connected to the second photoresist layer PR2 (see reference) may be etched and removed. Figure 13A The overlapping portion, and the remaining portion overlapping with the second photoresist layer PR2, can form the first connecting electrode CNEc. The second photoresist layer PR2 can be removed.

[0357] refer to Figure 13C The manufacturing method of the display panel may include forming an intermediate layer IML and a second electrode EL2 (or cathode) on a connecting electrode CNEc and a pixel defining layer PDLa. Each of the formation of the intermediate layer IML and the formation of the second electrode EL2 can be performed by a deposition process.

[0358] The intermediate layer IML can be patterned via the tip portion TPc of the connecting electrode CNEc, and a portion of the intermediate layer IML can be disposed in the groove GV. The portion of the intermediate layer IML separated from the intermediate layer IML by the tip portion TPc of the connecting electrode CNEc can be defined as a first separator pattern PP1a. The first separator pattern PP1a can comprise the same material as the intermediate layer IML, and the first separator pattern PP1a can be formed substantially simultaneously with the intermediate layer IML in a single process.

[0359] The second electrode EL2 can be patterned via the tip portion TPc of the connecting electrode CNEc, and a portion of the second electrode EL2 can be disposed in the groove GV. The portion of the second electrode EL2 separated from the second electrode EL2 by the tip portion TPc of the connecting electrode CNEc can be defined as a second separator pattern PP2a. The second separator pattern PP2a can comprise the same material as the second electrode EL2, and the second separator pattern PP2a can be formed substantially simultaneously with the second electrode EL2 in a single process. The first separator pattern PP1a and the second separator pattern PP2a can form a dummy pattern DMPc.

[0360] Although embodiments of the present disclosure have been described, it is understood that the disclosure should not be limited to these embodiments, but rather that various changes and modifications can be made by those skilled in the art within the spirit and scope of the disclosure. Therefore, the subject matter disclosed should not be limited to the embodiments described herein.

Claims

1. A display panel, characterized in that, The display panel includes: The driving element layer includes a pixel driving section; A light-emitting element is disposed on the driving element layer, and the light-emitting element includes: First electrode; An intermediate layer is disposed on the first electrode; and The second electrode is disposed on the intermediate layer; A pixel defining layer is disposed on the driving element layer, and the pixel defining layer includes a light-emitting opening and a groove surrounding the light-emitting opening; and A connecting electrode is disposed on the pixel defining layer, and the connecting electrode is electrically connected to the pixel driving part and the second electrode.

2. The display panel according to claim 1, characterized in that, The light-emitting opening exposes at least a portion of the first electrode. The light-emitting element includes multiple light-emitting elements. The pixel driving unit includes multiple pixel driving units. The connection electrode includes multiple connection electrodes. The plurality of connecting electrodes electrically connect the plurality of light-emitting elements to the plurality of pixel driving units respectively, and The gaps between adjacent connecting electrodes among the plurality of connecting electrodes overlap with the groove.

3. The display panel according to claim 1, characterized in that, The light-emitting opening exposes at least a portion of the first electrode. The connecting electrode includes: First edge; and The second edge surrounds the first edge, and The second edge overlaps with the groove.

4. The display panel according to claim 1, characterized in that, The light-emitting opening exposes at least a portion of the first electrode. In the region adjacent to the groove, the second electrode is electrically connected to the connecting electrode.

5. The display panel according to claim 1, characterized in that, The light-emitting opening exposes at least a portion of the first electrode. The connecting electrode includes a pointed portion protruding from the end of the groove, and In the plan view, the connecting electrode overlaps with the groove of the pixel defining layer.

6. The display panel according to claim 5, characterized in that, The second electrode is electrically connected to the connecting electrode at the tip portion.

7. The display panel according to claim 5, characterized in that, The via is further defined through the pixel defining layer, and The connection electrode is electrically connected to the pixel driving unit through the through hole.

8. The display panel according to claim 5, characterized in that, The connecting electrode includes: A first connecting electrode layer is disposed on the pixel defining layer; and A second connecting electrode layer is disposed on the first connecting electrode layer, and The second connecting electrode layer covers the first connecting electrode layer.

9. The display panel according to claim 8, characterized in that, The intermediate layer is disposed on the second connecting electrode layer. The second electrode is disposed on the intermediate layer, and The second electrode is electrically connected to the second connecting electrode layer at the tip portion.

10. The display panel according to claim 8, characterized in that, The display panel also includes: First dividing pattern; The second dividing pattern; and The third dividing pattern, in which... The first dividing pattern, the second dividing pattern, and the third dividing pattern are disposed in the groove. The first dividing pattern is electrically connected to the third dividing pattern.

11. The display panel according to claim 1, characterized in that, The light-emitting opening exposes at least a portion of the first electrode. The connection electrode includes a first connection electrode layer disposed on the pixel defining layer, and The intermediate layer covers the first connecting electrode layer. The display panel further includes: a first dividing pattern; and a second dividing pattern. The first dividing pattern and the second dividing pattern are disposed in the groove.

12. The display panel according to claim 1, characterized in that, The light-emitting opening exposes at least a portion of the first electrode. The pixel definition layer includes: The first pixel-defined layer portion; and The second pixel defining layer portion is disposed on the first pixel defining layer portion, the first pixel defining layer portion and the second pixel defining layer portion are integral, and the groove is defined in the second pixel defining layer portion.

13. A display panel, characterized in that, The display panel includes: The driving element layer includes a pixel driving section; The light-emitting element is disposed on the driving element layer; A pixel defining layer is disposed on the driving element layer, and the pixel defining layer includes a groove formed by removing a portion of the pixel defining layer in the thickness direction of the pixel defining layer; and A connecting electrode is disposed on the pixel defining layer, and the connecting electrode includes a pointed portion protruding from the end of the groove.

14. The display panel according to claim 13, characterized in that, The light-emitting element includes: a first electrode; an intermediate layer disposed on the first electrode; and a second electrode disposed on the intermediate layer. The pixel defining layer further includes a light-emitting opening that exposes at least a portion of the first electrode, and The groove surrounds the light-emitting opening.

15. The display panel according to claim 13, characterized in that, The light-emitting element includes: a first electrode; an intermediate layer disposed on the first electrode; and a second electrode disposed on the intermediate layer. The connecting electrode electrically connects the pixel driving unit to the second electrode, and The second electrode is electrically connected to the connecting electrode at the tip portion.

16. The display panel according to claim 13, characterized in that, A via is defined through the pixel defining layer, and The connection electrode is electrically connected to the pixel driving unit through the through hole.

17. The display panel according to claim 13, characterized in that, The light-emitting element includes multiple light-emitting elements. The pixel driving unit includes multiple pixel driving units. The connection electrode includes multiple connection electrodes. The plurality of connecting electrodes electrically connect the plurality of light-emitting elements to the plurality of pixel driving units respectively, and The gaps between adjacent connecting electrodes among the plurality of connecting electrodes overlap with the groove.

18. The display panel according to claim 13, characterized in that, The connecting electrode includes: First edge; and The second edge surrounds the first edge, and The second edge overlaps with the groove.

19. The display panel according to claim 13, characterized in that, The light-emitting element includes: a first electrode; an intermediate layer disposed on the first electrode; and a second electrode disposed on the intermediate layer. The connecting electrode includes: A first connecting electrode layer is disposed on the pixel defining layer; and The second connecting electrode layer is disposed on the first connecting electrode layer. The second connection electrode layer covers the first connection electrode layer, and The second electrode is electrically connected to the second connecting electrode layer at the tip portion.

20. The display panel according to claim 19, characterized in that, The display panel also includes: First dividing pattern; The second dividing pattern; and The third dividing pattern, in which... The first dividing pattern, the second dividing pattern, and the third dividing pattern are disposed in the groove, and The first dividing pattern is electrically connected to the third dividing pattern.

21. The display panel according to claim 13, characterized in that, The light-emitting element includes: a first electrode; an intermediate layer disposed on the first electrode; and a second electrode disposed on the intermediate layer. The connection electrode includes a first connection electrode layer disposed on the pixel defining layer, and The intermediate layer covers the first connecting electrode layer. The display panel further includes: a first dividing pattern; and a second dividing pattern. The first dividing pattern and the second dividing pattern are disposed in the groove.

22. The display panel according to claim 13, characterized in that, The pixel definition layer includes: The first pixel-defined layer portion; and The second pixel defining layer portion is disposed on the first pixel defining layer portion, the first pixel defining layer portion and the second pixel defining layer portion are integral, and the groove is defined in the second pixel defining layer portion.

Images