Riser expansion card, server mainboard and server

Abstract

The embodiment of the utility model discloses a Riser expansion card, a server mainboard and a server. An MCU (Microprogrammed Control Unit) chip, a plurality of PCIe (Peripheral Component Interconnect Express) slots and a plurality of PCIe high-speed signal connectors in the Riser expansion card are all arranged on an expansion card body; each PCIe slot in the plurality of PCIe slots is connected with a corresponding PCIe high-speed signal connector in the plurality of PCIe high-speed signal connectors; and each PCIe high-speed signal connector in the plurality of PCIe high-speed signal connectors is also connected with the MCU chip. According to the embodiment of the utility model, the Riser expansion card is provided with a plurality of PCIe high-speed signal connectors which are connected with the mainboard end, so that the docking interface of the Riser expansion card and the mainboard can be standardized, and free docking with the mainboard can be realized.

Description

TECHNICAL FIELD

[0001] The utility model relates to server technical field especially riser expansion card, server mainboard and server. BACKGROUND

[0002] Riser card (a kind of expansion card for providing PCIe card interface, wherein PCIe is the full name of Peripheral Component Interconnect Express and indicates high-speed serial computer expansion bus standard) as an important component of server, Riser card is inserted on server mainboard, and PCIe signal is switched over. The design mode of one kind of Riser card in prior art is as shown in Figure 1 Riser card 1 is connected on 1 slot of mainboard 2, then PCIe signal is split and 3 PCIe slots are provided outward, PCIe AIC device 3 (AIC in PCIe AIC represents Add in card, and it is the most common PCIe interface form, and PCIe AIC device is the device supporting PCIe AIC interface), such as network card, RAID card (the full name of RAID is Redundant Array of Independent Disk, indicating independent redundant disk array) etc.

[0003] As shown in Figure 1 Riser card is connected on mainboard, and Riser card can usually provide 1, 2 or 3 (quantity according to the demand of specific project), corresponding 1, 2 or 3 PCIe AIC devices can be docked.

[0004] PCIe bandwidth provided by mainboard is x32, Riser card provides 2 PCIe slots and is respectively recorded as SLOT1 slot and SLOT2 slot, Riser card can provide ID signal 00 to the BMC (the full name is Baseboard Management Controller, indicating baseboard management controller) of mainboard, when mainboard is started, BIOS (the full name is Basic Input Output System, indicating basic input output system) obtains ID value through BMC, and the PCIe port P1 and P2 of CPU (the full name is Central Processing Unit, indicating central processor) are configured to PCIe x16 output respectively, and are transmitted to Riser card through golden finger to be connected to SLOT1 slot and SLOT2 slot respectively.

[0005] For example, the Riser card provides three PCIe slots, and the Riser card provides an ID signal 01 to the BMC of the motherboard. When the motherboard is powered on, the BIOS obtains the ID value through the BMC, the PCIe port P1 of the CPU is configured as PCIe x16 output, the PCIe port P2 is configured as two PCIe x8 outputs, and the Riser card is connected to the SLOT3 slot, the SLOT2 slot and the SLOT1 slot of the Riser card through the golden finger.

[0006] However, the existing Riser card is usually distinguished by the configuration of the ID pin. The BIOS of the motherboard identifies the ID number of the Riser card, and then configures the PCIe port of the CPU. However, the above-mentioned method does not form a standard. For example, when the Riser card ID is 00, there are two SLOT slots on the Riser card in a certain motherboard design, and the PCIe bandwidth of each SLOT slot is x16. However, in another motherboard design, there are three or one SLOT slots on the Riser card, and the PCIe bandwidth of the SLOT slot may be x16 or x8, which is completely determined by the designer. This limits the Riser card to become a standard product, and limits a Riser card to be used in multiple projects or multiple motherboards. Inventive content

[0007] Embodiments of the utility model provide a Riser expansion card, a server motherboard and a server, and aim to solve the problems in the prior art that the Riser card is connected to the motherboard through a golden finger, the motherboard cannot quickly distinguish the model of the Riser card when the number of slots on the Riser card is different, the Riser card cannot be quickly adapted, and the Riser card is limited to be used in multiple projects or multiple motherboards.

[0008] In a first aspect, the utility model provides a Riser expansion card, which comprises: an expansion card body, an MCU chip, a plurality of PCIe slots and a plurality of PCIe high-speed signal connectors; the MCU chip, the plurality of PCIe slots and the plurality of PCIe high-speed signal connectors are all arranged on the expansion card body; the total number of PCIe slots in the plurality of PCIe slots is the same as the total number of PCIe high-speed signal connectors in the plurality of PCIe high-speed signal connectors, and each PCIe slot in the plurality of PCIe slots is connected with a corresponding PCIe high-speed signal connector in the plurality of PCIe high-speed signal connectors; and each PCIe high-speed signal connector in the plurality of PCIe high-speed signal connectors is further connected with the MCU chip.

[0009] In a second aspect, the utility model embodiment further provides a server mainboard, it includes the riser expansion card as above described first aspect, still include mainboard end, be equipped with a plurality of mainboard high speed connector on the mainboard end, a plurality of mainboard high speed connector with a plurality of PCIe high speed signal connector in the riser expansion card are connected through high speed cable.

[0010] In a third aspect, the utility model embodiment further provides a server, it is the server mainboard as above described first aspect, still include server body, the server mainboard is located in the server body.

[0011] The utility model embodiment provides riser expansion card, server mainboard and server, including expansion card body, MCU chip, a plurality of PCIe slot and a plurality of PCIe high speed signal connector, MCU chip, a plurality of PCIe slot and a plurality of PCIe high speed signal connector all are equipped on expansion card body, the total number of PCIe slot in a plurality of PCIe slot is same with the total number of PCIe high speed signal connector in a plurality of PCIe high speed signal connector, and every PCIe slot in a plurality of PCIe slot is connected with corresponding one PCIe high speed signal connector in a plurality of PCIe high speed signal connector, every PCIe high speed signal connector in a plurality of PCIe high speed signal connector still is connected with MCU chip, in the utility model embodiment, through the setting a plurality of PCIe high speed signal connector of riser expansion card with mainboard end connection, can make riser expansion card and mainboard docking interface standardization, and realize and mainboard's free docking. BRIEF DESCRIPTION OF DRAWINGS

[0012] In order to more clearly illustrate the utility model embodiment technical scheme, below will to the drawing needed to be used in the embodiment description simple introduction, obviously, the drawing in the following description is some embodiments of the utility model, for those skilled in the art, under the premise of not paying creative labor, still can obtain other drawings according to these drawings.

[0013] Figure 1 It is the structural schematic diagram of the riser card in prior art and is connected on the mainboard;

[0014] Figure 2 It is the schematic block diagram of the riser expansion card provided by the utility model embodiment;

[0015] Figure 3 It is the circuit schematic diagram of the connecting circuit between MCU chip and first PCIe high speed signal connector in the riser expansion card provided by the utility model embodiment;

[0016] Figure 4The utility model provides a schematic block diagram of server mainboard.

[0017] Figure 5 The utility model provides a circuit schematic view of the connecting circuit between the riser expansion card and the mainboard end in the server mainboard. DETAILED DESCRIPTION

[0018] The technical solutions in the embodiments of the utility model will be clearly and completely described below with reference to the drawings in the embodiments of the utility model. Obviously, the described embodiments are part of the embodiments of the utility model and not all the embodiments. Based on the embodiments in the utility model, all the other embodiments obtained by the ordinary skilled in the art without creative labor fall within the scope of the utility model.

[0019] It should be understood that when used in the specification and the appended claims, the terms "comprise" and "include" indicate the presence of described features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0020] It should also be understood that the terms used in this utility model specification are only for the purpose of describing specific embodiments and are not intended to limit the utility model. As used in the utility model specification and the appended claims, the singular forms "a", "an" and "the" are intended to include the plural forms unless the context clearly indicates otherwise.

[0021] It should be further understood that the term "and / or" used in the utility model specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes these combinations.

[0022] As Figure 2 shown, Figure 2The utility model provides an illustrative block diagram of the Riser expansion card. The Riser expansion card 10 comprises an expansion card body 11, an MCU chip 12, a plurality of PCIe slots 13 and a plurality of PCIe high-speed signal connectors 14. The MCU chip 12, the plurality of PCIe slots 13 and the plurality of PCIe high-speed signal connectors 14 are all arranged on the expansion card body 11. The total number of PCIe slots in the plurality of PCIe slots 13 is the same as the total number of PCIe high-speed signal connectors in the plurality of PCIe high-speed signal connectors 14, and each PCIe slot in the plurality of PCIe slots 13 is connected to a corresponding PCIe high-speed signal connector in the plurality of PCIe high-speed signal connectors 14. Each PCIe high-speed signal connector in the plurality of PCIe high-speed signal connectors 14 is also connected to the MCU chip 12.

[0023] In the embodiment, the Riser expansion card 10 is no longer connected to the motherboard end 20 by using a golden finger, but is connected to the motherboard end 20 by the plurality of PCIe high-speed signal connectors 14 on the expansion card body 11. At the same time, a plurality of motherboard high-speed connectors are also arranged on the motherboard end 20, and the plurality of motherboard high-speed connectors are connected to the plurality of PCIe high-speed signal connectors 14 in the Riser expansion card 10 through high-speed cables. Moreover, the MCU chip 12 arranged on the expansion card body 11 can be used as a terminal of a PESTI signal line (PESTI stands for Peripheral Sideband Tunneling Interface, which means peripheral device sideband tunneling interface), and the motherboard end 20 is used as a source end of the PESTI signal line. The description information of the Riser expansion card 10 is stored in the MCU chip 12. When the motherboard end 20 is powered on, the motherboard end 20 reads the description information corresponding to the Riser expansion card 10 stored in the MCU chip 12 through the PESTI signal line. The description information is transmitted back to the BMC (i.e., baseboard management controller) of the motherboard end 20, and the BIOS (i.e., basic input / output system) of the motherboard end 20 configures the PCIe port of the CPU chip in the motherboard end 20 according to the description information obtained by the BMC, thereby completing the adaptation with the Riser expansion card 10. It can be seen that, by arranging a plurality of PCIe high-speed signal connectors on the Riser expansion card and connecting the PCIe high-speed signal connectors to the motherboard end, the standardization of the docking interface of the Riser expansion card and the motherboard can be realized, and the free docking with the motherboard can be achieved.

[0024] In an embodiment, as shown in Figure 2As shown, the plurality of PCIe high-speed signal connectors 14 include a first PCIe high-speed signal connector 141 and a second PCIe high-speed signal connector 142, and the plurality of PCIe slots 13 include a first PCIe slot 131 and a second PCIe slot 132; the first PCIe slot 131 is connected to the first PCIe high-speed signal connector 141 through a first PCIe bus 1311, and the second PCIe slot 132 is connected to the second PCIe high-speed signal connector 142 through a second PCIe bus 1321.

[0025] In this embodiment, two PCIe high-speed signal connectors, designated as the first PCIe high-speed signal connector 141 and the second PCIe high-speed signal connector 142, are specifically provided on the Riser expansion card 10. Two PCIe slots, designated as the first PCIe slot 131 and the second PCIe slot 132, are also provided on the Riser expansion card 10. The first PCIe high-speed signal connector 141 and the second PCIe high-speed signal connector 142 employ standard PCIe high-speed signal connectors, such as SlimSAS connectors or MCIO connectors (SlimSAS connectors support PCIe GEN4 and higher transmission rates, and MCIO connectors support PCIe GEN5 and higher transmission rates; MCIO stands for Micro Coax Input / Output). More specifically, both the first PCIe high-speed signal connector 141 and the second PCIe high-speed signal connector 142 adopt MCIO connectors supporting PCIe GEN5, and the maximum supported PCIe bandwidth is x16. The first PCIe slot 131 is connected to the first PCIe high-speed signal connector 141 through a first PCIe bus 1311 with a maximum supported bandwidth of x16, and the second PCIe slot 132 is connected to the second PCIe high-speed signal connector 142 through a second PCIe bus 1321 with a maximum supported bandwidth of x16. This connection method ensures high-speed signal transmission within the Riser expansion card.

[0026] In one embodiment, such as Figure 2 As shown, the MCU chip 12 is connected to the first PCIe high-speed signal connector 141 via the first PESTI signal line 121, and is also connected to the second PCIe high-speed signal connector 142 via the second PESTI signal line 122.

[0027] In the embodiment, the MCU chip 12 is connected with the first PCIe high-speed signal connector 141 and the second PCIe high-speed signal connector 142 through two PESTI signal lines respectively, the MCU chip 12 as the terminal of the PESTI signal line can be quickly read into the MCU chip 12 by the corresponding source end of the mainboard end 20 to store the description information corresponding to the Riser expansion card 10. Moreover, the MCU chip 12 and the corresponding source end of the mainboard end 20 both support the M-PESTI protocol (M-PESTI stands for Modular-Peripheral Sideband Tunneling Interface, which means modular peripheral sideband tunneling interface). Through the above setting, the standardization of the docking between the Riser expansion card and the mainboard end is realized, and the free docking with the mainboard supporting the M-PESTI protocol is realized.

[0028] In an embodiment, as shown in Figure 3 the M-PESTI pin of the MCU chip 12 is connected with the first PCIe high-speed signal connector 141 through the first resistor R1; the GPIO pin of the MCU chip 12 is connected with the first PCIe high-speed signal connector 141 and also connected with the first end of the second resistor R2; the second end of the second resistor R2 is connected with the 3.3V power supply and also connected with the first end of the third resistor R3; the second end of the third resistor R3 is grounded; the GPIO pin of the MCU chip 12 is also connected with the 3.3V power supply through the fourth resistor R4, and also connected with the gate of the first MOS tube Q1; the source of the first MOS tube Q1 is connected with the 3.3V power supply, the drain of the first MOS tube Q1 is also grounded through the fifth resistor R5, and also connected with the first PCIe high-speed signal connector 141 through the sixth resistor R6.

[0029] In the embodiment, the circuit connection relationship between the MCU chip 12 and the first PCIe high-speed signal connector 141 is taken as an example to be described, the circuit connection relationship between the MCU chip 12 and the second PCIe high-speed signal connector 142 is completely same as the circuit connection relationship between the MCU chip 12 and the first PCIe high-speed signal connector 141 in the above example, and will not be described again. The first resistor R1 can be used for signal impedance adjustment and test point in the debugging process, the second resistor R2, the third resistor R3, the fifth resistor R5 and the sixth resistor R6 are used for signal pull-down, the sixth resistor R6 provides a rising time of high level for a drain open port corresponding to the M-PESTI pin of the MCU chip 12, and the fifth resistor R5 provides a path to the ground for the current generated in the signal pull-up process. Moreover, the first MOS tube Q1 is driven by the MCU chip 12, when the MCU chip 12 has completed preparation and can respond to the discovery request of the mainboard end, the MCU chip 12 outputs low level to make the first MOS tube Q1 conduct. When the mainboard end detects that the PESTI signal corresponding to the M-PESTI pin jumps from low level to high level, it is determined that the locking of the MCU chip 12 has been released, and data transmission can be carried out between the MCU chip 12 and the mainboard end. It can be seen that the data transmission process between the Riser expansion card and the mainboard end is precisely controlled through the above circuit structure.

[0030] The MCU chip 12 also stores 2 32-byte register values, one of which is used for the mainboard end to read through the signal S0_PESTI_A_N, and the other is used for the mainboard end to read through the signal S1_PESTI_A_N.

[0031] It can be seen that the embodiment of the Riser expansion card in the application can standardize the Riser expansion card and the mainboard docking interface by arranging a plurality of PCIe high-speed signal connectors on the Riser expansion card and connecting the Riser expansion card with the mainboard, and free docking with the mainboard can be realized.

[0032] The embodiment of the utility model further provides a kind of server mainboard. Please refer to Figure 4 , Figure 4 The embodiment of the utility model provides the schematic diagram of server mainboard. As Figure 4 Indicated, the server mainboard 100 includes the Riser expansion card 10 described in any of the preceding embodiments, further include mainboard end 20, the mainboard end 20 is equipped with a plurality of mainboard high-speed connector 21, the plurality of mainboard high-speed connector 21 with the plurality of PCIe high-speed signal connectors in the Riser expansion card 10 is connected by high-speed cable 25.

[0033] In this embodiment, the Riser expansion card 10 no longer uses gold fingers to connect to the motherboard 20. Instead, it connects to the motherboard 20 via several PCIe high-speed signal connectors 14 on the expansion card body 11. Simultaneously, several motherboard high-speed connectors 21 are also correspondingly provided on the motherboard 20. These motherboard high-speed connectors 21 are connected to the several PCIe high-speed signal connectors 14 in the Riser expansion card 10 via high-speed cables 25. Therefore, by setting several PCIe high-speed signal connectors on the Riser expansion card to connect to the motherboard high-speed connectors, the interface between the Riser expansion card and the motherboard can be standardized, enabling free docking with the motherboard.

[0034] In one embodiment, such as Figure 4 As shown, the motherboard 20 also includes a complex programmable logic device 22, a baseboard management controller 23, and a CPU chip 24; the baseboard management controller 23 is connected to the complex programmable logic device 22; the complex programmable logic device 22 is connected to the plurality of motherboard high-speed connectors 21; and the CPU chip 24 is connected to the plurality of PCIe high-speed signal connectors 21.

[0035] In this embodiment, the complex programmable logic device 22 in the motherboard 20 is connected to the plurality of motherboard high-speed connectors 21, and the baseboard management controller 23 is connected to the complex programmable logic device 22. The CPU chip 24 is connected to the plurality of PCIe high-speed signal connectors 21. The MCU chip 12 disposed on the expansion card body 11 can be used as the terminal of the PESTI signal line, and the complex programmable logic device 22 in the motherboard 20 is used as the source of the PESTI signal line. The MCU chip 12 stores the description information of the Riser expansion card 10. When the motherboard 20 is powered on, the complex programmable logic device 22 in the motherboard 20 reads the description information corresponding to the Riser expansion card 10 stored in the MCU chip 12 through the PESTI signal line. This description information is then sent back to the baseboard management controller 23 in the motherboard 20. The BIOS (i.e., basic input / output system) of the motherboard 20 configures the PCIe port of the CPU chip 24 in the motherboard 20 according to the description information obtained by the baseboard management controller 23, thereby completing the adaptation with the Riser expansion card 10.

[0036] Finally, the BIOS of the mainboard end 20 obtains the description information of the Riser expansion card 10 stored in the MCU chip 12, and the configuration of the PCIe port of the CPU chip 24 is completed. Since the mainboard supporting the M-PESTI interface can directly access the description information of the Riser expansion card in the MCU chip of the Riser expansion card, the Riser expansion card can realize one card with multiple uses, that is, the Riser expansion card can be used in multiple projects or multiple servers.

[0037] In an embodiment, as shown in Figure 4 The plurality of mainboard high-speed connectors 21 include a first mainboard high-speed connector 211, a second mainboard high-speed connector 212, a third mainboard high-speed connector 213, and a fourth mainboard high-speed connector 214; the plurality of PCIe high-speed signal connectors 14 include a first PCIe high-speed signal connector 141 and a second PCIe high-speed signal connector 142; the first mainboard high-speed connector 211 and the second mainboard high-speed connector 212 are connected with the first PCIe high-speed signal connector 141 through a first Y-shaped high-speed cable 251 in the high-speed cable 25, and the third mainboard high-speed connector 213 and the fourth mainboard high-speed connector 214 are connected with the second PCIe high-speed signal connector 142 through a second Y-shaped high-speed cable 252 in the high-speed cable 25.

[0038] In the embodiment, two PCIe high-speed signal connectors are arranged on the riser expansion card 10, and are respectively denoted as a first PCIe high-speed signal connector 141 and a second PCIe high-speed signal connector 142. Four mainboard high-speed connectors are arranged on the mainboard end 20, and are respectively denoted as a first mainboard high-speed connector 211, a second mainboard high-speed connector 212, a third mainboard high-speed connector 213 and a fourth mainboard high-speed connector 214. The first PCIe high-speed signal connector 141 and the second PCIe high-speed signal connector 142 are standard PCIe high-speed signal connectors, such as SlimSAS connectors or MCIO connectors. Similarly, the first mainboard high-speed connector 211, the second mainboard high-speed connector 212, the third mainboard high-speed connector 213 and the fourth mainboard high-speed connector 214 are also standard PCIe high-speed signal connectors, such as SlimSAS connectors or MCIO connectors. More specifically, the first PCIe high-speed signal connector 141 and the second PCIe high-speed signal connector 142 are MCIO connectors supporting PCIe GEN5, and the maximum supported PCIe bandwidth is x16. The first mainboard high-speed connector 211, the second mainboard high-speed connector 212, the third mainboard high-speed connector 213 and the fourth mainboard high-speed connector 214 are MCIO connectors supporting PCIe GEN5, and the maximum supported PCIe bandwidth is x8. Through the above connection mode, high-speed transmission of signals in the riser expansion card can be ensured, and high-speed transmission of signals between the riser expansion card and the mainboard end can also be ensured.

[0039] In an embodiment, as shown in FIG. 2, the CPU chip 24 is connected with the first mainboard high-speed connector 211 and the second mainboard high-speed connector 212 through a third PCIe bus 241, and is also connected with the third mainboard high-speed connector 213 and the fourth mainboard high-speed connector 214 through a fourth PCIe bus 242. Figure 4

[0040] In the embodiment, the first mainboard high-speed connector 211 and the second mainboard high-speed connector 212 are connected with a PCIe port P1 of the CPU chip 24 through the third PCIe bus 241, and the third mainboard high-speed connector 213 and the fourth mainboard high-speed connector 214 are connected with a PCIe port P2 of the CPU chip 24 through the fourth PCIe bus 242. Through the above connection mode, high-speed transmission of signals in the mainboard end can be ensured.

[0041] In an embodiment, as shown in FIG. 2, the CPU chip 24 is connected with the first mainboard high-speed connector 211 and the second mainboard high-speed connector 212 through a third PCIe bus 241, and is also connected with the third mainboard high-speed connector 213 and the fourth mainboard high-speed connector 214 through a fourth PCIe bus 242. Figure 4 and Figure 5 ​As shown, the CPLD_M-PESTI_0 pin of the complex programmable logic device 22 is connected with the first end of the seventh resistor R7; the second end of the seventh resistor R7 is connected with the first mainboard high-speed connector 211, and is also connected with the 3.3V power supply through the eighth resistor R8; the CPLD_M-PESTI_1 pin of the complex programmable logic device 22 is connected with the first end of the ninth resistor R9; the second end of the ninth resistor R9 is connected with the second mainboard high-speed connector 212, and is also connected with the 3.3V power supply through the tenth resistor R10.

[0042] In the embodiment, the circuit connection relationship between the MCU chip 12 and the first PCIe high-speed signal connector 141, and the circuit connection relationship between the complex programmable logic device 22 and the first mainboard high-speed connector 211 and the second mainboard high-speed connector 212 are taken as examples for illustration, the circuit connection relationship between the MCU chip 12 and the second PCIe high-speed signal connector 142 is exactly the same as the circuit connection relationship between the MCU chip 12 and the first PCIe high-speed signal connector 141 in the above example, and the circuit connection relationship between the complex programmable logic device 22 and the third mainboard high-speed connector 213 and the fourth mainboard high-speed connector 214 will not be described herein again. Among them, the first resistor R1, the seventh resistor R7 and the ninth resistor R9 can be used for signal impedance adjustment and test points in the debugging process, the second resistor R2, the third resistor R3, the fifth resistor R5 and the sixth resistor R6 are used for pulling down the signal in the Riser expansion card, the eighth resistor R8 and the tenth resistor R10 are used for pulling up the signal at the mainboard end (preferably a larger resistance value is selected to reduce the current, and the signal level also needs to be ensured), and the sixth resistor R6 provides a high-level rising time for the drain open port corresponding to the M-PESTI pin of the MCU chip 12, and the fifth resistor R5 provides a path to the ground for the current generated in the eighth resistor R8 pulling up process. Moreover, the first MOS tube Q1 is driven by the MCU chip 12, when the MCU chip 12 has completed the preparation and can respond to the discovery request of the complex programmable logic device 22 at the mainboard end, the MCU chip 12 outputs a low level to make the first MOS tube Q1 conductive. When the complex programmable logic device 22 at the mainboard end detects that the PESTI signal corresponding to the M-PESTI pin (such as the CPLD_M-PESTI_0, CPLD_M-PESTI_1 pin, etc.) jumps from low level to high level, it is determined that the lock of the MCU chip 12 has been released, and data transmission between the MCU chip 12 and the mainboard end can be performed. It can be seen that through the above circuit structure, the data transmission process between the Riser expansion card and the mainboard end is precisely controlled.

[0043] The MCU chip 12 further stores two 32 Byte register values, one of which is read by the mainboard end 20 through a signal S0_PESTI_A_N, and the other of which is read by the mainboard end 20 through a signal S1_PESTI_A_N.

[0044] It can be seen that the server mainboard in the application can standardize the docking interface of the riser expansion card and the mainboard and realize free docking with the mainboard by connecting the riser expansion card with the corresponding mainboard high-speed signal connector on the mainboard end through a plurality of PCIe high-speed signal connectors arranged on the riser expansion card.

[0045] The embodiment of the utility model further provides a kind of server.The server includes the server mainboard described in any one embodiment, further include server body;The server mainboard is located in the server body.

[0046] It should be explained that the skilled in the art can clearly understand the specific implementation process of the above server and components, which can be referred to the corresponding description in the foregoing server mainboard embodiments, and for the convenience and brevity of description, it will not be repeated here.

[0047] The above is only a specific implementation manner of the utility model, but the protection scope of the utility model is not limited to this, and anyone skilled in the art can easily think of various equivalent modifications or replacements within the technical range disclosed by the utility model, and these modifications or replacements should be covered in the protection scope of the utility model. Therefore, the protection scope of the utility model should be subject to the protection scope of claims.

Claims

1. A Riser expansion card, characterized by, The riser expansion card comprises a riser expansion card body, an MCU chip, a plurality of PCIe slots and a plurality of PCIe high-speed signal connectors; the MCU chip, the plurality of PCIe slots and the plurality of PCIe high-speed signal connectors are arranged on the riser expansion card body; the total number of PCIe slots in the plurality of PCIe slots is the same as the total number of PCIe high-speed signal connectors in the plurality of PCIe high-speed signal connectors, and each PCIe slot in the plurality of PCIe slots is connected with a corresponding PCIe high-speed signal connector in the plurality of PCIe high-speed signal connectors; and each PCIe high-speed signal connector in the plurality of PCIe high-speed signal connectors is further connected with the MCU chip. The plurality of PCIe high-speed signal connectors comprises a first PCIe high-speed signal connector and a second PCIe high-speed signal connector, and the plurality of PCIe slots comprises a first PCIe slot and a second PCIe slot; the first PCIe slot is connected with the first PCIe high-speed signal connector through a first PCIe bus, and the second PCIe slot is connected with the second PCIe high-speed signal connector through a second PCIe bus.

2. The Riser Expansion Card of claim 1, wherein, The MCU chip is connected with the first PCIe high-speed signal connector through a first PESTI signal line, and is further connected with the second PCIe high-speed signal connector through a second PESTI signal line.

3. The Riser Expansion Card of claim 2, wherein, An M-PESTI pin of the MCU chip is connected with the first PCIe high-speed signal connector through a first resistor; a GPIO pin of the MCU chip is connected with the first PCIe high-speed signal connector, and is further connected with a first end of a second resistor; a second end of the second resistor is connected with a 3.3V power supply, and is further connected with a first end of a third resistor; a second end of the third resistor is grounded; the GPIO pin of the MCU chip is further connected with the 3.3V power supply through a fourth resistor, and is further connected with a gate of a first MOS transistor; a source of the first MOS transistor is connected with the 3.3V power supply, a drain of the first MOS transistor is further grounded through a fifth resistor, and the drain of the first MOS transistor is further connected with the first PCIe high-speed signal connector through a sixth resistor.

4. The Riser expansion card of claim 3, wherein, The riser expansion card further comprises a mainboard end; a plurality of mainboard high-speed connectors are arranged on the mainboard end, and the plurality of mainboard high-speed connectors are connected with the plurality of PCIe high-speed signal connectors in the riser expansion card through high-speed cables.

5. A server motherboard, characterized by, The mainboard end further comprises a complex programmable logic device, a baseboard management controller and a CPU chip; the baseboard management controller is connected with the complex programmable logic device; the complex programmable logic device is connected with the plurality of mainboard high-speed connectors; and the CPU chip is connected with the plurality of PCIe high-speed signal connectors.

6. The server motherboard of claim 5, wherein, ​ 7. The server motherboard of claim 6, wherein, The plurality of mainboard high-speed connectors include a first mainboard high-speed connector, a second mainboard high-speed connector, a third mainboard high-speed connector and a fourth mainboard high-speed connector; the plurality of PCIe high-speed signal connectors include a first PCIe high-speed signal connector and a second PCIe high-speed signal connector; the first mainboard high-speed connector and the second mainboard high-speed connector are connected with the first PCIe high-speed signal connector through a first Y-shaped high-speed cable in the high-speed cables, and the third mainboard high-speed connector and the fourth mainboard high-speed connector are connected with the second PCIe high-speed signal connector through a second Y-shaped high-speed cable in the high-speed cables.

8. The server motherboard of claim 7, wherein, The CPU chip is connected with the first mainboard high-speed connector and the second mainboard high-speed connector through a third PCIe bus, and is also connected with the third mainboard high-speed connector and the fourth mainboard high-speed connector through a fourth PCIe bus.

9. The server motherboard of claim 7, wherein, The CPLD_M-PESTI_0 pin of the complex programmable logic device is connected with a first end of a seventh resistor; a second end of the seventh resistor is connected with the first mainboard high-speed connector and is also connected with a 3.3V power supply through an eighth resistor; the CPLD_M-PESTI_1 pin of the complex programmable logic device is connected with a first end of a ninth resistor; a second end of the ninth resistor is connected with the second mainboard high-speed connector and is also connected with a 3.3V power supply through a tenth resistor.

10. A server, characterized by The server mainboard includes the server mainboard as claimed in any one of claims 5-9, and further includes a server body; the server mainboard is arranged in the server body.

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