Automatic rapid discharging circuit of super capacitor

Abstract

The utility model discloses a super capacitor automatic rapid discharge circuit, which comprises a system-on-chip, a super capacitor and a switching circuit, the super capacitor is connected with the system-on-chip, the switching circuit is respectively connected with the system-on-chip and the super capacitor, and the switching circuit comprises a power resistor; wherein when the system-on-chip chip is in a working state, the system-on-chip chip controls the switching circuit to be switched off, so that the super capacitor is disconnected from the power resistor; and when the system-on-chip chip is in a shutdown state, the switching circuit is switched on, so that the super capacitor is communicated with the power resistor. The automatic rapid discharge circuit of the super capacitor is simple in structure, easy to realize, low in manufacturing cost and high in reliability, and can avoid the problem that the discharge of the super capacitor cannot be controlled due to program runaway of the controller.

Description

TECHNICAL FIELD

[0001] The utility model relates to electrical technology field especially relates to a super capacitor automatic quick discharge circuit. BACKGROUND

[0002] Electronic equipment will be usually provided with super capacitor, and super capacitor is used as backup power supply, when external power supply is abnormal and power off, super capacitor is used as power supply when on-chip system chip backup data is enabled. Usually, when the on-chip system chip is powered off, the super capacitor still has residual power, and this part of residual power needs to be quickly discharged after the on-chip system chip is powered off to avoid damaging the electronic equipment.

[0003] At present, the residual power of super capacitor is usually handled by two methods: the first method is to use a large resistance and super capacitor in parallel, and discharge to ground, this method takes a long time to discharge, and cannot achieve the purpose of quick discharge; the second method needs to additionally increase a controller (MCU) and a power supply circuit, and the MCU and the power supply circuit are used to control the on-off of MOS tube or the switching of relay, so that the super capacitor is turned on with a low resistance power resistor, and quick discharge is realized, this method increases the circuit complexity and cost of the product, and the controller has the problem of being unable to control the discharge of super capacitor due to program runaway in the running process. SUMMARY

[0004] The technical problem to be solved by the utility model is to provide a super capacitor automatic quick discharge circuit to solve the problems of slow discharge speed, high cost and low reliability of the existing super capacitor discharge scheme.

[0005] In order to solve the above technical problem, the utility model adopts the technical scheme of a super capacitor automatic quick discharge circuit, which comprises an on-chip system chip, a super capacitor and a switching circuit, the super capacitor is connected with the on-chip system chip, the switching circuit is connected with the on-chip system chip and the super capacitor respectively, and the switching circuit comprises a power resistor; when the on-chip system chip is in working state, the on-chip system chip controls the switching circuit to be turned off, so that the super capacitor is disconnected with the power resistor; when the on-chip system chip is in shutdown state, the switching circuit is turned on, so that the super capacitor is connected with the power resistor.

[0006] Further, the on-chip system chip comprises a GPIO pin, the switching circuit is connected with the GPIO pin, when the on-chip system chip is in working state, the GPIO pin is pulled up to high level, so that the switching circuit is turned off, when the on-chip system chip is in shutdown state, the GPIO pin outputs low level, so that the switching circuit is turned on.

[0007] Further, the switch circuit further comprises a switch element, an input end of the switch element is connected with the system on chip, a first response end of the switch element is connected with the super capacitor, and a second response end of the switch element is connected with the power resistor.

[0008] Further, the switch element is a first MOS tube, a gate of the first MOS tube is connected with the system on chip, a source of the first MOS tube is connected with the super capacitor, and a drain of the first MOS tube is connected with the power resistor.

[0009] Further, the switch element is a relay, a control end of the relay is connected with the system on chip, and a normally closed contact structure of the relay is connected in series between the super capacitor and the power resistor.

[0010] Further, the switch circuit further comprises a signal amplification unit, the signal amplification unit comprises a second MOS tube and a triode, a gate of the second MOS tube is connected with the system on chip, a source of the second MOS tube is grounded, a drain of the second MOS tube is connected with a base of the triode, an emitter of the triode is grounded, and a collector of the triode is connected with an input end of the switch element.

[0011] Further, the switch circuit further comprises a protection unit, the protection unit comprises a first resistor and a protection capacitor, one end of the first resistor and one end of the protection capacitor are both connected with a gate of the switch element, and the other end of the first resistor and the other end of the protection capacitor are both connected in series between the super capacitor and a first response end of the switch element.

[0012] Further, the switch circuit further comprises a power supply and a charging circuit, the power supply is connected with the system on chip and the charging circuit respectively, the charging circuit is connected with the super capacitor, and the charging circuit is used for charging the super capacitor.

[0013] Further, the switch circuit further comprises a power management circuit, the power management circuit is connected with the power supply, the super capacitor and the system on chip respectively.

[0014] Further, the switch circuit further comprises a power failure detection circuit, the power failure detection circuit is connected with the power supply and the system on chip respectively.

[0015] The super capacitor automatic rapid discharging circuit has the advantages of simple structure, easy realization, low manufacturing cost, high reliability, and the like, and can avoid the problem that the program of the controller runs away and the super capacitor cannot be controlled to discharge. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1 The utility model discloses a super capacitor automatic rapid discharging circuit's circuit principle diagram for the utility model discloses a super capacitor automatic rapid discharging circuit's circuit principle diagram.

[0017] Figure 2 The utility model discloses a super capacitor automatic rapid discharging circuit's module principle diagram for the utility model discloses a super capacitor automatic rapid discharging circuit's module principle diagram.

[0018] Label explanation:

[0019] 1, system on chip;

[0020] 2, super capacitor;

[0021] 3, switch circuit; 31, signal amplification unit; 32, protection unit;

[0022] 4, power supply;

[0023] 5, charging circuit;

[0024] 6, power management circuit;

[0025] 7, power failure detection circuit. DETAILED DESCRIPTION

[0026] To explain the technical content, the purpose and effect of the utility model in detail, the following will be explained by combining with the drawings.

[0027] Please refer to Figure 1 And Figure 2The utility model provides a kind of super capacitor automatic fast discharge circuit, including system on chip 1, super capacitor 2 and switching circuit 3, the super capacitor 2 with the system on chip 1 is connected, the switching circuit 3 respectively with the system on chip 1, the super capacitor 2 is connected, the switching circuit 3 includes power resistor;Wherein, when the system on chip 1 is in working condition, the system on chip 1 controls the switching circuit 3 and is turned off, to make the super capacitor 2 with the power resistor disconnect;When the system on chip 1 is in shutdown state, the switching circuit 3 is turned on, to make the super capacitor 2 with the power resistor communication.

[0028] The utility model discloses a kind of super capacitor automatic fast discharge circuit, which can directly utilize system on chip 1 to control the on-off of switching circuit 3, wherein, system on chip 1 can automatically send driving signal to switching circuit 3 when in working condition, to make switching circuit 3 in off state, so that super capacitor 2 is disconnected with power resistor;When system on chip 1 is in shutdown state, system on chip 1 does not send driving signal to switching circuit 3, at this time, switching circuit 3 is in on state, so that super capacitor 2 is communicated with power resistor, and super capacitor 2 is discharged quickly by power resistor.The structure of the super capacitor automatic fast discharge circuit provided by the utility model is simple and easy to implement, with low manufacturing cost and high reliability, which can avoid the problem of controller program running away and being unable to control super capacitor 2 discharge.

[0029] Further, the system on chip 1 includes GPIO pin, and the switching circuit 3 is connected with the GPIO pin;When the system on chip 1 is in working condition, the GPIO pin is pulled up to high level, to make the switching circuit 3 turn off;When the system on chip 1 is in shutdown state, the GPIO pin outputs low level, to make the switching circuit 3 turn on.

[0030] As described above, the super capacitor automatic fast discharge circuit can control the on-off of switching circuit 3 by using the GPIO pin with internal pull-up property of system on chip 1;Wherein, when system on chip 1 is powered on and works, GPIO pin outputs high level, to make switching circuit 3 disconnect;When system on chip 1 is powered off, GPIO pin jumps from high level to low level, to make switching circuit 3 turn on, and super capacitor 2 is communicated with power resistor, so that super capacitor 2 is discharged quickly by power resistor.

[0031] Further, the switching circuit 3 further includes a switching element, an input end of the switching element is connected with the system on chip 1, a first response end of the switching element is connected with the super capacitor 2, and a second response end of the switching element is connected with the power resistor.

[0032] Further, the switch element is a first MOS tube, a gate of the first MOS tube is connected with the system on chip 1, a source of the first MOS tube is connected with the super capacitor 2, and a drain of the first MOS tube is connected with the power resistor.

[0033] Further, the switch element is a relay, a control end of the relay is connected with the system on chip 1, and a normally closed contact structure of the relay is connected in series between the super capacitor 2 and the power resistor.

[0034] From the above description, it can be known that the switch element can be selected at least from a MOS tube or a relay.

[0035] Further, the switch circuit 3 further comprises a signal amplification unit 31, the signal amplification unit 31 comprises a second MOS tube and a triode, a gate of the second MOS tube is connected with the system on chip 1, a source of the second MOS tube is grounded, a drain of the second MOS tube is connected with a base of the triode, an emitter of the triode is grounded, and a collector of the triode is connected with an input end of the switch element.

[0036] From the above description, it can be known that when the system on chip 1 is in a working state, the signal amplification unit 31 can amplify the electrical signal received by the switch circuit 3, thereby improving the reliability of the switch circuit 3.

[0037] Further, the switch circuit 3 further comprises a protection unit 32, the protection unit 32 comprises a first resistor and a protection capacitor, one end of the first resistor and one end of the protection capacitor are both connected with a gate of the switch element, and the other end of the first resistor and the other end of the protection capacitor are both connected in series between the super capacitor 2 and a first response end of the switch element.

[0038] From the above description, it can be known that the protection unit 32 can play a protection role for the switch circuit 3.

[0039] Further, a power supply 4 and a charging circuit 5 are further included, the power supply 4 is connected with the system on chip 1 and the charging circuit 5 respectively, the charging circuit 5 is connected with the super capacitor 2, and the charging circuit 5 is used for charging the super capacitor 2.

[0040] From the above description, it can be known that the power supply 4 can supply power to the system on chip 1 and charge the super capacitor 2 at the same time.

[0041] Further, a power management circuit 6 is further included, the power management circuit 6 is connected with the power supply 4, the super capacitor 2 and the system on chip 1 respectively.

[0042] From the above description, the power management circuit 6 can improve the safety and reliability of the super capacitor 2 and the power supply 4 for supplying power to the system on chip 1.

[0043] Further, it also includes a power failure detection circuit 7, which is connected with the power supply 4 and the system on chip 1 respectively.

[0044] From the above description, when the power supply 4 abnormally powers off, the power failure detection signal can feedback the abnormal power-off signal to the system on chip 1, and the super capacitor 2 saves the power to automatically supply power to the system on chip 1, so that the system on chip 1 has enough time to save important data.

[0045] Embodiment one

[0046] Please refer to Figures 1 to 2 The embodiment one of the utility model provides a super capacitor automatic fast discharge circuit, which comprises a system on chip 1 (SOC), a super capacitor 2 and a switch circuit 3. The super capacitor 2 is connected with the system on chip 1 to serve as a backup power supply of the system on chip 1, and the switch circuit 3 is connected with the super capacitor 2 and the system on chip 1 respectively. The switch circuit 3 comprises a low-resistance power resistor RL. When the system on chip 1 is in a working state, the system on chip 1 controls the switch circuit 3 to be turned off to disconnect the super capacitor 2 and the power resistor RL. When the system on chip 1 is in a shutdown state, the switch circuit 3 is turned on to connect the super capacitor 2 and the power resistor RL, and the super capacitor 2 can be quickly discharged through the low-resistance power resistor RL.

[0047] Specifically, in the embodiment, the system on chip 1 comprises a GPIO pin, and the GPIO pin has an internal pull-up attribute after the system on chip 1 is powered on, that is, when the system on chip 1 is in a power-on state, the GPIO pin embeds an indeterminate signal at a high level, and controls the switch circuit 3 to maintain an off state through the high-level signal. At this time, the super capacitor 2 is disconnected with the power resistor RL, and the super capacitor 2 will not be discharged through the power resistor RL. When the system on chip 1 enters a shutdown state, the GPIO pin will automatically jump from a high level to a low level, and the switch circuit 3 maintains a conduction state in a state of losing high-level signal excitation after receiving the low-level signal. At this time, the super capacitor 2 is connected with the power resistor RL, and the super capacitor 2 is quickly discharged through the power resistor RL.

[0048] In the embodiment, the switch circuit 3 further comprises a switching element, the input end of the switching element is connected with the system on chip 1, the first response end of the switching element is connected with the super capacitor 2, and the second response end of the switching element is connected with the power resistor RL.

[0049] Please refer toFigure 1 In the embodiment, the switch element is a first MOS tube Q1, a gate of the first MOS tube Q1 is connected with the system on chip 1, a source of the first MOS tube Q1 is connected with the super capacitor 2, and a drain of the first MOS tube Q1 is connected with the power resistor RL.

[0050] Preferably, the first MOS tube Q1 is a P-type MOS tube, and the first MOS tube Q1 is turned off when the gate receives a high-level signal.

[0051] Of course, in other preferred embodiments of the utility model, a relay can also be used to replace the first MOS tube Q1, and when the switch element is a relay, a control end of the relay is connected with the system on chip 1, and a normally closed contact structure of the relay is connected in series between the super capacitor 2 and the power resistor RL.

[0052] In the embodiment, in order to improve the safety and reliability of the switch circuit 3, the switch circuit 3 further comprises a signal amplification unit 31 and a protection unit 32.

[0053] Specifically, further refer to Figure 1 In the embodiment, the protection unit 32 comprises a first resistor R1 and a protection capacitor C, one end of the first resistor R1 and one end of the protection capacitor C are both connected with the gate of the switch element, and the other end of the first resistor R1 and the other end of the protection capacitor C are both connected in series between the super capacitor 2 and the source of the first MOS tube Q1.

[0054] The signal amplification unit 31 comprises a second MOS tube Q2, a triode Q3, a second resistor R2, a third resistor R3, a fourth resistor R4 and a fifth resistor R5, a gate of the second MOS tube Q2 is connected with a GPIO pin of the system on chip 1, a source of the second MOS tube Q2 is grounded, a drain of the second MOS tube Q2 is connected with one end of the second resistor R2 and one end of the third resistor R3 respectively, the other end of the second resistor R2 is grounded, the other end of the third resistor R3 is connected with one end of the fourth resistor R4 and a base of the triode Q3 respectively, the other end of the fourth resistor R4 is grounded, an emitter of the triode Q3 is grounded, a collector of the triode Q3 is connected with one end of the fifth resistor R5, and the other end of the fifth resistor R5 is connected with the gate of the first MOS tube Q1.

[0055] Further refer to Figure 1 As can be seen, one end of the power resistor RL is connected with the drain of the first triode Q3, and the other end of the power resistor RL is grounded, and when the super capacitor 2 is in communication with the power resistor RL, the super capacitor 2 can quickly discharge the remaining power through the power resistor RL.

[0056] Refer to Figure 2In the embodiment, the super capacitor automatic fast discharge circuit further comprises a power supply 4, a charging circuit 5, a power management circuit 6 and a power-off detection circuit 7, the power management circuit 6 is connected with the power supply 4, the super capacitor 2 and the system on chip 1 respectively, the charging circuit 5 is connected with the power supply 4 and the super capacitor 2 respectively, and the power-off detection circuit 7 is connected with the power supply 4 and the system on chip 1 respectively.

[0057] In the embodiment, the power supply 4 can be a mains or an external energy storage power supply, which can supply power to the power management circuit 6 and the charging circuit 5 at the same time to realize power supply to the system on chip 1 and charging of the super capacitor respectively. When the voltage of the power supply 4 is normal, the super capacitor 2 does not supply power to the power management circuit 6, so as to ensure that the super capacitor 2 has sufficient power in the case of abnormal power-off of the power supply 4.

[0058] The power-off detection circuit 7 detects the abnormal power-off state of the power supply 4, and when the power-off detection circuit 7 detects the abnormal power-off of the power supply 4, an abnormal power-off signal is fed back to the system on chip 1, and at the same time, the power saved by the super capacitor 2 automatically supplies power to the power management circuit 6, so that the system on chip 1 has sufficient time to save important data.

[0059] After the system on chip 1 saves the data, the system on chip 1 enters a shutdown state, at this time, the GPIO pin of the system on chip 1 automatically jumps from high level to low level, so that the first MOS tube Q1 is turned on, the super capacitor 2 is connected with the power resistor RL, and the super capacitor 2 can quickly discharge the remaining power through the power resistor RL.

[0060] When the system on chip 1 is powered on again, the GPIO pin is high, so that the MOS tube is closed, the super capacitor 2 is disconnected with the power resistor RL, and at this time, the super capacitor 2 will not discharge.

[0061] In summary, the super capacitor automatic fast discharge circuit provided by the utility model configures the pull-up property of the GPIO pin of the system on chip 1, automatically controls the fast discharge of the super capacitor 2 by using the GPIO pin of the system on chip 1 itself, and can realize the fast discharge function of the super capacitor 2 without adding a controller and a power supply circuit. The super capacitor automatic fast discharge circuit provided by the utility model has the advantages of simple structure, easy realization, low manufacturing cost, high reliability, and can avoid the problem that the super capacitor 2 discharges due to the program runaway of the controller which cannot be controlled.

[0062] The above only describes the embodiments of the utility model, and does not limit the patent range of the utility model, and any equivalent transformation or direct or indirect application in the related technical field according to the content of the utility model specification and the drawings is also included in the patent protection range of the utility model.

Claims

1. A supercapacitor automatic fast discharge circuit, comprising a system on chip and a supercapacitor, the supercapacitor being connected with the system on chip, characterized in that, The switch circuit is connected with the system on chip and the super capacitor, and comprises a power resistor; when the system on chip is in a working state, the system on chip controls the switch circuit to be off, so that the super capacitor is disconnected with the power resistor; when the system on chip is in a shutdown state, the switch circuit is turned on, so that the super capacitor is connected with the power resistor.

2. The supercap automatic quick discharge circuit according to claim 1, wherein, The system on chip comprises a GPIO pin, and the switch circuit is connected with the GPIO pin; when the system on chip is in a working state, the GPIO pin is pulled up to a high level, so that the switch circuit is off; when the system on chip is in a shutdown state, the GPIO pin outputs a low level, so that the switch circuit is turned on.

3. The supercapacitor automatic quick discharge circuit of claim 1, wherein, The switch circuit further comprises a switching element, an input end of the switching element is connected with the system on chip, a first response end of the switching element is connected with the super capacitor, and a second response end of the switching element is connected with the power resistor.

4. The supercapacitor automatic quick discharge circuit of claim 3, wherein, The switching element is a first MOS tube, a gate of the first MOS tube is connected with the system on chip, a source of the first MOS tube is connected with the super capacitor, and a drain of the first MOS tube is connected with the power resistor.

5. The supercapacitor automatic quick discharge circuit of claim 3, wherein, The switching element is a relay, a control end of the relay is connected with the system on chip, and a normally closed contact structure of the relay is connected in series between the super capacitor and the power resistor.

6. The supercapacitor automatic quick discharge circuit of claim 3, wherein, The switch circuit further comprises a signal amplification unit, the signal amplification unit comprises a second MOS tube and a triode, a gate of the second MOS tube is connected with the system on chip, a source of the second MOS tube is grounded, a drain of the second MOS tube is connected with a base of the triode, an emitter of the triode is grounded, and a collector of the triode is connected with an input end of the switching element.

7. The supercapacitor automatic quick discharge circuit of claim 3, wherein, The switch circuit further comprises a protection unit, the protection unit comprises a first resistor and a protection capacitor, one end of the first resistor and one end of the protection capacitor are connected with a gate of the switching element, and the other end of the first resistor and the other end of the protection capacitor are connected in series between the super capacitor and a first response end of the switching element.

8. The supercapacitor automatic quick discharge circuit of claim 1, wherein, The switch circuit further comprises a power supply and a charging circuit, the power supply is connected with the system on chip and the charging circuit, the charging circuit is connected with the super capacitor, and the charging circuit is used for charging the super capacitor.

9. The supercapacitor automatic quick discharge circuit of claim 8, wherein, The switch circuit further comprises a power management circuit, the power management circuit is connected with the power supply, the super capacitor and the system on chip.

10. The supercapacitor automatic quick discharge circuit of claim 8, wherein, The switch circuit further comprises a power failure detection circuit, the power failure detection circuit is connected with the power supply and the system on chip.

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